diff --git a/nfc/libnfc-nxp.taimen.conf b/nfc/libnfc-nxp.taimen.conf
index 08abdc0..98f3a1e 100644
--- a/nfc/libnfc-nxp.taimen.conf
+++ b/nfc/libnfc-nxp.taimen.conf
@@ -83,7 +83,8 @@ NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 31, 01, 01, 31, 00, 00, 00, 01,
 ###############################################################################
 #config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
 #monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms
-NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, B2, 00, B2, 1E, 1F, 00, D0, 0C}
+#NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, B2, 00, B2, 1E, 11, 00, D0, 0C}
+NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, B2, 00, B2, 1E, 15, 00, D0, 0C}
 
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
@@ -91,24 +92,121 @@ NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, B2, 00, B2, 1E, 1F,
 #NXP_RF_CONF_BLK_1={
 #}
 
+NXP_RF_CONF_BLK_1={ 20, 02, A8, 14,
+    A0, 0D, 06, 06, 37, 08, 76, 00, 00,
+    A0, 38, 04, 14, 0B, 0B, 00,
+    A0, 0D, 03, 24, 03, 7E,
+    A0, 0D, 06, 06, 42, 00, 00, F4, F4,
+    A0, 0D, 04, 32, 42, FC, 40,
+    A0, 0D, 04, 46, 42, 68, 40,
+    A0, 0D, 04, 56, 42, 78, 40,
+    A0, 0D, 04, 5C, 42, 80, 40,
+    A0, 0D, 06, 34, 44, 66, 0A, 00, 00,
+    A0, 0D, 06, 48, 44, 65, 0A, 00, 00,
+    A0, 0D, 06, 58, 44, 55, 08, 00, 00,
+    A0, 0D, 06, 5E, 44, 55, 08, 00, 00,
+    A0, 0D, 06, 34, 2D, DC, 20, 04, 00,
+    A0, 0D, 06, 48, 2D, 15, 34, 1F, 01,
+    A0, 0D, 06, 58, 2D, 0D, 48, 0C, 01,
+    A0, 0D, 06, 5E, 2D, 0D, 5A, 0C, 01,
+    A0, 0D, 06, 32, 4A, 53, 07, 00, 1B,
+    A0, 0D, 06, 46, 4A, 33, 07, 00, 07,
+    A0, 0D, 06, 56, 4A, 43, 07, 00, 07,
+    A0, 0D, 06, 5C, 4A, 11, 07, 01, 07
+}
+
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
 #NXP_RF_CONF_BLK_2={
 #}
 
+NXP_RF_CONF_BLK_2={ 20, 02, 26, 02,
+    A0, 3A, 08, 2D, 00, 2D, 00, 2D, 00, 2D, 00,
+    A0, 29, 17, 1C, 02, 00, 1F, 00, 02, 00, 1F, 00, 02, 00, 40, F3, F3, 00, 43, F3, F3, 38, 70, 00, 00, 01
+}
+
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
 #NXP_RF_CONF_BLK_3={
 #}
 
+NXP_RF_CONF_BLK_3={20, 02, D6, 01,
+    A0, 34, D2, 23, 04, 18,
+    07,
+    40,
+    00, 20, 40, 00,
+    2D, 20, 40, 00,
+    32, 20, 40, 00,
+    3B, 20, 40, 00,
+    5C, 20, 40, 00,
+    9A, 00, 60, 00,
+    AE, 00, 70, 00,
+    00, 00, 08, 02,
+    00, 00, 08, 02,
+    00, 00, 08, 02,
+    00, 00, 08, 02,
+    00, 00, 08, 02,
+    00, 00, 08, 02,
+    00, 00, 48, 01,
+    00, 00, 08, 03,
+    00, 00, 08, 01,
+    00, 00, C8, 02,
+    00, 00, C8, 00,
+    00, 00, 88, 02,
+    00, 00, 48, 02,
+    00, 00, B8, 00,
+    00, 00, 68, 00,
+    00, 00, 18, 00,
+    00, 00, 08, 02,
+    00, 00, 00, 00,
+    00, 00, 00, 00,
+    07,
+    00, 20, 40, 00,
+    2D, 20, 40, 00,
+    32, 20, 40, 00,
+    3B, 20, 40, 00,
+    5C, 20, 40, 00,
+    9A, 00, 60, 00,
+    AE, 00, 70, 00,
+    00, 00, 08, 02,
+    00, 00, 08, 02,
+    00, 00, 08, 02,
+    00, 00, 08, 02,
+    00, 00, 08, 02,
+    00, 00, 08, 02,
+    00, 00, 48, 01,
+    00, 00, 08, 03,
+    00, 00, 08, 01,
+    00, 00, C8, 02,
+    00, 00, C8, 00,
+    00, 00, 88, 02,
+    00, 00, 48, 02,
+    00, 00, B8, 00,
+    00, 00, 68, 00,
+    00, 00, 18, 00,
+    00, 00, 08, 02,
+    00, 00, 00, 00
+}
+
+
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
 #NXP_RF_CONF_BLK_4={
 #}
 
+NXP_RF_CONF_BLK_4={ 20, 02, 5B, 01,
+    A0, 0B, 57, 05, 85, 90, 78, 0F, 4E, 00, 3D, 95,
+    00, 00, 3D, 9F, 00, 00, 50, 9F, 00, 00, 59, 9F, 00,
+    00, 5A, 9F, 00, 00, 64, 9F, 00, 00, 65, 1F, 00, 00,
+    6E, 1F, 00, 00, 72, 1F, 00, 00, 79, 1F, 00, 00, 7B,
+    1F, 00, 00, 84, 1F, 00, 00, 86, 1F, 00, 00, 8F, 1F,
+    00, 00, 91, 1F, 00, 00, 9A, 1F, 00, 00, A1, 1F, 00,
+    00, A7, 1F, 00, 00, B0, 1F, 00, 00, B9, 1F, 00, 00
+}
+
 ###############################################################################
 # NXP RF configuration ALM/PLM settings
 # This section needs to be updated with the correct values based on the platform
@@ -141,17 +239,46 @@ NXP_SET_CONFIG_ALWAYS=0x00
 # UICC2 bit rate A0D1
 # SWP1A interface A0D4
 # DWP intf behavior config, SVDD Load activated by default if set to 0x31 - A037
-NXP_CORE_CONF_EXTN={20, 02, 25, 09,
+
+#NXP_CORE_CONF_EXTN={20, 02, 79, 17,
+#    A0, 02, 01, 01,
+#    A0, 0E, 0B, 11, 01, C2, 82, 00, 0A, 1E, 15, 00, D0, 0C,
+#    A0, 11, 04, CD, 67, 22, FF,
+#    A0, 12, 01, 02,
+#    A0, 37, 01, 35,
+#    A0, 40, 01, 00,
+#    A0, 41, 01, 03,
+#    A0, 42, 01, 19,
+#    A0, 43, 01, 04,
+#    A0, 47, 02, 00, 27,
+#    A0, 62, 01, 01,
+#    A0, 69, 09, 02, CF, 80, 00, 00, 07, 40, 00, 00,
+#    A0, 80, 02, 20, 03,
+#    A0, 85, 04, 51, 08, A8, 7C,
+#    A0, 96, 01, 20,
+#    A0, CD, 01, 7F,
+#    A0, D4, 01, 00,
+#    A0, D8, 01, 02,
+#    A0, EC, 01, 01,
+#    A0, ED, 01, 01,
+#    A0, F2, 01, 01,
+#    A0, F3, 02, 10, 27,
+#    A0, B1, 02, E8, 03
+#}
+
+NXP_CORE_CONF_EXTN={20, 02, 2D, 0B,
     A0, EC, 01, 01,
     A0, ED, 01, 00,
     A0, 5E, 01, 01,
     A0, 12, 01, 02,
-    A0, 40, 01, 01,
+    A0, 40, 01, 05,
+    A0, 41, 01, 05,
+    A0, 43, 01, 04,
     A0, DD, 01, 2D,
     A0, D1, 01, 02,
     A0, D4, 01, 01,
     A0, 37, 01, 35
-   }
+}
 #       A0, F2, 01, 01,
 #       A0, 40, 01, 01,
 #       A0, 41, 01, 02,