Evolution-x-devices/device_xiaomi_sdm710-common
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sdm710-common: Adjust libnfc-nxp.conf for Grus & Pyxis

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With current NFC configuration the payments using GooglePay is
not functional.
This follow-up commit adjust libnfc-nxp.conf file for Grus and
Pyxis.

Tested: On Pyxis by successful payment using GooglePay
Change-Id: Iec64c5ca7740004f899b3be4a79cd3f6eb764750
This commit is contained in:
Ivan Vecera
2022-08-17 18:28:35 +02:00
committed by Sebastiano Barezzi
parent cef3b175d4
commit 76cb1d6e42
1 changed files with 12 additions and 11 deletions
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23
nfc/libnfc-nxp.conf
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@@ -66,7 +66,7 @@ NXP_FW_NAME="libpn553_fw.so"
# System clock source selection configuration
# define CLK_SRC_XTAL 1
# define CLK_SRC_PLL 2
NXP_SYS_CLK_SRC_SEL=0x01
NXP_SYS_CLK_SRC_SEL=0x02
###############################################################################
# System clock frequency selection configuration
@@ -76,7 +76,7 @@ NXP_SYS_CLK_SRC_SEL=0x01
# define CLK_FREQ_26MHZ 4
# define CLK_FREQ_38_4MHZ 5
# define CLK_FREQ_52MHZ 6
NXP_SYS_CLK_FREQ_SEL=0x01
NXP_SYS_CLK_FREQ_SEL=0x02
###############################################################################
# The timeout value to be used for clock request acknowledgment
@@ -114,7 +114,7 @@ NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 31, 01, 01, 31, 00, 00, 00, 01,
###############################################################################
# config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
# monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms
NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, C2, 00, BA, 1E, 15, 00, D0, 0C}
NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, B2, 00, BA, 1E, 15, 00, D0, 0C}
###############################################################################
# config3: use DCDC in CE, use Tx_Pwr_Req, SLALM, monitoring 5V from DCDC,
@@ -127,7 +127,7 @@ NXP_EXT_TVDD_CFG_3={20, 02, 0B, 02, A0, 66, 01, 01, A0, 0E, 03, 52, 40, 0A}
NXP_RF_CONF_BLK_1={
20, 02, E7, 1B,
A0, 0D, 06, 06, 37, 08, 76, 00, 00,
A0, 0D, 03, 24, 03, 7D,
A0, 0D, 03, 24, 03, 7C,
A0, 0D, 06, 02, 35, 00, 3E, 00, 00,
A0, 0D, 06, 04, 35, F4, 05, 70, 02,
A0, 0D, 06, C2, 35, 00, 3E, 00, 03,
@@ -137,7 +137,7 @@ NXP_RF_CONF_BLK_1={
A0, 0D, 04, 56, 42, 78, 40,
A0, 0D, 04, 5C, 42, 80, 40,
A0, 0D, 04, CA, 42, 68, 40,
A0, 0D, 06, 06, 42, 00, 02, F6, F6,
A0, 0D, 06, 06, 42, 00, 02, F4, F4,
A0, 0D, 06, 32, 4A, 53, 07, 00, 1B,
A0, 0D, 06, 46, 4A, 33, 07, 00, 07,
A0, 0D, 06, 56, 4A, 43, 07, 00, 07,
@@ -160,7 +160,7 @@ NXP_RF_CONF_BLK_1={
# This section needs to be updated with the correct values based on the platform
# Enable DLMA
NXP_RF_CONF_BLK_2={
20, 02, D6, 01, A0, 34, D2, 23, 04, 18, 47, 40, 00, 00, 40, 01, 32, 00, 40, 01, 47, 00, 40, 01, 6C, 00, 40, 01, B1, 00, 40, 01, 1E, 01, 08, 01, A0, 01, 48, 00, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 48, 01, 00, 00, 08, 03, 00, 00, 08, 01, 00, 00, C8, 02, 00, 00, C8, 00, 00, 00, 88, 02, 00, 00, 48, 02, 00, 00, B8, 00, 00, 00, 68, 00, 00, 00, 18, 00, 00, 00, 08, 02, 00, 00, 00, 00, 00, 00, 00, 00, 47, 00, 00, 40, 01, 32, 00, 40, 01, 47, 00, 40, 01, 6C, 00, 40, 01, B1, 00, 40, 01, 1E, 01, 08, 01, A0, 01, 48, 00, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 48, 01, 00, 00, 08, 03, 00, 00, 08, 01, 00, 00, C8, 02, 00, 00, C8, 00, 00, 00, 88, 02, 00, 00, 48, 02, 00, 00, B8, 00, 00, 00, 68, 00, 00, 00, 18, 00, 00, 00, 08, 02, 00, 00, 00, 00
20, 02, D6, 01, A0, 34, D2, 23, 04, 18, 47, 40, 00, 00, 40, 01, 32, 00, 40, 01, 47, 00, 40, 01, 73, 00, 40, 01, B9, 00, 40, 01, 15, 01, 08, 01, 75, 01, 48, 00, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 48, 01, 00, 00, 08, 03, 00, 00, 08, 01, 00, 00, C8, 02, 00, 00, C8, 00, 00, 00, 88, 02, 00, 00, 48, 02, 00, 00, B8, 00, 00, 00, 68, 00, 00, 00, 18, 00, 00, 00, 08, 02, 00, 00, 00, 00, 00, 00, 00, 00, 47, 00, 00, 40, 01, 32, 00, 40, 01, 47, 00, 40, 01, 73, 00, 40, 01, B9, 00, 40, 01, 15, 01, 08, 01, 75, 01, 48, 00, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 08, 02, 00, 00, 48, 01, 00, 00, 08, 03, 00, 00, 08, 01, 00, 00, C8, 02, 00, 00, C8, 00, 00, 00, 88, 02, 00, 00, 48, 02, 00, 00, B8, 00, 00, 00, 68, 00, 00, 00, 18, 00, 00, 00, 08, 02, 00, 00, 00, 00
}
###############################################################################
@@ -177,8 +177,8 @@ NXP_RF_CONF_BLK_3={
# CE detector/phase
NXP_RF_CONF_BLK_4={
20, 02, 21, 04,
A0, 38, 04, 06, 06, 06, 00,
A0, 3A, 08, C8, 00, C8, 00, C8, 00, C8, 00,
A0, 38, 04, 08, 08, 08, 00,
A0, 3A, 08, E1, 00, E1, 00, E1, 00, E1, 00,
A0, 0D, 06, 06, 16, 0E, 00, 1F, 00,
A0, B1, 02, A8, 02
}
@@ -220,7 +220,7 @@ NXP_SET_CONFIG_ALWAYS=0x01
# A096 - Notify all AIDs
# A037 - SE DWP system configuration
NXP_CORE_CONF_EXTN={
20, 02, 51, 13,
20, 02, 6B, 14,
A0, 09, 02, 90, 01,
A0, EC, 01, 01,
A0, ED, 01, 03,
@@ -239,7 +239,8 @@ NXP_CORE_CONF_EXTN={
A0, 9F, 02, 08, 08,
A0, 96, 01, 01,
A0, 37, 01, 35,
A0, 3F, 01, 01
A0, 3F, 01, 01,
A0, 29, 17, 1A, 07, 00, 1D, 00, 02, 00, 1D, 00, 02, 00, 40, F6, F6, 00, 43, F6, F6, 38, 70, 00, 00, 00
}
###############################################################################
@@ -437,7 +438,7 @@ NXP_SWP_SWITCH_TIMEOUT=0x0A
# P61 interface options for JCOP Download
# NFC 0x01
# SPI 0x02
NXP_P61_JCOP_DEFAULT_INTERFACE=0x01
NXP_P61_JCOP_DEFAULT_INTERFACE=0x00
###############################################################################
# P61 JCOP OS download options