Michel Dänzer 42baf21d91 drm/radeon/cik: Add tiling mode index for 1D tiled depth/stencil surfaces ...

CIK uses a different index for 1D DST surfaces compared to SI.  Expose
the new index so libdrm_radeon can use it properly for userspace
drivers.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2013-09-20 17:33:40 -04:00

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drm_fourcc.h

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drm_mode.h

drm: Add DRM_MODE_PAGE_FLIP_ASYNC flag definition

2013-08-30 09:25:13 +10:00

drm_sarea.h

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drm.h

drm: Advertise async page flip ability through GETCAP ioctl

2013-08-30 09:25:13 +10:00

exynos_drm.h

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i810_drm.h

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i915_drm.h

drm/i915: Use Write-Through cacheing for the display plane on Iris

2013-08-22 13:31:38 +02:00

Kbuild

drm/msm: add a3xx gpu support

2013-08-24 14:57:18 -04:00

mga_drm.h

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msm_drm.h

drm/msm: add a3xx gpu support

2013-08-24 14:57:18 -04:00

nouveau_drm.h

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omap_drm.h

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qxl_drm.h

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r128_drm.h

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radeon_drm.h

drm/radeon/cik: Add tiling mode index for 1D tiled depth/stencil surfaces

2013-09-20 17:33:40 -04:00

savage_drm.h

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sis_drm.h

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tegra_drm.h

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via_drm.h

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vmwgfx_drm.h

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