#include <dt-bindings/interrupt-controller/arm-gic.h>

&soc {
	apps_smmu: apps-smmu@15000000 {
		compatible = "qcom,qsmmu-v500";
		reg = <0x15000000 0x100000>,
			<0x15182000 0x28>;
		reg-names = "base", "tcu-base";
		#iommu-cells = <2>;
		qcom,skip-init;
		qcom,use-3-lvl-tables;
		#global-interrupts = <2>;
		#size-cells = <1>;
		#address-cells = <1>;
		ranges;

		interrupts =	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;

		anoc_1_tbu: anoc_1_tbu@15189000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x15189000 0x1000>,
				<0x15182200 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x0 0x400>;
			qcom,iova-width = <36>;
		};

		anoc_2_tbu: anoc_2_tbu@15191000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x15191000 0x1000>,
				<0x15182208 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x400 0x400>;
			qcom,iova-width = <36>;
		};

		mnoc_sf_0_tbu: mnoc_sf_0_tbu@15199000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x15199000 0x1000>,
				<0x15182210 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x800 0x400>;
			qcom,iova-width = <36>;
		};

		mnoc_sf_1_tbu: mnoc_sf_1_tbu@0x151a1000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x151A1000 0x1000>,
				<0x15182218 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0xC00 0x400>;
			qcom,iova-width = <36>;
		};

		mdp_00_tbu: mdp_00_tbu@0x151a9000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x151A9000 0x1000>,
				<0x15182220 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x1000 0x400>;
			qcom,iova-width = <32>;
		};

		mdp_01_tbu: mdp_01_tbu@0x151b1000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x151B1000 0x1000>,
				<0x15182228 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x1400 0x400>;
			qcom,iova-width = <32>;
		};

		mdp_10_tbu: mdp_10_tbu@0x151b9000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x151B9000 0x1000>,
				<0x15182230 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x1800 0x400>;
			qcom,iova-width = <32>;
		};

		mdp_11_tbu: mdp_11_tbu@151c1000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x151C1000 0x1000>,
				< 0x15182238 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x1C00 0x400>;
			qcom,iova-width = <32>;
		};

		nsp_00_tbu: nsp_00_tbu@151c9000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x151C9000 0x1000>,
				< 0x15182240 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x2000 0x400>;
			qcom,iova-width = <32>;
		};

		nsp_01_tbu: nsp_01_tbu@151d1000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x151D1000 0x1000>,
				< 0x15182248 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x2400 0x400>;
			qcom,iova-width = <32>;
		};

		nsp_10_tbu: nsp_10_tbu@151d9000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x151D9000 0x1000>,
				< 0x15182250 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x2800 0x400>;
			qcom,iova-width = <32>;
		};

		nsp_11_tbu: nsp_11_tbu@151e1000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x151E1000 0x1000>,
				< 0x15182258 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x2C00 0x400>;
			qcom,iova-width = <32>;
		};

		lpass_tbu: lpass_tbu@151e9000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x151E9000 0x1000>,
				< 0x15182260 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x3000 0x400>;
			qcom,iova-width = <32>;
		};

		cam_tbu: cam_tbu@151f1000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x151F1000 0x1000>,
				< 0x15182268 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x3400 0x400>;
			qcom,iova-width = <32>;
		};

		gpdsp_sail_ss_tbu: gpdsp_sail_ss_tbu@151f9000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x151F9000 0x1000>,
				< 0x15182270 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x3800 0x400>;
			qcom,iova-width = <32>;
		};
	};

	pcie_smmu: pcie-smmu@0x15200000 {
		compatible = "qcom,qsmmu-v500";
		reg = <0x15200000 0x80000>,
			<0x152F2000 0x28>;
		reg-names = "base", "tcu-base";
		#iommu-cells = <2>;
		qcom,skip-init;
		qcom,use-3-lvl-tables;
		qcom,split-tables;
		#global-interrupts = <2>;
		#size-cells = <1>;
		#address-cells = <1>;
		#tcu-testbus-version = <1>;
		ranges;

		interrupts =	<GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;

		pcie_0_tbu: pcie_0_tbu@152f9000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x152F9000 0x1000>,
				<0x152F2200 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x0 0x400>;
			qcom,iova-width = <36>;
		};

		pcie_1_tbu: pcie_1_tbu@152fb000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x152FB000 0x1000>,
				<0x152F3200 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x400 0x400>;
			qcom,iova-width = <36>;
		};
	};

	kgsl_smmu: kgsl-smmu@3da0000 {
		compatible = "qcom,qsmmu-v500";
		reg = <0x3da0000 0x20000>,
			<0x3dca000 0x28>;
		reg-names = "base", "tcu-base";
		#iommu-cells = <2>;
		qcom,skip-init;
		qcom,use-3-lvl-tables;
		qcom,split-tables;
		#global-interrupts = <2>;
		#size-cells = <1>;
		#address-cells = <1>;
		#tcu-testbus-version = <1>;
		ranges;
		dma-coherent;
		qcom,regulator-names = "vdd";
		vdd-supply = <&gpu_cc_cx_gdsc>;

		clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
			<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
			<&gpucc GPU_CC_AHB_CLK>,
			<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
			<&gpucc GPU_CC_CX_GMU_CLK>,
			<&gpucc GPU_CC_HUB_CX_INT_CLK>,
			<&gpucc GPU_CC_HUB_AON_CLK>;

		clock-names = "gcc_gpu_memnoc_gfx",
				"gcc_gpu_snoc_dvm_gfx",
				"gpu_cc_ahb",
				"gpu_cc_hlos1_vote_gpu_smmu_clk",
				"gpu_cc_cx_gmu_clk",
				"gpu_cc_hub_cx_int_clk",
				"gpu_cc_hub_aon_clk";


		interrupts =	<GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;

		gfx_0_tbu: gfx_0_tbu@3dd1000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x3DD1000 0x1000>,
				<0x3DCA200 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x0 0x400>;
			qcom,iova-width = <49>;
		};

		gfx_1_tbu: gfx_1_tbu@3dd3000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x3DD3000 0x1000>,
				<0x3DCA208 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x400 0x400>;
			qcom,iova-width = <49>;
		};

		gfx_2_tbu: gfx_2_tbu@3dd9000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x3DD9000 0x1000>,
				<0x3DCB200 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x800 0x400>;
			qcom,iova-width = <49>;
		};

		gfx_3_tbu: gfx_3_tbu@3ddb000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x3DDB000 0x1000>,
				<0x3DCB208 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0xC00 0x400>;
			qcom,iova-width = <49>;
		};
	};

	iommu_test_device {

		compatible = "qcom,iommu-debug-test";

		usecase0_apps {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&apps_smmu 0x580 0>;
		};

		usecase1_apps_fastmap {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&apps_smmu 0x580 0>;
			qcom,iommu-dma = "fastmap";
		};

		usecase2_apps_atomic {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&apps_smmu 0x580 0>;
			qcom,iommu-dma = "atomic";
		};

		usecase3_apps_dma {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&apps_smmu 0x581 0>;
			dma-coherent;
		};

		usecase0_pcie {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&pcie_smmu 0x440 0x0>;
		};

		usecase1_pcie_fastmap {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&pcie_smmu 0x440 0x0>;
			qcom,iommu-dma = "fastmap";
		};

		usecase2_pcie_atomic {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&pcie_smmu 0x440 0x0>;
			qcom,iommu-dma = "atomic";
		};

		usecase3_pcie_dma {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&pcie_smmu 0x440 0x0>;
			dma-coherent;
		};

		usecase0_kgsl {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&kgsl_smmu 0x7 0xC00>;
		};

		usecase1_kgsl_fastmap {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&kgsl_smmu 0x7 0xC00>;
			qcom,iommu-dma = "fastmap";
		};

		usecase2_kgsl_atomic {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&kgsl_smmu 0x7 0xC00>;
			qcom,iommu-dma = "atomic";
		};

		usecase3_kgsl_dma {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&kgsl_smmu 0x407 0xC00>;
			dma-coherent;
		};
	};
};
