Qualcomm Technologies, Inc. High Speed I2S Interface

* HS-I2S generic node

Required properties:

 - compatible : Should include "qcom,hsi2s"
		Should include target specific compatible field
		"qcom,sa6155-hsi2s" for SA6155
		"qcom,sa8155-hsi2s" for SA8155
		"qcom,sa8195-hsi2s" for SA8195
 - number-of-interfaces : Denotes the number of HS-I2S interfaces
 - reg : Specifies the base physical address and the size of the HS-I2S
	 register space
 - reg-names : "lpa_if" - string to identify the HS-I2S base register
 - interrupts : Interrupt number used by this interface
 - clocks : Core clocks used by this interface
 - clock-names : Clock names for each core clock
 - iommus: The phandle and stream IDs for the SMMU used by this root
 - qcom,iommu-dma-addr-pool: Specifies the start address and size of iova space

Optional properties:

 - number-of-rate-detectors : Number of rate detectors to enable
			      0 - Doesn't enable rate detectors
			      1 - Enables primary rate detector
			      2 - Enables both primary and secondary
				  rate detectors
 - rate-detector-interfaces : Specifies the minor number of the interfaces
			      to have rate detection enabled

* HS-I2S interface nodes

Required properties:

 - compatible : Should be "qcom,hsi2s-interface"
 - minor-number : Minor number of the character device interface
		  Should be 0 for HS0 interface
		  Should be 1 for HS1 interface
		  Should be 2 for HS2 interface
 - clocks : Interface clock used by this interface
 - clock-names : Clock name for the interface clock
 - pinctrl-names : Pinctrl state names for each pin group configuration
 - pinctrl-x : Defines pinctrl state for each pin group
 - bit-clock-hz : Default bit clock frequency in hertz
 - data-buffer-ms : Default periodic interrupt interval in milliseconds

Optional properties:

 - bit-depth : Bit depth of the I2S data
	       Default - 32
 - spkr-channel-count : Number of speaker channels
			Default - 2
 - mic-channel-count : Number of mic channels
		       Default - 2
 - pcm-rate : Number of bit clocks per PCM frame
	      0 - ENUM_8
	      1 - ENUM_16
	      2 - ENUM_32 (Default)
	      3 - ENUM_64
	      4 - ENUM_128
	      5 - ENUM_256
 - pcm-sync-src : Specifies whether the PCM block uses internal or
		  external sync
		  0 - External (Default)
		  1 - Internal
 - aux-mode : Specifies the type of sync expected/generated by the
	      PCM block.
	      0 - PCM (Short sync) (Default)
	      1 - Aux PCM (Long sync)
 - rpcm-width : Number of bits per receive slot
		0 - 8 bits
		1 - 16 bits (Default)
 - tpcm-width : Number of bits per transmit slot
		0 - 8 bits
		1 - 16 bits (Default)
 - enable-tdm : Specifies whether TDM is enabled by default
		0 - Disable TDM
		1 - Enable TDM (Default)
 - tdm-rate : Number of bit clocks per TDM frame
	      Maximum permissible value is 512
	      Default - 32
 - tdm-rpcm-width : Number of bits per receive slot in TDM
	      Maximum permissible value is 32
	      Default - 16
 - tdm-tpcm-width : Number of bits per transmit slot in TDM
	      Maximum permissible value is 32
	      Default - 16
 - tdm-sync-delay : Specifies the data delay relative to sync pulse
		    0 - First data appears two cycles after frame pulse
		    1 - First data appears one cycle after frame pulse
		    2 - First data and frame pulse occur on the same cycle
		    Default - 2
 - tdm-inv-sync : Specifies whether the frame sync has to be inverted
		  in long sync(Aux PCM) mode
		  0 - Do not invert frame sync (Default)
		  1 - Invert frame sync
 - pcm-lane-config : Specifies the PCM data lane configuration
		     0 - Single lane
			 D0 - MIC
			 D1 - SPEAKER
		     1 - Multi lane Rx (Default)
			 D0 - MIC
			 D1 - MIC
		     2 - Multi lane Tx
			 D0 - SPEAKER
			 D1 - SPEAKER

Example:

hsi2s: qcom,hsi2s {
	compatible = "qcom,sa6155-hsi2s", "qcom,hsi2s";
	number-of-interfaces = <2>;
	reg = <0x1B40000 0x28000>;
	reg-names = "lpa_if";
	interrupts = <GIC_SPI 267 0>;
	clocks = <&clock_gcc GCC_SDR_CORE_CLK>,
		 <&clock_gcc GCC_SDR_WR0_MEM_CLK>,
		 <&clock_gcc GCC_SDR_WR1_MEM_CLK>,
		 <&clock_gcc GCC_SDR_WR2_MEM_CLK>,
		 <&clock_gcc GCC_SDR_CSR_HCLK>;
	clock-names = "core_clk", "wr0_mem_clk",
		      "wr1_mem_clk", "wr2_mem_clk",
		      "csr_hclk";
	number-of-rate-detectors = <2>;
	rate-detector-interfaces = <0 1>;
	iommus = <&apps_smmu 0x035C 0x1>;
	qcom,iommu-dma-addr-pool = <0x0 0xFFFFFFFF>;

	sdr0: qcom,hs0_i2s {
		compatible = "qcom,hsi2s-interface";
		minor-number = <0>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&hs0_i2s_sck_active &hs0_i2s_data0_active
			     &hs0_i2s_data1_active>;
		pinctrl-1 = <&hs0_i2s_sck_sleep &hs0_i2s_data0_sleep
			     &hs0_i2s_data1_sleep>;
		clocks = <&clock_gcc GCC_SDR_PRI_MI2S_CLK>;
		clock-names = "pri_mi2s_clk";
		bit-clock-hz = <12288000>;
		data-buffer-ms = <10>;
		bit-depth = <32>;
		spkr-channel-count = <2>;
		mic-channel-count = <2>;
		pcm-rate = <2>;
		pcm-sync-src = <0>;
		aux-mode = <0>;
		rpcm-width = <1>;
		tpcm-width = <1>;
		enable-tdm = <1>;
		tdm-rate = <32>;
		tdm-rpcm-width = <16>;
		tdm-tpcm-width = <16>;
		tdm-sync-delay = <2>;
		tdm-inv-sync = <0>;
		pcm-lane-config = <1>;
	};

	sdr1: qcom,hs1_i2s {
		compatible = "qcom,hsi2s-interface";
		minor-number = <1>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&hs1_i2s_sck_active &hs1_i2s_data0_active
			     &hs1_i2s_data1_active>;
		pinctrl-1 = <&hs1_i2s_sck_sleep &hs1_i2s_data0_sleep
			     &hs1_i2s_data1_sleep>;
		clocks = <&clock_gcc GCC_SDR_SEC_MI2S_CLK>;
		clock-names = "sec_mi2s_clk";
		bit-clock-hz = <12288000>;
		data-buffer-ms = <10>;
		bit-depth = <32>;
		spkr-channel-count = <2>;
		mic-channel-count = <2>;
		pcm-rate = <2>;
		pcm-sync-src = <0>;
		aux-mode = <0>;
		rpcm-width = <1>;
		tpcm-width = <1>;
		enable-tdm = <1>;
		tdm-rate = <32>;
		tdm-rpcm-width = <16>;
		tdm-tpcm-width = <16>;
		tdm-sync-delay = <2>;
		tdm-inv-sync = <0>;
		pcm-lane-config = <1>;
	};
};
