# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Actions Semi Owl SoCs SIRQ interrupt controller

maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

description: |
  This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700
  and S900) and provides support for handling up to 3 external interrupt lines.

properties:
  compatible:
    enum:
      - actions,s500-sirq
      - actions,s700-sirq
      - actions,s900-sirq

  reg:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 2
    description:
      The first cell is the input IRQ number, between 0 and 2, while the second
      cell is the trigger type as defined in interrupt.txt in this directory.

  'interrupts':
    description: |
      Contains the GIC SPI IRQs mapped to the external interrupt lines.
      They shall be specified sequentially from output 0 to 2.
    minItems: 3
    maxItems: 3

required:
  - compatible
  - reg
  - interrupt-controller
  - '#interrupt-cells'
  - 'interrupts'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    sirq: interrupt-controller@b01b0200 {
      compatible = "actions,s500-sirq";
      reg = <0xb01b0200 0x4>;
      interrupt-controller;
      #interrupt-cells = <2>;
      interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */
                   <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */
                   <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */
    };

...
