#include <dt-bindings/interconnect/qcom,waipio.h>

&soc {
	/* QUPv3 SE Instances
	 * Qup0 0: SE 0
	 * Qup0 1: SE 1
	 * Qup0 2: SE 2
	 * Qup0 3: SE 3
	 * Qup0 4: SE 4
	 * Qup0 5: SE 5
	 * Qup0 6: SE 6
	 * Qup0 7: SE 7
	 * Qup1 0: SE 8
	 * Qup1 1: SE 9
	 * Qup1 2: SE 10
	 * Qup1 3: SE 11
	 * Qup1 4: SE 12
	 * Qup1 5: SE 13
	 * Qup1 6: SE 14
	 * Qup2 0: SE 15
	 * Qup2 1: SE 16
	 * Qup2 2: SE 17
	 * Qup2 3: SE 18
	 * Qup2 4: SE 19
	 * Qup2 5: SE 20
	 * Qup2 6: SE 21
	 */

	/* QUPv3_0  wrapper  instance */
	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
		compatible = "qcom,geni-se-qup";
		reg = <0x9c0000 0x2000>;
		clock-names = "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		status = "ok";

		/* Debug UART Instance */
		qupv3_se7_2uart: qcom,qup_uart@99c000 {
			compatible = "qcom,geni-debug-uart";
			reg = <0x99c000 0x4000>;
			reg-names = "se_phys";
			interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "se", "m-ahb", "s-ahb";
			clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>,
				<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
				<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&qupv3_se7_2uart_active>;
			pinctrl-1 = <&qupv3_se7_2uart_sleep>;
			status = "disabled";
		};
	};

	/* GPI Instance */
	gpi_dma0: qcom,gpi-dma@900000 {
		compatible = "qcom,gpi-dma";
		#dma-cells = <5>;
		reg = <0x900000 0x60000>;
		reg-names = "gpi-top";
		iommus = <&apps_smmu 0x5b6 0x0>;
		qcom,max-num-gpii = <12>;
		interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
		qcom,static-gpii-mask = <0x1>;
		qcom,gpii-mask = <0x7e>;
		qcom,ev-factor = <2>;
		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
		qcom,gpi-ee-offset = <0x10000>;
		qcom,le-vm;
		status = "disabled";
	};

	qupv3_se0_i2c: i2c@980000 {
		compatible = "qcom,i2c-geni";
		reg = <0x980000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se0_i2c_active>;
		pinctrl-1 = <&qupv3_se0_i2c_sleep>;
		dmas = <&gpi_dma0 0 0 3 64 0>,
			<&gpi_dma0 1 0 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se0_spi: spi@980000 {
		compatible = "qcom,spi-geni";
		reg = <0x980000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se0_spi_active>;
		pinctrl-1 = <&qupv3_se0_spi_sleep>;
		dmas = <&gpi_dma0 0 0 1 64 0>,
			<&gpi_dma0 1 0 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se1_i2c: i2c@984000 {
		compatible = "qcom,i2c-geni";
		reg = <0x984000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se1_i2c_active>;
		pinctrl-1 = <&qupv3_se1_i2c_sleep>;
		dmas = <&gpi_dma0 0 1 3 64 0>,
			<&gpi_dma0 1 1 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se1_spi: spi@984000 {
		compatible = "qcom,spi-geni";
		reg = <0x984000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se1_spi_active>;
		pinctrl-1 = <&qupv3_se1_spi_sleep>;
		dmas = <&gpi_dma0 0 1 1 64 0>,
			<&gpi_dma0 1 1 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se2_i2c: i2c@988000 {
		compatible = "qcom,i2c-geni";
		reg = <0x988000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se2_i2c_active>;
		pinctrl-1 = <&qupv3_se2_i2c_sleep>;
		dmas = <&gpi_dma0 0 2 3 64 0>,
			<&gpi_dma0 1 2 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se2_spi: spi@988000 {
		compatible = "qcom,spi-geni";
		reg = <0x988000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se2_spi_active>;
		pinctrl-1 = <&qupv3_se2_spi_sleep>;
		dmas = <&gpi_dma0 0 2 1 64 0>,
			<&gpi_dma0 1 2 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se3_i2c: i2c@98c000 {
		compatible = "qcom,i2c-geni";
		reg = <0x98c000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se3_i2c_active>;
		pinctrl-1 = <&qupv3_se3_i2c_sleep>;
		dmas = <&gpi_dma0 0 3 3 64 0>,
			<&gpi_dma0 1 3 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se3_spi: spi@98c000 {
		compatible = "qcom,spi-geni";
		reg = <0x98c000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se3_spi_active>;
		pinctrl-1 = <&qupv3_se3_spi_sleep>;
		dmas = <&gpi_dma0 0 3 1 64 0>,
			<&gpi_dma0 1 3 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	/* TUI over I2C */
	qupv3_se4_i2c: i2c@990000 {
		compatible = "qcom,i2c-geni";
		reg = <0x990000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se4_i2c_active>;
		pinctrl-1 = <&qupv3_se4_i2c_sleep>;
		dmas = <&gpi_dma0 0 4 3 64 2>,
			<&gpi_dma0 1 4 3 64 2>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se4_spi: spi@990000 {
		compatible = "qcom,spi-geni";
		reg = <0x990000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se4_spi_active>;
		pinctrl-1 = <&qupv3_se4_spi_sleep>;
		dmas = <&gpi_dma0 0 4 1 64 2>,
			<&gpi_dma0 1 4 1 64 2>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se5_i2c: i2c@994000 {
		compatible = "qcom,i2c-geni";
		reg = <0x994000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se5_i2c_active>;
		pinctrl-1 = <&qupv3_se5_i2c_sleep>;
		dmas = <&gpi_dma0 0 5 3 64 0>,
			<&gpi_dma0 1 5 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_0>;
		qcom,shared;
		status = "disabled";
	};

	qupv3_se5_spi: spi@994000 {
		compatible = "qcom,spi-geni";
		reg = <0x994000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se5_spi_active>;
		pinctrl-1 = <&qupv3_se5_spi_sleep>;
		dmas = <&gpi_dma0 0 5 1 64 0>,
			<&gpi_dma0 1 5 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se6_i2c: i2c@998000 {
		compatible = "qcom,i2c-geni";
		reg = <0x998000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se6_i2c_active>;
		pinctrl-1 = <&qupv3_se6_i2c_sleep>;
		dmas = <&gpi_dma0 0 6 3 64 0>,
			<&gpi_dma0 1 6 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	qupv3_se6_spi: spi@998000 {
		compatible = "qcom,spi-geni";
		reg = <0x998000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se6_spi_active>;
		pinctrl-1 = <&qupv3_se6_spi_sleep>;
		dmas = <&gpi_dma0 0 6 1 64 0>,
			<&gpi_dma0 1 6 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	/* QUPv3_1  wrapper  instance */
	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0xac0000 0x2000>;
		qcom,msm-bus,num-paths = <3>;
		interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
		interconnects =
		<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
		<&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>,
		<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
		iommus = <&apps_smmu 0x43 0x0>;
		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
		qcom,iommu-geometry = <0x40000000 0x10000000>;
		qcom,iommu-dma = "fastmap";
		dma-coherent;
		status = "disabled";
	};

	/* GPI Instance */
	gpi_dma1: qcom,gpi-dma@a00000 {
		compatible = "qcom,gpi-dma";
		#dma-cells = <5>;
		reg = <0xa00000 0x60000>;
		reg-names = "gpi-top";
		iommus = <&apps_smmu 0x56 0x0>;
		qcom,max-num-gpii = <12>;
		interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
		qcom,gpii-mask = <0x3f>;
		qcom,ev-factor = <2>;
		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
		qcom,gpi-ee-offset = <0x10000>;
		status = "disabled";
	};

	qupv3_se8_i2c: i2c@a80000 {
		compatible = "qcom,i2c-geni";
		reg = <0xa80000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se8_i2c_active>;
		pinctrl-1 = <&qupv3_se8_i2c_sleep>;
		dmas = <&gpi_dma1 0 0 3 64 0>,
			<&gpi_dma1 1 0 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se8_spi: spi@a80000 {
		compatible = "qcom,spi-geni";
		reg = <0xa80000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se8_spi_active>;
		pinctrl-1 = <&qupv3_se8_spi_sleep>;
		dmas = <&gpi_dma1 0 0 1 64 0>,
			<&gpi_dma1 1 0 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se9_i2c: i2c@a84000 {
		compatible = "qcom,i2c-geni";
		reg = <0xa84000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se9_i2c_active>;
		pinctrl-1 = <&qupv3_se9_i2c_sleep>;
		dmas = <&gpi_dma1 0 1 3 64 0>,
			<&gpi_dma1 1 1 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se9_spi: spi@a84000 {
		compatible = "qcom,spi-geni";
		reg = <0xa84000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se9_spi_active>;
		pinctrl-1 = <&qupv3_se9_spi_sleep>;
		dmas = <&gpi_dma1 0 1 1 64 0>,
			<&gpi_dma1 1 1 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se10_i2c: i2c@a88000 {
		compatible = "qcom,i2c-geni";
		reg = <0xa88000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se10_i2c_active>;
		pinctrl-1 = <&qupv3_se10_i2c_sleep>;
		dmas = <&gpi_dma1 0 2 3 64 0>,
			<&gpi_dma1 1 2 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se10_spi: spi@a88000 {
		compatible = "qcom,spi-geni";
		reg = <0xa88000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se10_spi_active>;
		pinctrl-1 = <&qupv3_se10_spi_sleep>;
		dmas = <&gpi_dma1 0 2 1 64 0>,
			<&gpi_dma1 1 2 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se11_i2c: i2c@a8c000 {
		compatible = "qcom,i2c-geni";
		reg = <0xa8c000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se11_i2c_active>;
		pinctrl-1 = <&qupv3_se11_i2c_sleep>;
		dmas = <&gpi_dma1 0 3 3 64 0>,
			<&gpi_dma1 1 3 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se11_spi: spi@a8c000 {
		compatible = "qcom,spi-geni";
		reg = <0xa8c000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se11_spi_active>;
		pinctrl-1 = <&qupv3_se11_spi_sleep>;
		dmas = <&gpi_dma1 0 3 1 64 0>,
			<&gpi_dma1 1 3 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se12_i2c: i2c@a90000 {
		compatible = "qcom,i2c-geni";
		reg = <0xa90000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se12_i2c_active>;
		pinctrl-1 = <&qupv3_se12_i2c_sleep>;
		dmas = <&gpi_dma1 0 4 3 64 0>,
			<&gpi_dma1 1 4 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se12_spi: spi@a90000 {
		compatible = "qcom,spi-geni";
		reg = <0xa90000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se12_spi_active>;
		pinctrl-1 = <&qupv3_se12_spi_sleep>;
		dmas = <&gpi_dma1 0 4 1 64 0>,
			<&gpi_dma1 1 4 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se13_i2c: i2c@a94000 {
		compatible = "qcom,i2c-geni";
		reg = <0xa94000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se13_i2c_active>;
		pinctrl-1 = <&qupv3_se13_i2c_sleep>;
		dmas = <&gpi_dma1 0 5 3 64 0>,
			<&gpi_dma1 1 5 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se13_spi: spi@a94000 {
		compatible = "qcom,spi-geni";
		reg = <0xa94000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se13_spi_active>;
		pinctrl-1 = <&qupv3_se13_spi_sleep>;
		dmas = <&gpi_dma1 0 5 1 64 0>,
			<&gpi_dma1 1 5 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se14_i2c: i2c@a98000 {
		compatible = "qcom,i2c-geni";
		reg = <0xa98000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S6_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se14_i2c_active>;
		pinctrl-1 = <&qupv3_se14_i2c_sleep>;
		dmas = <&gpi_dma1 0 6 3 64 0>,
			<&gpi_dma1 1 6 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	qupv3_se14_spi: spi@a98000 {
		compatible = "qcom,spi-geni";
		reg = <0xa98000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S6_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se14_spi_active>;
		pinctrl-1 = <&qupv3_se14_spi_sleep>;
		dmas = <&gpi_dma1 0 6 1 64 0>,
			<&gpi_dma1 1 6 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
	};

	/* QUPv3_2  wrapper  instance */
	qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0x8c0000 0x2000>;
		qcom,msm-bus,num-paths = <3>;
		interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
		interconnects =
		<&clk_virt  MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
		<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
		<&aggre2_noc  MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
		iommus = <&apps_smmu 0x483 0x0>;
		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
		qcom,iommu-geometry = <0x40000000 0x10000000>;
		qcom,iommu-dma = "fastmap";
		dma-coherent;
		status = "disabled";
	};

	/* GPI Instance */
	gpi_dma2: qcom,gpi-dma@800000 {
		compatible = "qcom,gpi-dma";
		#dma-cells = <5>;
		reg = <0x800000 0x60000>;
		reg-names = "gpi-top";
		iommus = <&apps_smmu 0x496 0x0>;
		qcom,max-num-gpii = <12>;
		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
		qcom,gpii-mask = <0x3f>;
		qcom,ev-factor = <2>;
		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
		qcom,gpi-ee-offset = <0x10000>;
		status = "disabled";
	};

	qupv3_se15_i2c: i2c@880000 {
		compatible = "qcom,i2c-geni";
		reg = <0x880000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S0_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se15_i2c_active>;
		pinctrl-1 = <&qupv3_se15_i2c_sleep>;
		dmas = <&gpi_dma2 0 0 3 64 0>,
			<&gpi_dma2 1 0 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se15_spi: spi@880000 {
		compatible = "qcom,spi-geni";
		reg = <0x880000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S0_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se15_spi_active>;
		pinctrl-1 = <&qupv3_se15_spi_sleep>;
		dmas = <&gpi_dma2 0 0 1 64 0>,
			<&gpi_dma2 1 0 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	i3c0: i3c-master@880000 {
		compatible = "qcom,geni-i3c";
		reg = <0x880000 0x4000>,
			<0x0ECB0000 0x10000>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S0_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep", "disable";
		pinctrl-0 = <&qupv3_se15_i3c_active>;
		pinctrl-1 = <&qupv3_se15_i3c_sleep>;
		pinctrl-2 = <&qupv3_se15_i3c_disable>;
		interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
				<&pdc 35 IRQ_TYPE_LEVEL_HIGH>,
				<&pdc 34 IRQ_TYPE_LEVEL_HIGH>;
		qcom,ibi-support-disabled;

		#address-cells = <3>;
		#size-cells = <0>;
		qcom,ibi-ctrl-id = <2>; //QUP2-SE0 – IBI2 - 0xECB0000
		qcom,wrapper-core = <&qupv3_2>;

		status = "disable";
	};

	qupv3_se16_i2c: i2c@884000 {
		compatible = "qcom,i2c-geni";
		reg = <0x884000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S1_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se16_i2c_active>;
		pinctrl-1 = <&qupv3_se16_i2c_sleep>;
		dmas = <&gpi_dma2 0 1 3 64 0>,
			<&gpi_dma2 1 1 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se16_spi: spi@884000 {
		compatible = "qcom,spi-geni";
		reg = <0x884000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S1_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se16_spi_active>;
		pinctrl-1 = <&qupv3_se16_spi_sleep>;
		dmas = <&gpi_dma2 0 1 1 64 0>,
			<&gpi_dma2 1 1 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se17_i2c: i2c@888000 {
		compatible = "qcom,i2c-geni";
		reg = <0x888000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S2_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se17_i2c_active>;
		pinctrl-1 = <&qupv3_se17_i2c_sleep>;
		dmas = <&gpi_dma2 0 2 3 64 0>,
			<&gpi_dma2 1 2 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se17_spi: spi@888000 {
		compatible = "qcom,spi-geni";
		reg = <0x888000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S2_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se17_spi_active>;
		pinctrl-1 = <&qupv3_se17_spi_sleep>;
		dmas = <&gpi_dma2 0 2 1 64 0>,
			<&gpi_dma2 1 2 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se18_i2c: i2c@88c000 {
		compatible = "qcom,i2c-geni";
		reg = <0x88c000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se18_i2c_active>;
		pinctrl-1 = <&qupv3_se18_i2c_sleep>;
		dmas = <&gpi_dma2 0 3 3 64 0>,
			<&gpi_dma2 1 3 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se18_spi: spi@88c000 {
		compatible = "qcom,spi-geni";
		reg = <0x88c000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se18_spi_active>;
		pinctrl-1 = <&qupv3_se18_spi_sleep>;
		dmas = <&gpi_dma2 0 3 1 64 0>,
			<&gpi_dma2 1 3 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se19_i2c: i2c@890000 {
		compatible = "qcom,i2c-geni";
		reg = <0x890000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se19_i2c_active>;
		pinctrl-1 = <&qupv3_se19_i2c_sleep>;
		dmas = <&gpi_dma2 0 4 3 64 0>,
			<&gpi_dma2 1 4 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se19_spi: spi@890000 {
		compatible = "qcom,spi-geni";
		reg = <0x890000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se19_spi_active>;
		pinctrl-1 = <&qupv3_se19_spi_sleep>;
		dmas = <&gpi_dma2 0 4 1 64 0>,
			<&gpi_dma2 1 4 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se20_i2c: i2c@894000 {
		compatible = "qcom,i2c-geni";
		reg = <0x894000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S5_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se20_i2c_active>;
		pinctrl-1 = <&qupv3_se20_i2c_sleep>;
		dmas = <&gpi_dma2 0 5 3 64 0>,
			<&gpi_dma2 1 5 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se20_spi: spi@894000 {
		compatible = "qcom,spi-geni";
		reg = <0x894000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S5_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se20_spi_active>;
		pinctrl-1 = <&qupv3_se20_spi_sleep>;
		dmas = <&gpi_dma2 0 5 1 64 0>,
			<&gpi_dma2 1 5 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se21_i2c: i2c@898000 {
		compatible = "qcom,i2c-geni";
		reg = <0x898000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S6_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se21_i2c_active>;
		pinctrl-1 = <&qupv3_se21_i2c_sleep>;
		dmas = <&gpi_dma2 0 6 3 64 0>,
			<&gpi_dma2 1 6 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	qupv3_se21_spi: spi@898000 {
		compatible = "qcom,spi-geni";
		reg = <0x898000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "se_phys";
		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S6_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se21_spi_active>;
		pinctrl-1 = <&qupv3_se21_spi_sleep>;
		dmas = <&gpi_dma2 0 6 1 64 0>,
			<&gpi_dma2 1 6 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};

	/* HS UART Instance */
	qupv3_se20_4uart: qcom,qup_uart@894000 {
		compatible = "qcom,msm-geni-serial-hs";
		reg = <0x894000 0x4000>;
		reg-names = "se_phys";
		interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>,
				<&tlmm 79 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S5_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "active", "sleep";
		pinctrl-0 = <&qupv3_se20_default_cts>,
			<&qupv3_se20_default_rtsrx>, <&qupv3_se20_default_tx>;
		pinctrl-1 = <&qupv3_se20_cts>, <&qupv3_se20_rts>,
			<&qupv3_se20_tx>, <&qupv3_se20_rx_active>;
		pinctrl-2 = <&qupv3_se20_cts>, <&qupv3_se20_rts>,
			<&qupv3_se20_tx>, <&qupv3_se20_rx_wake>;
		qcom,wakeup-byte = <0xFD>;
		qcom,wrapper-core = <&qupv3_2>;
		status = "disabled";
	};
};
