#include "bengal-gpu.dtsi"

&msm_gpu {
	qcom,chipid = <0x06010001>;

	qcom,bus-table-ddr =
		<MHZ_TO_KBPS(0, 4)>,    /* index=0  */
		<MHZ_TO_KBPS(200, 4)>,  /* index=1  */
		<MHZ_TO_KBPS(547, 4)>,  /* index=2  */
		<MHZ_TO_KBPS(768, 4)>,  /* index=3  */
		<MHZ_TO_KBPS(1017, 4)>, /* index=4  */
		<MHZ_TO_KBPS(1555, 4)>, /* index=5  */
		<MHZ_TO_KBPS(1804, 4)>, /* index=6  */
		<MHZ_TO_KBPS(2092, 4)>; /* index=7  */

	/delete-node/ qcom,gpu-pwrlevel-bins;
	/*
	 * Speed-bin zero is default speed bin.
	 * For rest of the speed bins, speed-bin value
	 * is calculated as FMAX/4.8 MHz round up to zero
	 * decimal places plus two margin to account for
	 * clock jitters.
	 */
	qcom,gpu-pwrlevel-bins {
		#address-cells = <1>;
		#size-cells = <0>;

		compatible = "qcom,gpu-pwrlevel-bins";

		qcom,gpu-pwrlevels-0 {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,speed-bin = <0>;

			qcom,initial-pwrlevel = <6>;
			qcom,ca-target-pwrlevel = <5>;

			/* TURBO_L1 */
			qcom,gpu-pwrlevel@0 {
				reg = <0>;
				qcom,gpu-freq = <1260000000>;
				qcom,bus-freq = <7>;
				qcom,bus-min = <7>;
				qcom,bus-max = <7>;
				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
			};

			/* TURBO_L1 */
			qcom,gpu-pwrlevel@1 {
				reg = <1>;
				qcom,gpu-freq = <1114800000>;
				qcom,bus-freq = <7>;
				qcom,bus-min = <7>;
				qcom,bus-max = <7>;
				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
			};

			/* TURBO */
			qcom,gpu-pwrlevel@2 {
				reg = <2>;
				qcom,gpu-freq = <1025000000>;
				qcom,bus-freq = <6>;
				qcom,bus-min = <5>;
				qcom,bus-max = <7>;
				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
			};

			/* NOM */
			qcom,gpu-pwrlevel@3 {
				reg = <3>;
				qcom,gpu-freq = <785000000>;
				qcom,bus-freq = <5>;
				qcom,bus-min = <4>;
				qcom,bus-max = <5>;
				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
			};

			/* SVS_L1 */
			qcom,gpu-pwrlevel@4 {
				reg = <4>;
				qcom,gpu-freq = <600000000>;
				qcom,bus-freq = <4>;
				qcom,bus-min = <3>;
				qcom,bus-max = <5>;
				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
			};

			/* SVS */
			qcom,gpu-pwrlevel@5 {
				reg = <5>;
				qcom,gpu-freq = <465000000>;
				qcom,bus-freq = <3>;
				qcom,bus-min = <2>;
				qcom,bus-max = <4>;
				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
			};

			/* LOW SVS */
			qcom,gpu-pwrlevel@6 {
				reg = <6>;
				qcom,gpu-freq = <320000000>;
				qcom,bus-freq = <2>;
				qcom,bus-min = <1>;
				qcom,bus-max = <2>;
				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
			};

			/* XO */
			qcom,gpu-pwrlevel@7 {
				reg = <7>;
				qcom,gpu-freq = <0>;
				qcom,bus-freq = <0>;
				qcom,bus-min = <0>;
				qcom,bus-max = <0>;
				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
			};
		};

		qcom,gpu-pwrlevels-1 {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,speed-bin = <235>;

			qcom,initial-pwrlevel = <5>;
			qcom,ca-target-pwrlevel = <4>;

			/* TURBO_L1 */
			qcom,gpu-pwrlevel@0 {
				reg = <0>;
				qcom,gpu-freq = <1114800000>;
				qcom,bus-freq = <7>;
				qcom,bus-min = <7>;
				qcom,bus-max = <7>;
				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
			};

			/* TURBO */
			qcom,gpu-pwrlevel@1 {
				reg = <1>;
				qcom,gpu-freq = <1025000000>;
				qcom,bus-freq = <6>;
				qcom,bus-min = <5>;
				qcom,bus-max = <7>;
				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
			};

			/* NOM */
			qcom,gpu-pwrlevel@2 {
				reg = <2>;
				qcom,gpu-freq = <785000000>;
				qcom,bus-freq = <5>;
				qcom,bus-min = <4>;
				qcom,bus-max = <5>;
				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
			};

			/* SVS_L1 */
			qcom,gpu-pwrlevel@3 {
				reg = <3>;
				qcom,gpu-freq = <600000000>;
				qcom,bus-freq = <4>;
				qcom,bus-min = <3>;
				qcom,bus-max = <5>;
				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
			};

			/* SVS */
			qcom,gpu-pwrlevel@4 {
				reg = <4>;
				qcom,gpu-freq = <465000000>;
				qcom,bus-freq = <3>;
				qcom,bus-min = <2>;
				qcom,bus-max = <4>;
				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
			};

			/* LOW SVS */
			qcom,gpu-pwrlevel@5 {
				reg = <5>;
				qcom,gpu-freq = <320000000>;
				qcom,bus-freq = <2>;
				qcom,bus-min = <1>;
				qcom,bus-max = <2>;
				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
			};

			/* XO */
			qcom,gpu-pwrlevel@6 {
				reg = <6>;
				qcom,gpu-freq = <0>;
				qcom,bus-freq = <0>;
				qcom,bus-min = <0>;
				qcom,bus-max = <0>;
				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
			};
		};

		qcom,gpu-pwrlevels-2 {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,speed-bin = <216>;

			qcom,initial-pwrlevel = <4>;
			qcom,ca-target-pwrlevel = <3>;

			/* TURBO */
			qcom,gpu-pwrlevel@0 {
				reg = <0>;
				qcom,gpu-freq = <1025000000>;
				qcom,bus-freq = <6>;
				qcom,bus-min = <5>;
				qcom,bus-max = <7>;
				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
			};

			/* NOM */
			qcom,gpu-pwrlevel@1 {
				reg = <1>;
				qcom,gpu-freq = <785000000>;
				qcom,bus-freq = <5>;
				qcom,bus-min = <4>;
				qcom,bus-max = <5>;
				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
			};

			/* SVS_L1 */
			qcom,gpu-pwrlevel@2 {
				reg = <2>;
				qcom,gpu-freq = <600000000>;
				qcom,bus-freq = <4>;
				qcom,bus-min = <3>;
				qcom,bus-max = <5>;
				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
			};

			/* SVS */
			qcom,gpu-pwrlevel@3 {
				reg = <3>;
				qcom,gpu-freq = <465000000>;
				qcom,bus-freq = <3>;
				qcom,bus-min = <2>;
				qcom,bus-max = <4>;
				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
			};

			/* LOW SVS */
			qcom,gpu-pwrlevel@4 {
				reg = <4>;
				qcom,gpu-freq = <320000000>;
				qcom,bus-freq = <2>;
				qcom,bus-min = <1>;
				qcom,bus-max = <2>;
				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
			};

			/* XO */
			qcom,gpu-pwrlevel@5 {
				reg = <5>;
				qcom,gpu-freq = <0>;
				qcom,bus-freq = <0>;
				qcom,bus-min = <0>;
				qcom,bus-max = <0>;
				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
			};
		};
	};
};
