
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))

/* External feature codes */
#define FC_UNKNOWN 0x0
#define FC_AA 0x1
#define FC_AB 0x2
#define FC_AC 0x3
#define FC_AD 0x4
#define FC_AE 0x5
#define FC_AF 0x6
#define FC_AG 0x7
#define FC_AH 0x8

/* Internal feature codes */
#define FC_Y0 0x00f1
#define FC_Y1 0x00f2
#define FC_Y2 0x00f3
#define FC_Y3 0x00f4
#define FC_Y4 0x00f5
#define FC_Y5 0x00f6
#define FC_Y6 0x00f7
#define FC_Y7 0x00f8
#define FC_Y8 0x00f9
#define FC_Y9 0x00fa
#define FC_YA 0x00fb
#define FC_YB 0x00fc
#define FC_YC 0x00fd
#define FC_YD 0x00fe
#define FC_YE 0x00ff
#define FC_YF 0x0100

/* Pcodes */
#define PCODE_UNKNOWN 0
#define PCODE_0 1
#define PCODE_1 2
#define PCODE_2 3
#define PCODE_3 4
#define PCODE_4 5
#define PCODE_5 6
#define PCODE_6 7
#define PCODE_7 8
#define PCODE_8 9

#define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode)

&msm_gpu {
	compatible = "qcom,adreno-gpu-gen7-2-0", "qcom,kgsl-3d0";
	status = "ok";
	reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,
		<0x03d50000 0x10000>, <0x3d8b000 0x2000>,
		<0x03d9e000 0x1000>, <0x10900000 0x80000>,
		<0x10048000 0x8000>, <0x10b05000 0x1000>;
	reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc",
		"isense_cntl", "cx_misc", "qdss_gfx", "qdss_etr",
		"qdss_tmc";
	interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "kgsl_3d0_irq";

	clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
		<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
		<&gpucc GPU_CC_AHB_CLK>,
		<&aoss_qmp QDSS_CLK>;
	clock-names = "gcc_gpu_memnoc_gfx",
			"gcc_gpu_snoc_dvm_gfx",
			"gpu_cc_ahb", "apb_pclk";

	qcom,gpu-model = "Adreno740";

	qcom,chipid = <0x43050a00>;

	qcom,no-nap;

	qcom,min-access-length = <32>;

	qcom,ubwc-mode = <4>;

	qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */

	qcom,tzone-names = "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3",
			"gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7";

	interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
	interconnect-names = "gpu_icc_path";

	qcom,bus-table-cnoc =
		<0>,   /* Off */
		<100>; /* On */

	qcom,bus-table-ddr =
		<MHZ_TO_KBPS(0, 4)>,    /* index=0 */
		<MHZ_TO_KBPS(547, 4) >, /* index=1 */
		<MHZ_TO_KBPS(768, 4) >, /* index=2 */
		<MHZ_TO_KBPS(1555, 4)>, /* index=3 */
		<MHZ_TO_KBPS(1708, 4)>, /* index=4 */
		<MHZ_TO_KBPS(2092, 4)>, /* index=5 */
		<MHZ_TO_KBPS(2736, 4)>, /* index=6 */
		<MHZ_TO_KBPS(3187, 4)>, /* index=7 */
		<MHZ_TO_KBPS(3686, 4)>, /* index=8 */
		<MHZ_TO_KBPS(4224, 4)>; /* index=9 */

	zap-shader {
		memory-region = <&gpu_micro_code_mem>;
	};

	qcom,gpu-mempools {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "qcom,gpu-mempools";

		/* 4K Page Pool configuration */
		qcom,gpu-mempool@0 {
			reg = <0>;
			qcom,mempool-page-size = <4096>;
			qcom,mempool-reserved = <2048>;
		};
		/* 8K Page Pool configuration */
		qcom,gpu-mempool@1 {
			reg = <1>;
			qcom,mempool-page-size = <8192>;
			qcom,mempool-reserved = <1024>;
		};
		/* 64K Page Pool configuration */
		qcom,gpu-mempool@2 {
			reg = <2>;
			qcom,mempool-page-size = <65536>;
			qcom,mempool-reserved = <256>;
		};
		/* 128K Page Pool configuration */
		qcom,gpu-mempool@3 {
			reg = <3>;
			qcom,mempool-page-size = <131072>;
			qcom,mempool-reserved = <128>;
		};
		/* 256K Page Pool configuration */
		qcom,gpu-mempool@4 {
			reg = <4>;
			qcom,mempool-page-size = <262144>;
			qcom,mempool-reserved = <80>;
		};
		/* 1M Page Pool configuration */
		qcom,gpu-mempool@5 {
			reg = <5>;
			qcom,mempool-page-size = <1048576>;
			qcom,mempool-reserved = <32>;
		};
	};
};

&soc {
	kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
		compatible = "qcom,kgsl-smmu-v2";
		reg = <0x03da0000 0x40000>;

		vddcx-supply = <&gpu_cc_cx_gdsc>;

		gfx3d_user: gfx3d_user {
			compatible = "qcom,smmu-kgsl-cb";
			iommus = <&kgsl_smmu 0x0 0x000>;
			qcom,iommu-dma = "disabled";
		};

		gfx3d_lpac: gfx3d_lpac {
			compatible = "qcom,smmu-kgsl-cb";
			iommus = <&kgsl_smmu 0x1 0x000>;
			qcom,iommu-dma = "disabled";
		};

		gfx3d_secure: gfx3d_secure {
			compatible = "qcom,smmu-kgsl-cb";
			iommus = <&kgsl_smmu 0x2 0x000>;
			qcom,iommu-dma = "disabled";
		};
	};

	gmu: qcom,gmu@3d69000 {
		compatible = "qcom,gen7-gmu";

		reg = <0x3d68000 0x37000>,
		      <0xb280000 0x10000>,
		      <0x03D40000 0x10000>;

		reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0";

		interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
			<0 305 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hfi", "gmu";

		regulator-names = "vddcx", "vdd";

		vddcx-supply = <&gpu_cc_cx_gdsc>;
		vdd-supply = <&gpu_cc_gx_gdsc>;

		clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
			<&gpucc GPU_CC_CXO_CLK>,
			<&gcc GCC_DDRSS_GPU_AXI_CLK>,
			<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
			<&gpucc GPU_CC_AHB_CLK>,
			<&gpucc GPU_CC_HUB_CX_INT_CLK>;

                clock-names = "gmu_clk", "cxo_clk", "axi_clk",
			"memnoc_clk", "ahb_clk", "hub_clk";

		qcom,gmu-freq-table = <220000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
					<550000000 RPMH_REGULATOR_LEVEL_SVS>;

		iommus = <&kgsl_smmu 0x5 0x000>;
		qcom,iommu-dma = "disabled";

		mboxes = <&qmp_aop 0>;
		mbox-names = "aop";

		qcom,ipc-core = <0x00400000 0x100000>;
	};

	coresight_cx_dgbc: qcom,gpu-coresight-cx {
		compatible = "qcom,gpu-coresight-cx";

		coresight-name = "coresight-gfx-cx";
		coresight-atid = <52>;

		out-ports {
			port {
				cx_dbgc_out_funnel_gfx: endpoint {
					remote-endpoint =
					  <&funnel_gfx_in_cx_dbgc>;
				};
			};
		};
	};

	coresight_gx_dgbc: qcom,gpu-coresight-gx {
		compatible = "qcom,gpu-coresight-gx";

		coresight-name = "coresight-gfx";
		coresight-atid = <53>;

		out-ports {
			port {
				gx_dbgc_out_funnel_gfx: endpoint {
					remote-endpoint =
					  <&funnel_gfx_in_gx_dbgc>;
				};
			};
		};
	};
};

&funnel_gfx {
	in-ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			funnel_gfx_in_gx_dbgc: endpoint {
			remote-endpoint =
				<&gx_dbgc_out_funnel_gfx>;
			};
		};

		port@1 {
			reg = <1>;
			funnel_gfx_in_cx_dbgc: endpoint {
			remote-endpoint =
				<&cx_dbgc_out_funnel_gfx>;
			};
		};
	};
};
