#include <dt-bindings/clock/qcom,gcc-sdxbaagha.h>

&soc {
	usb0: hsusb@a600000 {
		compatible = "qcom,dwc-usb3-msm";
		reg = <0xa600000 0x100000>;
		reg-names = "core_base";

		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		USB3_GDSC-supply = <&gcc_usb20_gdsc>;

		clocks = <&gcc GCC_USB20_MASTER_CLK>,
			<&gcc GCC_SYS_NOC_USB_SF_AXI_CLK>,
			<&gcc GCC_USB20_SLEEP_CLK>,
			<&gcc GCC_USB20_MOCK_UTMI_CLK>;

		clock-names = "core_clk", "iface_clk", "sleep_clk", "utmi_clk";

		resets = <&gcc GCC_USB20_BCR>;
		reset-names = "core_reset";

		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "pwr_event_irq";

		qcom,core-clk-rate = <60000000>;

		dwc3@a600000 {
			compatible = "snps,dwc3";
			reg = <0xa600000 0xd93c>;

			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			snps,disable-clk-gating;
			snps,has-lpm-erratum;
			snps,hird-threshold = /bits/ 8 <0x0>;
			snps,is-utmi-l1-suspend;
			snps,dis-u1-entry-quirk;
			snps,dis-u2-entry-quirk;
			maximum-speed = "high-speed";
			dr_mode = "otg";
			usb-role-switch;
		};
	};
};
