#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>

/ {
	model = "Qualcomm Technologies, Inc. SM6150";
	compatible = "qcom,sm6150";
	qcom,msm-name = "SM6150";
	qcom,msm-id = <355 0x0>;
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;
	memory { device_type = "memory"; reg = <0 0 0 0>; };

	aliases {
		serial0 = &uart2;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
			cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
			power-domains = <&CPU_PD0>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			i-cache-size = <0x8000>;
			d-cache-size = <0x8000>;
			next-level-cache = <&L2_0>;
			#cooling-cells = <2>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;

				L3_0: l3-cache {
				      compatible = "arm,arch-cache";
				      cache-size = <0x100000>;
				      cache-level = <3>;
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "psci";
			cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
			power-domains = <&CPU_PD1>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			i-cache-size = <0x8000>;
			d-cache-size = <0x8000>;
			next-level-cache = <&L2_100>;
			L2_100: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};


		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x200>;
			enable-method = "psci";
			cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
			power-domains = <&CPU_PD2>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			i-cache-size = <0x8000>;
			d-cache-size = <0x8000>;
			next-level-cache = <&L2_200>;
			L2_200: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x300>;
			enable-method = "psci";
			cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
			power-domains = <&CPU_PD3>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			i-cache-size = <0x8000>;
			d-cache-size = <0x8000>;
			next-level-cache = <&L2_300>;
			L2_300: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x400>;
			enable-method = "psci";
			cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
			power-domains = <&CPU_PD4>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			i-cache-size = <0x8000>;
			d-cache-size = <0x8000>;
			next-level-cache = <&L2_400>;
			L2_400: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x500>;
			enable-method = "psci";
			cpu-idle-states = <&SILVER_OFF &SILVER_PLL_OFF>;
			power-domains = <&CPU_PD5>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			i-cache-size = <0x8000>;
			d-cache-size = <0x8000>;
			next-level-cache = <&L2_500>;
			L2_500: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x600>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
			power-domains = <&CPU_PD6>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1740>;
			i-cache-size = <0x10000>;
			d-cache-size = <0x10000>;
			next-level-cache = <&L2_600>;
			#cooling-cells = <2>;
			L2_600: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x40000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x700>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
			power-domains = <&CPU_PD7>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1740>;
			i-cache-size = <0x10000>;
			d-cache-size = <0x10000>;
			next-level-cache = <&L2_700>;
			L2_700: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x40000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};

				core4 {
					cpu = <&CPU4>;
				};

				core5 {
					cpu = <&CPU5>;
				};

			};

			cluster1 {
				core0 {
					cpu = <&CPU6>;
				};

				core1 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	idle-states {
		SILVER_OFF: silver-c3 {  /* C3 */
			compatible = "arm,idle-state";
			idle-state-name = "pc";
			entry-latency-us = <549>;
			exit-latency-us = <901>;
			min-residency-us = <1774>;
			arm,psci-suspend-param = <0x40000003>;
			local-timer-stop;
		};

		SILVER_PLL_OFF: silver-c4 {  /* C4 */
			compatible = "arm,idle-state";
			idle-state-name = "rail-pc";
			entry-latency-us = <702>;
			exit-latency-us = <915>;
			min-residency-us = <4001>;
			arm,psci-suspend-param = <0x40000004>;
			local-timer-stop;
		};

		GOLD_OFF: gold-c3 {  /* C3 */
			compatible = "arm,idle-state";
			idle-state-name = "pc";
			entry-latency-us = <523>;
			exit-latency-us = <1244>;
			min-residency-us = <2207>;
			arm,psci-suspend-param = <0x40000003>;
			local-timer-stop;
		};

		GOLD_RAIL_OFF: gold-c4 {  /* C4 */
			compatible = "arm,idle-state";
			idle-state-name = "rail-pc";
			entry-latency-us = <526>;
			exit-latency-us = <1854>;
			min-residency-us = <5555>;
			arm,psci-suspend-param = <0x40000004>;
			local-timer-stop;
		};

		CLUSTER_OFF: cluster-d4 { /* D4 */
			compatible = "domain-idle-state";
			idle-state-name = "llcc-off";
			entry-latency-us = <2752>;
			exit-latency-us = <3048>;
			min-residency-us = <6118>;
			arm,psci-suspend-param = <0x41000044>;
		};

		CX_RET: cx-ret { /* Cx Ret */
			compatible = "domain-idle-state";
			idle-state-name = "llcc-off";
			entry-latency-us = <3263>;
			exit-latency-us = <4562>;
			min-residency-us = <8467>;
			arm,psci-suspend-param = <0x41001344>;
		};

		APSS_OFF: cluster-e3 { /* AOSS sleep */
			compatible = "domain-idle-state";
			idle-state-name = "llcc-off";
			entry-latency-us = <3638>;
			exit-latency-us = <6562>;
			min-residency-us = <9826>;
			arm,psci-suspend-param = <0x4100b344>;
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";

		CPU_PD0: cpu-pd0 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD1: cpu-pd1 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD2: cpu-pd2 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD3: cpu-pd3 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD4: cpu-pd4 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD5: cpu-pd5 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD6: cpu-pd6 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD7: cpu-pd7 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CLUSTER_PD: cluster-pd {
			#power-domain-cells = <0>;
			domain-idle-states = <&CLUSTER_OFF &CX_RET &APSS_OFF>;
		};
	};

	chosen { };

	soc: soc { };

	firmware: firmware { };

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hyp_region: hyp_region@85700000 {
			no-map;
			reg = <0x0 0x85700000 0x0 0x600000>;
		};

		xbl_aop_mem: xbl_aop_mem@85e00000 {
			no-map;
			reg = <0x0 0x85e00000 0x0 0x120000>;
		};

		aop_cmd_db: memory@85f20000 {
			compatible = "qcom,cmd-db";
			reg = <0x0 0x85f20000 0x0 0x20000>;
			no-map;
		};

		sec_apps_mem: sec_apps_region@85fff000 {
			no-map;
			reg = <0x0 0x85fff000 0x0 0x1000>;
		};

		smem_region: smem@86000000 {
			no-map;
			reg = <0x0 0x86000000 0x0 0x200000>;
		};

		removed_region: removed_region@86200000 {
			no-map;
			reg = <0x0 0x86200000 0x0 0x2d00000>;
		};

		pil_camera_mem: camera_region@8ab00000 {
			no-map;
			reg = <0x0 0x8ab00000 0x0 0x500000>;
		};

		pil_modem_mem: modem_region@8b000000 {
			no-map;
			reg = <0x0 0x8b000000 0x0 0x8400000>;
		};

		pil_video_mem: pil_video_region@93400000 {
			no-map;
			reg = <0x0 0x93400000 0x0 0x500000>;
		};

		wlan_msa_mem: wlan_msa_region@93900000 {
			no-map;
			reg = <0x0 0x93900000 0x0 0x200000>;
		};

		pil_cdsp_mem: cdsp_regions@93b00000 {
			no-map;
			reg = <0x0 0x93b00000 0x0 0x1e00000>;
		};

		pil_adsp_mem: pil_adsp_region@95900000 {
			no-map;
			reg = <0x0 0x95900000 0x0 0x1e00000>;
		};

		pil_ipa_fw_mem: ips_fw_region@97700000 {
			no-map;
			reg = <0x0 0x97700000 0x0 0x10000>;
		};

		pil_ipa_gsi_mem: ipa_gsi_region@97710000 {
			no-map;
			reg = <0x0 0x97710000 0x0 0x5000>;
		};

		pil_gpu_mem: gpu_region@97715000 {
			no-map;
			reg = <0x0 0x97715000 0x0 0x2000>;
		};

		qseecom_mem: qseecom_region {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0x0 0x9e400000 0x0 0x1400000>;
		};

		cdsp_sec_mem: cdsp_sec_regions@9f800000 {
			no-map;
			reg = <0x0 0x9f800000 0x0 0x1e00000>;
		};

		adsp_mem: adsp_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x800000>;
		};

		sdsp_mem: sdsp_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x400000>;
		};

		user_contig_mem: user_contig_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x1000000>;
		};

		qseecom_ta_mem: qseecom_ta_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x1000000>;
		};

		sp_mem: sp_region {  /* SPSS-HLOS ION shared mem */
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x800000>;
		};

		secure_display_memory: secure_display_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x8c00000>;
		};

		cont_splash_memory: splash_region {
			reg = <0x0 0x9c000000 0x0 0x0f00000>;
			label = "cont_splash_region";
		};

		dfps_data_memory: dfps_data_region@9cf00000 {
			reg = <0x0 0x9cf00000 0x0 0x0100000>;
			label = "dfps_data_region";
		};

		disp_rdump_memory: disp_rdump_region@9c000000 {
			reg = <0x0 0x9c000000 0x0 0x01000000>;
			label = "disp_rdump_region";
		};

		dump_mem: mem_dump_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			size = <0 0x2800000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x2000000>;
			linux,cma-default;
		};
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			clock-frequency = <38400000>;
			clock-output-names = "xo_board";
			#clock-cells = <0>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			clock-output-names = "sleep_clk";
			#clock-cells = <0>;
		};
	};
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	apps_rsc: rsc@18200000 {
		label = "apps_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0x18200000 0x10000>,
		      <0x18210000 0x10000>,
		      <0x18220000 0x10000>;
		reg-names = "drv-0", "drv-1", "drv-2";
		qcom,drv-count = <3>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&CLUSTER_PD>;

		apps_rsc_drv2: drv@2 {
			qcom,drv-id = <2>;
			qcom,tcs-offset = <0xd00>;
			channel@0 {
				qcom,tcs-config = <ACTIVE_TCS    2>,
						  <SLEEP_TCS     3>,
						  <WAKE_TCS      3>,
						  <CONTROL_TCS   1>,
						  <FAST_PATH_TCS 0>;
			};

			rpmhcc: clock-controller {
				compatible = "qcom,sm6150-rpmh-clk";
				#clock-cells = <1>;
				status = "okay";
			};
		};
	};

	disp_rsc: rsc@af20000 {
		label = "disp_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0xaf20000 0x10000>;
		reg-names = "drv-0";
		qcom,drv-count = <1>;
		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;

		disp_rsc_drv0: drv@0 {
			qcom,drv-id = <0>;
			qcom,tcs-offset = <0x1c00>;
			channel@0 {
				qcom,tcs-config = <SLEEP_TCS     1>,
						  <WAKE_TCS      1>,
						  <ACTIVE_TCS    2>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 0>;
			};
		};
	};

	intc: interrupt-controller@17a00000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x20000>;
		reg = <0x17a00000 0x10000>,     /* GICD */
		      <0x17a60000 0x100000>;    /* GICR * 8 */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&intc>;
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};

	timer@17c20000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17c20000 0x1000>;
		clock-frequency = <19200000>;

		frame@17c21000 {
			frame-number = <0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c21000 0x1000>,
			      <0x17c22000 0x1000>;
		};

		frame@17c23000 {
			frame-number = <1>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c23000 0x1000>;
			status = "disabled";
		};

		frame@17c25000 {
			frame-number = <2>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c25000 0x1000>;
			status = "disabled";
		};

		frame@17c27000 {
			frame-number = <3>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c27000 0x1000>;
			status = "disabled";
		};

		frame@17c29000 {
			frame-number = <4>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c29000 0x1000>;
			status = "disabled";
		};

		frame@17c2b000 {
			frame-number = <5>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c2b000 0x1000>;
			status = "disabled";
		};

		frame@17c2d000 {
			frame-number = <6>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c2d000 0x1000>;
			status = "disabled";
		};
	};

	pdc: interrupt-controller@b220000 {
		compatible = "qcom,sm6150-pdc", "qcom,pdc";
		reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
		qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
		#interrupt-cells = <2>;
		interrupt-parent = <&intc>;
		interrupt-controller;
	};

	qcom,msm-rtb {
		compatible = "qcom,msm-rtb";
		qcom,rtb-size = <0x100000>;
	};

	thermal_zones: thermal-zones {
	};

	qupv3_id_1: geniqup@8c0000 {
		compatible = "qcom,geni-se-qup";
		reg = <0xac0000 0x6000>;
		ranges;
		#address-cells = <1>;
		#size-cells = <1>;
		status = "ok";

		uart2: serial@880000 {
			compatible = "qcom,geni-debug-uart";
			reg = <0x880000 0x4000>;
			clock-names = "se";
			interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
			status = "ok";
		};
	};

	soc-sleep-stats@c3f0000 {
		compatible = "qcom,rpmh-sleep-stats-legacy";
		reg = <0xc3f0000 0x400>;
		ss-name = "modem", "adsp", "adsp_island",
			  "cdsp", "slpi", "slpi_island",
			  "apss";
	};
};

#include "sm6150-pinctrl.dtsi"
#include "sm6150-thermal.dtsi"
