&soc {
	/* QUPv3_0 wrapper instance */
	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
		compatible = "qcom,geni-se-qup";
		reg = <0x9c0000 0x2000>;
		#address-cells = <1>;
		#size-cells = <1>;
		clock-names = "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		/*
		 * iommus = <&apps_smmu 0xa3 0x0>;
		 * qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
		 * qcom,iommu-geometry = <0x40000000 0x10000000>;
		 * qcom,iommu-dma = "fastmap";
		 * dma-coherent;
		 */
		ranges;
		status = "ok";

		/*PORed Debug UART Instance */
		qupv3_se3_2uart: qcom,qup_uart@98c000 {
			compatible = "qcom,geni-debug-uart";
			reg = <0x98c000 0x4000>;
			reg-names = "se_phys";
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "se";
			clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
			/*
			 * interconnect-names = "qup-core", "qup-config", "qup-memory";
			 * interconnects =
			 * <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
			 * <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
			 * <&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
			 */
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&qupv3_se3_2uart_tx_active>, <&qupv3_se3_2uart_rx_active>;
			pinctrl-1 = <&qupv3_se3_2uart_sleep>;
			status = "disabled";
		};
	};
};
