//#include <dt-bindings/clock/mdss-7nm-pll-clk.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,dispcc-sm8150.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interconnect/qcom,sm8150.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>

&soc {
	mdss_mdp: qcom,mdss_mdp@ae00000 {
		compatible = "qcom,sde-kms";
		reg = <0x0ae00000 0x84208>,
		      <0x0aeb0000 0x2008>,
		      <0x0aeac000 0x214>;
		reg-names = "mdp_phys",
			"vbif_phys",
			"regdma_phys";

		clocks =
			<&gcc GCC_DISP_HF_AXI_CLK>,
			<&gcc GCC_DISP_SF_AXI_CLK>,
			<&dispcc DISP_CC_MDSS_AHB_CLK>,
			<&dispcc DISP_CC_MDSS_MDP_CLK>,
			<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
			<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
			<&dispcc DISP_CC_MDSS_ROT_CLK>;
		clock-names = "gcc_bus", "gcc_nrt_bus",
				"iface_clk", "core_clk", "vsync_clk",
				"lut_clk", "rot_clk";
		clock-rate = <0 0 0 300000000 19200000 300000000 19200000>;
		clock-max-rate = <0 0 0 460000000 19200000 460000000
					460000000>;

		sde-vdd-supply = <&mdss_core_gdsc>;
		mmcx-supply = <&VDD_MMCX_LEVEL>;

		/* interrupt config */
		interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <1>;
		iommus = <&apps_smmu 0x800 0x420>;

		#address-cells = <1>;
		#size-cells = <0>;

		#power-domain-cells = <0>;

		/* hw blocks */
		qcom,sde-off = <0x1000>;
		qcom,sde-len = <0x45c>;

		qcom,sde-ctl-off = <0x2000 0x2200 0x2400
				     0x2600 0x2800 0x2a00>;
		qcom,sde-ctl-size = <0x1e0>;
		qcom,sde-ctl-display-pref = "primary", "none", "none",
			    "none", "none", "none";

		qcom,sde-mixer-off = <0x45000 0x46000 0x47000
				      0x48000 0x49000 0x4a000>;
		qcom,sde-mixer-size = <0x320>;
		qcom,sde-mixer-display-pref = "primary", "none", "none",
					      "none", "none", "none";

		qcom,sde-mixer-cwb-pref = "none", "none", "cwb",
					      "cwb", "cwb", "cwb";

		qcom,sde-dspp-top-off = <0x1300>;
		qcom,sde-dspp-top-size = <0x80>;
		qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>;
		qcom,sde-dspp-size = <0x1800>;

		qcom,sde-dest-scaler-top-off = <0x00061000>;
		qcom,sde-dest-scaler-top-size = <0x1c>;
		qcom,sde-dest-scaler-off = <0x800 0x1000>;
		qcom,sde-dest-scaler-size = <0xa0>;

		qcom,sde-wb-off = <0x66000>;
		qcom,sde-wb-size = <0x2c8>;
		qcom,sde-wb-xin-id = <6>;
		qcom,sde-wb-id = <2>;
		qcom,sde-wb-clk-ctrl = <0x3b8 24>;
		qcom,sde-wb-clk-status = <0x3bc 20>;

		qcom,sde-intf-off = <0x6b000 0x6b800
					0x6c000 0x6c800>;
		qcom,sde-intf-size = <0x2b8>;
		qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";

		qcom,sde-pp-off = <0x71000 0x71800
					  0x72000 0x72800 0x73000 0x73800>;
		qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>;
		qcom,sde-pp-size = <0xd4>;
		qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>;

		qcom,sde-merge-3d-off = <0x84000 0x84100 0x84200>;
		qcom,sde-merge-3d-size = <0x100>;

		qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0 0x0>;

		qcom,sde-cdm-off = <0x7a200>;
		qcom,sde-cdm-size = <0x224>;

		qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>;
		qcom,sde-dsc-size = <0x140>;
		qcom,sde-dsc-pair-mask = <2 1 4 3>;

		qcom,sde-roi-misr-off = <0x82820 0x82880 0x828e0
					0x82940 0x829a0 0x82a00>;
		qcom,sde-roi-misr-size = <0x60>;

		qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0
							0x30e0 0x30e0 0x30e0>;
		qcom,sde-dither-version = <0x00010000>;
		qcom,sde-dither-size = <0x20>;

		qcom,sde-sspp-type = "vig", "vig", "vig", "vig",
					"dma", "dma", "dma", "dma";

		qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000
					0x25000 0x27000 0x29000 0x2b000>;
		qcom,sde-sspp-src-size = <0x1f0>;

		qcom,sde-sspp-xin-id = <0 4 8 12
					1 5 9 13>;
		qcom,sde-sspp-excl-rect = <1 1 1 1
						1 1 1 1>;
		qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>;
		qcom,sde-smart-dma-rev = "smart_dma_v2p5";

		qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>;

		qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
						0xb0 0xc8 0xe0 0xf8 0x110>;

		qcom,sde-max-per-pipe-bw-kbps = <4500000 4500000
						 4500000 4500000
						 4500000 4500000
						 4500000 4500000>;

		/* offsets are relative to "mdp_phys + qcom,sde-off */
		qcom,sde-sspp-clk-ctrl =
				<0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>,
				 <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>;
		qcom,sde-sspp-clk-status =
				<0x2b0 0>, <0x2b8 0>, <0x2c0 0>, <0x2c8 0>,
				 <0x2b0 12>, <0x2b8 12>, <0x2c8 12>, <0x2c8 14>;
		qcom,sde-sspp-csc-off = <0x1a00>;
		qcom,sde-csc-type = "csc-10bit";
		qcom,sde-qseed-sw-lib-rev = "qseedv3";
		qcom,sde-qseed-scalar-version = <0x3000>;
		qcom,sde-sspp-qseed-off = <0xa00>;
		qcom,sde-mixer-linewidth = <2560>;
		qcom,sde-sspp-linewidth = <4096>;
		qcom,sde-wb-linewidth = <4096>;
		qcom,sde-mixer-blendstages = <0xb>;
		qcom,sde-highest-bank-bit = <0x2>;
		qcom,sde-ubwc-version = <0x30000000>;
		qcom,sde-ubwc-bw-calc-version = <0x1>;
		qcom,sde-smart-panel-align-mode = <0xc>;
		qcom,sde-panic-per-pipe;
		qcom,sde-has-cdp;
		qcom,sde-has-src-split;
		qcom,sde-pipe-order-version = <0x1>;
		qcom,sde-has-dim-layer;
		qcom,sde-has-idle-pc;
		qcom,sde-max-dest-scaler-input-linewidth = <2048>;
		qcom,sde-max-dest-scaler-output-linewidth = <2560>;
		qcom,sde-max-bw-low-kbps = <12800000>;
		qcom,sde-max-bw-high-kbps = <12800000>;
		qcom,sde-min-core-ib-kbps = <2400000>;
		qcom,sde-min-llcc-ib-kbps = <800000>;
		qcom,sde-min-dram-ib-kbps = <800000>;
		qcom,sde-dram-channels = <2>;
		qcom,sde-num-nrt-paths = <0>;
		qcom,sde-dspp-ad-version = <0x00040000>;
		qcom,sde-dspp-ad-off = <0x28000 0x27000>;

		qcom,sde-vbif-off = <0>;
		qcom,sde-vbif-size = <0x1040>;
		qcom,sde-vbif-id = <0>;
		qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
		qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;

		qcom,sde-vbif-default-ot-wr-limit = <16>;
		qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2 124416000 6 497664000 16>;

		qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
		qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
		qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 6>;
		qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 6>;

		qcom,sde-qos-refresh-rates = <120 240>;
		qcom,sde-danger-lut = <0x3ffff 0x3ffff 0x0 0x0 0x0 0x3fffff 0x3fffff>,
		<0x3ffffff 0x3ffffff 0x0 0x0 0x0 0x3ffffff 0x3fffff>;

		qcom,sde-safe-lut = <0xFE00 0xFE00 0xFFFF 0x01 0x03FF 0xF800 0xF800>,
		<0xE000 0xE000 0xFFFF 0x01 0x03FF 0xE000 0xF800>;

		qcom,sde-creq-lut = <0x00112234 0x45566777 0x00112236 0x67777777
				0x00112234 0x45566777 0x00112236 0x67777777
				0x0        0x0         0x0        0x0
				0x77776666 0x66666540 0x77776666 0x66666540
				0x77776541 0x00000000 0x77776541 0x00000000
				0x00123445 0x56677777 0x00123667 0x77777777
				0x00123445 0x56677777 0x00123667 0x77777777>,
				<0x02344455 0x56667777 0x02366677 0x77777777
				0x02344455 0x56667777 0x02366677 0x77777777
				0x0        0x0        0x0        0x0
				0x77776666 0x66666540 0x77776666 0x66666540
				0x77776541 0x00000000 0x77776541 0x00000000
				0x02344455 0x56667777 0x02366677 0x77777777
				0x00123445 0x56677777 0x00123667 0x77777777>;

		qcom,sde-cdp-setting = <1 1>, <1 0>;

		qcom,sde-qos-cpu-mask = <0x3>;
		qcom,sde-qos-cpu-mask-performance = <0xf>;
		qcom,sde-qos-cpu-dma-latency = <300>;
		qcom,sde-qos-cpu-irq-latency = <300>;

		/* offsets are relative to "mdp_phys + qcom,sde-off */
		qcom,sde-reg-dma-off = <0>;
		qcom,sde-reg-dma-version = <0x00010001>;
		qcom,sde-reg-dma-trigger-off = <0x119c>;

		qcom,sde-secure-sid-mask = <0x4200801>;

		qcom,sde-reg-bus,vectors-KBps = <0 0>,
				<0 74000>,
				<0 148000>,
				<0 265000>;

		/* data and reg bus scale settings */
		interconnects =
			<&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
			<&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>,
			<&gem_noc MASTER_APPSS_PROC
				&config_noc SLAVE_DISPLAY_CFG>;
		interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1",
			"qcom,sde-reg-bus";

		qcom,sde-ib-bw-vote = <2500000 0 800000>;

		qcom,sde-sspp-vig-blocks {
			vcm@0 {
				cell-index = <0>;
				com,sde-vig-csc-off = <0x1a00>;
				qcom,sde-vig-qseed-off = <0xa00>;
				qcom,sde-vig-qseed-size = <0xa0>;
				qcom,sde-vig-gamut = <0x1d00 0x00050000>;
				qcom,sde-vig-igc = <0x1d00 0x00050000>;
				qcom,sde-vig-inverse-pma;
			};
		};

		qcom,sde-sspp-dma-blocks {
			dgm@0 {
				cell-index = <0>;
				qcom,sde-dma-igc = <0x400 0x00050000>;
				qcom,sde-dma-gc = <0x600 0x00050000>;
				qcom,sde-dma-inverse-pma;
				qcom,sde-dma-csc-off = <0x200>;
			};
			dgm@1 {
				cell-index = <1>;
				qcom,sde-dma-igc = <0x1400 0x00050000>;
				qcom,sde-dma-gc = <0x600 0x00050000>;
				qcom,sde-dma-inverse-pma;
				qcom,sde-dma-csc-off = <0x1200>;
			};
		};

		qcom,sde-dspp-blocks {
			qcom,sde-dspp-igc = <0x0 0x00030001>;
			qcom,sde-dspp-hsic = <0x800 0x00010007>;
			qcom,sde-dspp-memcolor = <0x880 0x00010007>;
			qcom,sde-dspp-hist = <0x800 0x00010007>;
			qcom,sde-dspp-sixzone= <0x900 0x00010007>;
			qcom,sde-dspp-vlut = <0xa00 0x00010008>;
			qcom,sde-dspp-gamut = <0x1000 0x00040001>;
			qcom,sde-dspp-pcc = <0x1700 0x00040000>;
			qcom,sde-dspp-gc = <0x17c0 0x00010008>;
			qcom,sde-dspp-dither = <0x82c 0x00010007>;
			qcom,sde-dspp-roi-misr = <0x1200 0x00010000>;
		};

		qcom,platform-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,platform-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "mmcx";
				qcom,supply-min-voltage = <0>;
				qcom,supply-max-voltage = <0>;
				qcom,supply-enable-load = <0>;
				qcom,supply-disable-load = <0>;
			};
		};
	};

	mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
		compatible = "qcom,dsi-ctrl-hw-v2.3";
		label = "dsi-ctrl-0";
		cell-index = <0>;
		reg = <0xae94000 0x400>,
			<0xaf0f000 0x4>,
			<0x0ae36000 0x300>;
		reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base";
		interrupt-parent = <&mdss_mdp>;
		interrupts = <4 0>;
		clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
			<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
			<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
			<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
			<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
			<&dispcc DISP_CC_MDSS_ESC0_CLK>,
			<&rpmhcc RPMH_CXO_CLK>;
		clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
					"pixel_clk", "pixel_clk_rcg",
					"esc_clk", "xo";

		qcom,ctrl-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,ctrl-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "vdda-1p2";
				qcom,supply-min-voltage = <1200000>;
				qcom,supply-max-voltage = <1200000>;
				qcom,supply-enable-load = <21800>;
				qcom,supply-disable-load = <0>;
			};
		};
		qcom,core-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,core-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "refgen";
				qcom,supply-min-voltage = <0>;
				qcom,supply-max-voltage = <0>;
				qcom,supply-enable-load = <0>;
				qcom,supply-disable-load = <0>;
			};
		};
	};

	mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
		compatible = "qcom,dsi-ctrl-hw-v2.3";
		label = "dsi-ctrl-1";
		cell-index = <1>;
		reg = <0xae96000 0x400>,
			<0xaf0f000 0x4>,
			<0x0ae37000 0x300>;
		reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base";
		interrupt-parent = <&mdss_mdp>;
		interrupts = <5 0>;
		clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
			<&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
			<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
			<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
			<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
			<&dispcc DISP_CC_MDSS_ESC1_CLK>,
			<&rpmhcc RPMH_CXO_CLK>;
		clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
					"pixel_clk", "pixel_clk_rcg",
					"esc_clk", "xo";
		qcom,ctrl-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,ctrl-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "vdda-1p2";
				qcom,supply-min-voltage = <1200000>;
				qcom,supply-max-voltage = <1200000>;
				qcom,supply-enable-load = <21800>;
				qcom,supply-disable-load = <0>;
			};
		};
		qcom,core-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,core-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "refgen";
				qcom,supply-min-voltage = <0>;
				qcom,supply-max-voltage = <0>;
				qcom,supply-enable-load = <0>;
				qcom,supply-disable-load = <0>;
			};
		};
	};

	mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 {
		compatible = "qcom,dsi-phy-v4.0";
		label = "dsi-phy-0";
		cell-index = <0>;
		#clock-cells = <1>;

		reg = <0xae94400 0xa00>,
		      <0xae94900 0x400>,
		      <0xae94200 0xa0>;
		reg-names = "dsi_phy", "pll_base", "dyn_refresh_base";
		pll-label = "dsi_pll_5nm";

		qcom,platform-strength-ctrl = [55 03
						55 03
						55 03
						55 03
						55 00];
		qcom,platform-lane-config = [00 00 0a 0a
						00 00 0a 0a
						00 00 0a 0a
						00 00 0a 0a
						00 00 8a 8a];
		qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
		qcom,phy-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;
			qcom,phy-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "vdda-0p9";
				qcom,supply-min-voltage = <880000>;
				qcom,supply-max-voltage = <880000>;
				qcom,supply-enable-load = <36000>;
				qcom,supply-disable-load = <0>;
			};
		};
	};

	mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96400 {
		compatible = "qcom,dsi-phy-v4.0";
		label = "dsi-phy-1";
		cell-index = <1>;
		#clock-cells = <1>;
		reg = <0xae96400 0xa00>,
		      <0xae96900 0x400>,
		      <0xae96200 0xa0>;
		reg-names = "dsi_phy", "pll_base", "dyn_refresh_base";
		pll-label = "dsi_pll_5nm";

		qcom,platform-strength-ctrl = [55 03
						55 03
						55 03
						55 03
						55 00];
		qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
		qcom,platform-lane-config = [00 00 0a 0a
						00 00 0a 0a
						00 00 0a 0a
						00 00 0a 0a
						00 00 8a 8a];
		qcom,phy-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;
			qcom,phy-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "vdda-0p9";
				qcom,supply-min-voltage = <880000>;
				qcom,supply-max-voltage = <880000>;
				qcom,supply-enable-load = <36000>;
				qcom,supply-disable-load = <0>;
			};
		};
	};

	qcom_msmhdcp: qcom,msm_hdcp {
		compatible = "qcom,msm-hdcp";
		cell-index = <0>;
	};

	sde_dp: qcom,dp_display@0{
		cell-index = <0>;
		compatible = "qcom,dp-display";

		reg =	<0xae90000 0x0dc>,
			<0xae90200 0x0c0>,
			<0xae90400 0x508>,
			<0xae90a00 0x098>,
			<0x88eaa00 0x200>,
			<0x88ea200 0x200>,
			<0x88ea600 0x200>,
			<0xaf02000 0x1a0>,
			<0x780000 0x621c>,
			<0x88ea000 0x200>,
			<0x88e8000 0x20>,
			<0x0aee1000 0x034>,
			<0xae91000 0x098>,
			<0xaf03000 0x8>;
		reg-names = "dp_ahb", "dp_aux", "dp_link",
			"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
			"dp_mmss_cc", "qfprom_physical", "dp_pll",
			"usb3_dp_com", "hdcp_physical", "dp_p1", "gdsc";

		interrupt-parent = <&mdss_mdp>;
		interrupts = <12 0>;

		#clock-cells = <1>;
		clocks =  <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
			 <&rpmhcc RPMH_CXO_CLK>,
			 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
			 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
			 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
			 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
			 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
			 <&sde_dp 1>,
			 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
			 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
			 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
		clock-names = "core_aux_clk", "rpmh_cxo_clk",
			"core_usb_ref_clk_src", "core_usb_pipe_clk",
			"link_clk_src", "link_iface_clk",
			"pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg",
			"strm0_pixel_clk", "strm1_pixel_clk";

		qcom,pll-revision = "7nm";
		qcom,phy-version = <0x420>;
		qcom,aux-cfg0-settings = [20 00];
		qcom,aux-cfg1-settings = [24 13];
		qcom,aux-cfg2-settings = [28 24];
		qcom,aux-cfg3-settings = [2c 00];
		qcom,aux-cfg4-settings = [30 0a];
		qcom,aux-cfg5-settings = [34 26];
		qcom,aux-cfg6-settings = [38 0a];
		qcom,aux-cfg7-settings = [3c 03];
		qcom,aux-cfg8-settings = [40 b7];
		qcom,aux-cfg9-settings = [44 03];

		qcom,max-pclk-frequency-khz = <675000>;

		qcom,mst-enable;
		qcom,dsc-feature-enable;
		qcom,fec-feature-enable;
		qcom,max-dp-dsc-blks = <2>;
		qcom,max-dp-dsc-input-width-pixs = <2048>;

		qcom,msm-hdcp = <&qcom_msmhdcp>;

		qcom,ctrl-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,ctrl-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "vdda-1p2";
				qcom,supply-min-voltage = <1200000>;
				qcom,supply-max-voltage = <1200000>;
				qcom,supply-enable-load = <21800>;
				qcom,supply-disable-load = <0>;
			};
		};

		qcom,phy-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,phy-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "vdda-0p9";
				qcom,supply-min-voltage = <880000>;
				qcom,supply-max-voltage = <880000>;
				qcom,supply-enable-load = <36000>;
				qcom,supply-disable-load = <0>;
			};
		};

		qcom,core-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,core-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "refgen";
				qcom,supply-min-voltage = <0>;
				qcom,supply-max-voltage = <0>;
				qcom,supply-enable-load = <0>;
				qcom,supply-disable-load = <0>;
			};
		};

		qcom,pll-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,pll-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "vdd_mx";
				qcom,supply-min-voltage =
						<RPMH_REGULATOR_LEVEL_TURBO>;
				qcom,supply-max-voltage =
						<RPMH_REGULATOR_LEVEL_MAX>;
				qcom,supply-enable-load = <0>;
				qcom,supply-disable-load = <0>;
			};
		};
	};

	smmu_sde_sec: qcom,smmu_sde_sec_cb {
		compatible = "qcom,smmu_sde_sec";
		iommus = <&apps_smmu 0x801 0x420>;
		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
		qcom,iommu-vmid = <0xa>;
	};

	smmu_sde_unsec:qcom,smmu_sde_unsec_cb {
		compatible = "qcom,smmu_sde_unsec";
		iommus = <&apps_smmu 0x800 0x420>;
		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
		qcom,iommu-earlymap; /* for cont-splash */
	};
};
