&soc {
	hwevent {
		compatible = "qcom,coresight-hwevent";

		coresight-name = "coresight-hwevent";
		coresight-csr = <&csr>;
		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	apss_tgu: tgu@9900000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b999>;
		reg = <0x09900000 0x1000>;
		reg-names = "tgu-base";
		tgu-steps = <3>;
		tgu-conditions = <4>;
		tgu-regs = <8>;
		tgu-timer-counters = <3>;
		interrupts = <0 53 1>, <0 54 1>, <0 55 1>, <0 56 1>;
		coresight-name = "coresight-tgu-apss";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	csr: csr@8001000 {
		compatible = "qcom,coresight-csr";
		reg = <0x8001000 0x1000>;
		reg-names = "csr-base";

		coresight-name = "coresight-csr";
		qcom,usb-bam-support;
		qcom,hwctrl-set-support;
		qcom,set-byte-cntr-support;
		qcom,perflsheot-set-support;

		qcom,blk-size = <1>;
		qcom,flushperiod = <8>;
	};

	swao_csr: csr@8a03000 {
		compatible = "qcom,coresight-csr";
		reg = <0x8a03000 0x1000>;
		reg-names = "csr-base";

		coresight-name = "coresight-swao-csr";

		qcom,timestamp-support;
		qcom,aodbg-csr-support;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		qcom,blk-size = <1>;
	};

	stm: stm@8002000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb962>;

		reg = <0x8002000 0x1000>,
		      <0xe280000 0x180000>;
		reg-names = "stm-base", "stm-stimulus-base";

		coresight-name = "coresight-stm";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		out-ports {
			port {
				stm_out_funnel_in0: endpoint {
					remote-endpoint = <&funnel_in0_in_stm>;
				};
			};
		};
	};

	tpdm_center: tpdm@8b58000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x8b58000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-center";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				tpdm_dl_ct_out_tpda0: endpoint {
					remote-endpoint =
					<&tpda0_in_tpdm_dl_ct>;
				};
			};
		};
	};

	tpdm_gpu: tpdm@8940000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x8940000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-gpu";

		status = "disabled";
		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				tpdm_gpu_out_funnel_gpu: endpoint {
					remote-endpoint =
					<&funnel_gpu_in_tpdm_gpu>;
				};
			};
		};
	};

	modem_rfxe: modem_rfxe {
		compatible = "qcom,coresight-dummy";

		coresight-name = "coresight-modem-rfxe";
		qcom,dummy-source;
		out-ports {
			port {
				modem_rxfe_out_funnel_in1: endpoint {
					remote-endpoint =
					<&funnel_in1_in_modem_rxfe>;
				};
			};
		};
	};

	audio_etm0: audio_etm0 {
		compatible = "qcom,coresight-remote-etm";
		coresight-name = "coresight-audio-etm0";

		qcom,inst-id = <5>;
		out-ports {
			port {
				audio_etm0_out_funnel_lpass: endpoint {
					remote-endpoint =
					<&funnel_lpass_in_audio_etm0>;
				};
			};
		};
	};

	snoc: snoc {
		compatible = "qcom,coresight-dummy";
		coresight-name = "coresight-snoc";

		qcom,dummy-source;

		out-ports {
			port {
				snoc_out_funnel_in0: endpoint {
					remote-endpoint =
					<&funnel_in0_in_snoc>;
				};
			};
		};
	};

	tpdm_lpass: tpdm@8a26000 {
		compatible = "qcom,coresight-dummy";

		coresight-name = "coresight-tpdm-lpass";
		qcom,dummy-source;
		out-ports {
			port {
				tpdm_lpass_out_funnel_lpass: endpoint {
					remote-endpoint =
					<&funnel_lpass_in_tpdm_lpass>;
				};
			};
		};
	};

	tpdm_ddr0: tpdm@8a50000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x8a50000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-ddr";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		status = "disabled";
		out-ports {
			port {
				tpdm_ddr0_out_funnel_ddr: endpoint {
					remote-endpoint =
					<&funnel_ddr_in_tpdm_ddr0>;
				};
			};
		};
	};

	tpdm_ddr1: tpdm@8a51000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x8a51000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-shrm";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		status = "disabled";
		out-ports {
			port {
				tpdm_ddr1_out_funnel_ddr: endpoint {
					remote-endpoint =
					<&funnel_ddr_in_tpdm_ddr1>;
				};
			};
		};
	};

	tpdm_vsense: tpdm@8840000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x8840000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-vsense";

		status = "disabled";
		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				tpdm_vsense_out_tpda15: endpoint {
					remote-endpoint =
					<&tpda15_in_tpdm_vsense>;
				};
			};
		};
	};

	tpdm_dcc: tpdm@8870000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x8870000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-dcc";

		qcom,hw-enable-check;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		qcom,cmb-msr-skip;
		out-ports {
			port {
				tpdm_dcc_out_tpda12: endpoint {
					remote-endpoint =
					<&tpda12_in_tpdm_dcc>;
				};
			};
		};
	};

	tpdm_prng: tpdm@884c000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x884c000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-prng";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		qcom,cmb-msr-skip;
		out-ports {
			port {
				tpdm_prng_out_tpda14: endpoint {
					remote-endpoint =
					<&tpda14_in_tpdm_prng>;
				};
			};
		};
	};

	tpdm_qm: tpdm@89d0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x89d0000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-qm";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				tpdm_qm_out_tpda16: endpoint {
					remote-endpoint =
					<&tpda16_in_tpdm_qm>;
				};
			};
		};
	};

	tpdm_west: tpdm@8a58000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x8a58000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-west";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				tpdm_west_out_tpda17: endpoint {
					remote-endpoint =
					<&tpda17_in_tpdm_west>;
				};
			};
		};
	};

	tpdm_pimem: tpdm@8850000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x8850000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-pimem";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		qcom,cmb-msr-skip;
		out-ports {
			port {
				tpdm_pimem_out_tpda21: endpoint {
					remote-endpoint =
					<&tpda21_in_tpdm_pimem>;
				};
			};
		};
	};

	tpdm_mapss: tpdm@8a01000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x8a01000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-mapss";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		qcom,cmb-msr-skip;
		out-ports {
			port {
				tpdm_mapss_out_tpda_mapss: endpoint {
					remote-endpoint =
					<&tpda_mapss_in_tpdm_mapss>;
				};
			};
		};
	};

	tpdm_sdcc_2: tpdm@89b9000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x89b9000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-sdcc-2";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		qcom,cmb-msr-skip;
		status = "disabled";
		out-ports {
			port {
				tpdm_sdcc2_out_tpda20: endpoint {
					remote-endpoint =
					<&tpda20_in_tpdm_sdcc2>;
				};
			};
		};
	};

	tpdm_sdcc_1: tpdm@89b8000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x89b8000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-sdcc-1";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		qcom,cmb-msr-skip;
		status = "disabled";
		out-ports {
			port {
				tpdm_sdcc1_out_tpda19: endpoint {
					remote-endpoint =
					<&tpda19_in_tpdm_sdcc1>;
				};
			};
		};
	};

	tpdm_spdm: tpdm@800f000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x800f000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-spdm";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		qcom,cmb-msr-skip;
		out-ports {
			port {
				tpdm_spdm_out_tpda18: endpoint {
					remote-endpoint =
					<&tpda18_in_tpdm_spdm>;
				};
			};
		};
	};

	tpdm_wcss: tpdm@899c000 {
		compatible = "qcom,coresight-dummy";
		coresight-name = "coresight-tpdm-wcss";
		qcom,dummy-source;

		out-ports {
			port {
				tpdm_wcss_out_funnel_wcss: endpoint {
					remote-endpoint =
					<&funnel_wcss_in_tpdm_wcss>;
				};
			};
		};
	};

	funnel_wcss: funnel@899e000 {
		compatible = "arm,coresight-static-funnel";
		coresight-name = "coresight-funnel-wcss";

		out-ports {
			port {
				funnel_wcss_out_funnel_in1: endpoint {
					remote-endpoint =
					<&funnel_in1_in_funnel_wcss>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@1 {
				reg = <1>;
				funnel_wcss_in_tpdm_wcss: endpoint {
					remote-endpoint =
					<&tpdm_wcss_out_funnel_wcss>;
				};
			};
		};
	};

	modem_etm0: modem_etm0 {
		compatible = "qcom,coresight-remote-etm";
		coresight-name = "coresight-modem-etm0";

		qcom,inst-id = <2>;

		out-ports {
			port {
				modem_etm0_out_funnel_in1: endpoint {
					remote-endpoint =
					<&funnel_in1_in_modem_etm0>;
				};
			};
		};
	};

	etm0: etm@9040000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;
		reg = <0x9040000 0x1000>;
		cpu = <&CPU0>;
		qcom,tupwr-disable;
		coresight-name = "coresight-etm0";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				etm0_out_funnel_apss0: endpoint {
					remote-endpoint =
					<&funnel_apss0_in_etm0>;
				};
			};
		};
	};

	etm1: etm@9140000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;
		reg = <0x9140000 0x1000>;
		cpu = <&CPU1>;
		qcom,tupwr-disable;
		coresight-name = "coresight-etm1";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				etm1_out_funnel_apss0: endpoint {
					remote-endpoint =
					<&funnel_apss0_in_etm1>;
				};
			};
		};
	};

	etm2: etm@9240000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;
		reg = <0x9240000 0x1000>;
		cpu = <&CPU2>;
		qcom,tupwr-disable;
		coresight-name = "coresight-etm2";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				etm2_out_funnel_apss0: endpoint {
					remote-endpoint =
					<&funnel_apss0_in_etm2>;
				};
			};
		};
	};

	etm3: etm@9340000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;
		reg = <0x9340000 0x1000>;
		cpu = <&CPU3>;
		qcom,tupwr-disable;
		coresight-name = "coresight-etm3";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				etm3_out_funnel_apss0: endpoint {
					remote-endpoint =
					<&funnel_apss0_in_etm3>;
				};
			};
		};
	};

	tpdm_actpm: tpd@9830000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x9830000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-actpm";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		qcom,cmb-msr-skip;
		out-ports {
			port {
				tpdm_actpm_out_tpda_actpm: endpoint {
					remote-endpoint =
					<&tpda_actpm_in_tpdm_actpm>;
				};
			};
		};
	};

	tpdm_llm_silver: tpdm@98a0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x98a0000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-llm-silver";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		qcom,cmb-msr-cnt = <12>;
		out-ports {
			port {
				tpdm_llm_silver_out_tpda_llm_silver: endpoint {
					remote-endpoint =
					<&tpda_llm_silver_in_tpdm_llm_silver>;
				};
			};
		};
	};

	tpdm_apss: tpdm@9860000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb968>;
		reg = <0x9860000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-apss";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				tpdm_apss_out_tpda_apss: endpoint {
					remote-endpoint =
					<&tpda_apss_in_tpdm_apss>;
				};
			};
		};
	};

	funnel_apss0: funnel@9800000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;
		reg = <0x9800000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-apss0";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		out-ports {
			port {
				funnel_apss0_out_funnel_in1: endpoint {
					remote-endpoint =
					<&funnel_in1_in_funnel_apss0>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_apss0_in_etm0: endpoint {
					remote-endpoint =
					<&etm0_out_funnel_apss0>;
				};
			};

			port@1 {
				reg = <1>;
				funnel_apss0_in_etm1: endpoint {
					remote-endpoint =
					<&etm1_out_funnel_apss0>;
				};
			};

			port@2 {
				reg = <2>;
				funnel_apss0_in_etm2: endpoint {
					remote-endpoint =
					<&etm2_out_funnel_apss0>;
				};
			};

			port@3 {
				reg = <3>;
				funnel_apss0_in_etm3: endpoint {
					remote-endpoint =
					<&etm3_out_funnel_apss0>;
				};
			};

			port@4 {
				reg = <4>;
				funnel_apss0_in_tpda_actpm: endpoint {
					remote-endpoint =
					<&tpda_actpm_out_funnel_apss0>;
				};
			};

			port@5 {
				reg = <5>;
				funnel_apss0_in_tpda_llm_silver: endpoint {
					remote-endpoint =
					<&tpda_llm_silver_out_funnel_apss0>;
				};
			};

			port@6 {
				reg = <6>;
				funnel_apss0_in_tpda_apss: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpda_apss_out_funnel_apss0>;
				};
			};
		};
	};

	tpda_actpm: tpda@9832000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb969>;
		reg = <0x9832000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-actpm";

		qcom,tpda-atid = <77>;
		qcom,cmb-elem-size = <0 32>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		out-ports {
			port {
				tpda_actpm_out_funnel_apss0: endpoint {
					remote-endpoint =
					<&funnel_apss0_in_tpda_actpm>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				tpda_actpm_in_tpdm_actpm: endpoint {
					remote-endpoint =
					<&tpdm_actpm_out_tpda_actpm>;
				};
			};
		};
	};

	tpda_apss: tpda@9862000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb969>;
		reg = <0x9862000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-apss";

		qcom,tpda-atid = <66>;
		qcom,dsb-elem-size = <0 32>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		out-ports {
			port {
				tpda_apss_out_funnel_apss0: endpoint {
					remote-endpoint =
					<&funnel_apss0_in_tpda_apss>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				tpda_apss_in_tpdm_apss: endpoint {
					remote-endpoint =
					<&tpdm_apss_out_tpda_apss>;
				};
			};
		};
	};


	tpda_llm_silver: tpda@98c0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb969>;
		reg = <0x98c0000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-llm-silver";

		qcom,tpda-atid = <72>;
		qcom,cmb-elem-size = <0 32>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		out-ports {
			port {
				tpda_llm_silver_out_funnel_apss0: endpoint {
					remote-endpoint =
					<&funnel_apss0_in_tpda_llm_silver>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				tpda_llm_silver_in_tpdm_llm_silver: endpoint {
					remote-endpoint =
					<&tpdm_llm_silver_out_tpda_llm_silver>;
				};
			};
		};
	};

	tpda_mapss: tpda@8a04000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb969>;
		reg = <0x8a04000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-mapss";

		qcom,tpda-atid = <76>;
		qcom,cmb-elem-size = <0 32>;
		qcom,dsb-elem-size = <0 32>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		out-ports {
			port {
				tpda_mapss_out_funnel_in1: endpoint {
					remote-endpoint =
					<&funnel_in1_in_tpda_mapss>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				tpda_mapss_in_tpdm_mapss: endpoint {
					remote-endpoint =
					<&tpdm_mapss_out_tpda_mapss>;
				};
			};

		};
	};


	funnel_gpu: funnel@8944000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;
		reg = <0x8944000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-gpu";
		status = "disabled";
		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		out-ports {
			port {
				funnel_gpu_out_tpda1: endpoint {
					remote-endpoint =
					<&tpda1_in_funnel_gpu>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				funnel_gpu_in_tpdm_gpu: endpoint {
					remote-endpoint =
					<&tpdm_gpu_out_funnel_gpu>;
				};
			};

		};
	};

	tpda: tpda@8004000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb969>;
		reg = <0x8004000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda";

		qcom,tpda-atid = <65>;
		qcom,dsb-elem-size = <0 32>,
						<1 32>,
						<16 32>,
						<17 32>;

		qcom,cmb-elem-size = <6 32>,
						<7 32>,
						<12 32>,
						<14 32>,
						<15 32>,
						<18 32>,
						<19 32>,
						<20 32>,
						<21 32>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		out-ports {
			port {
				tpda_out_funnel_qatb: endpoint {
					remote-endpoint =
					<&funnel_qatb_in_tpda>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				tpda0_in_tpdm_dl_ct: endpoint {
					remote-endpoint =
					<&tpdm_dl_ct_out_tpda0>;
				};
			};

			port@1 {
				reg = <1>;
				tpda1_in_funnel_gpu: endpoint {
					remote-endpoint =
					<&funnel_gpu_out_tpda1>;
				};
			};

			port@6 {
				reg = <6>;
				tpda6_in_funnel_ddr: endpoint {
					remote-endpoint =
					<&funnel_ddr_out_tpda6>;
				};
			};

			port@7 {
				reg = <7>;
				tpda7_in_funnel_ddr: endpoint {
					remote-endpoint =
					<&funnel_ddr_out_tpda7>;
				};
			};

			port@12 {
				reg = <12>;
				tpda12_in_tpdm_dcc: endpoint {
					remote-endpoint =
					<&tpdm_dcc_out_tpda12>;
				};
			};

			port@14 {
				reg = <14>;
				tpda14_in_tpdm_prng: endpoint {
					remote-endpoint =
					<&tpdm_prng_out_tpda14>;
				};
			};

			port@15 {
				reg = <15>;
				tpda15_in_tpdm_vsense: endpoint {
					remote-endpoint =
					<&tpdm_vsense_out_tpda15>;
				};
			};

			port@16 {
				reg = <16>;
				tpda16_in_tpdm_qm: endpoint {
					remote-endpoint =
					<&tpdm_qm_out_tpda16>;
				};
			};

			port@17 {
				reg = <17>;
				tpda17_in_tpdm_west: endpoint {
					remote-endpoint =
					<&tpdm_west_out_tpda17>;
				};
			};

			port@18 {
				reg = <18>;
				tpda18_in_tpdm_spdm: endpoint {
					remote-endpoint =
					<&tpdm_spdm_out_tpda18>;
				};
			};

			port@19 {
				reg = <19>;
				tpda19_in_tpdm_sdcc1: endpoint {
					remote-endpoint =
					<&tpdm_sdcc1_out_tpda19>;
				};
			};

			port@20 {
				reg = <20>;
				tpda20_in_tpdm_sdcc2: endpoint {
					remote-endpoint =
					<&tpdm_sdcc2_out_tpda20>;
				};
			};

			port@21 {
				reg = <21>;
				tpda21_in_tpdm_pimem: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpdm_pimem_out_tpda21>;
				};
			};
		};
	};

	funnel_qatb: funnel@8005000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;
		reg = <0x8005000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-qatb";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		out-ports {
			port {
				funnel_qatb_out_funnel_in0: endpoint {
					remote-endpoint =
					<&funnel_in0_in_funnel_qatb>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				funnel_qatb_in_tpda: endpoint {
					remote-endpoint =
					<&tpda_out_funnel_qatb>;
				};
			};

			port@5 {
				reg = <5>;
				funnel_qatb_in_funnel_lpass: endpoint {
					remote-endpoint =
					<&funnel_lpass_out_funnel_qatb>;
				};
			};
		};
	};

	funnel_in0: funnel@8041000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;
		reg = <0x8041000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-in0";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		out-ports {
			port {
				funnel_in0_out_funnel_merg: endpoint {
					remote-endpoint =
					<&funnel_merg_in_funnel_in0>;
				};
			};
		};


		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@5 {
				reg = <5>;
				funnel_in0_in_snoc: endpoint {
					remote-endpoint =
					<&snoc_out_funnel_in0>;
				};
			};

			port@6 {
				reg = <6>;
				funnel_in0_in_funnel_qatb: endpoint {
					remote-endpoint =
					<&funnel_qatb_out_funnel_in0>;
				};
			};

			port@7 {
				reg = <7>;
				funnel_in0_in_stm: endpoint {
					remote-endpoint =
					<&stm_out_funnel_in0>;
				};
			};

		};
	};

	funnel_in1: funnel@8042000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;
		reg = <0x8042000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-in1";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		out-ports {
			port {
				funnel_in1_out_funnel_merg: endpoint {
					remote-endpoint =
					<&funnel_merg_in_funnel_in1>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@1 {
				reg = <1>;
				funnel_in1_in_tpda_mapss: endpoint {
					remote-endpoint =
					<&tpda_mapss_out_funnel_in1>;
				};
			};

			port@2 {
				reg = <2>;
				funnel_in1_in_modem_rxfe: endpoint {
					remote-endpoint =
					<&modem_rxfe_out_funnel_in1>;
				};
			};

			port@3 {
				reg = <3>;
				funnel_in1_in_funnel_wcss: endpoint {
					remote-endpoint =
					<&funnel_wcss_out_funnel_in1>;
				};
			};

			port@4 {
				reg = <4>;
				funnel_in1_in_modem_etm0: endpoint {
					remote-endpoint =
					<&modem_etm0_out_funnel_in1>;
				};
			};

			port@6 {
				reg = <6>;
				funnel_in1_in_funnel_apss0: endpoint {
					remote-endpoint =
					<&funnel_apss0_out_funnel_in1>;
				};
			};

		};
	};

	funnel_lpass: funnel@8a24000 {
		compatible = "arm,coresight-static-funnel";
		coresight-name = "coresight-funnel-lpass";

		out-ports {
			port {
				funnel_lpass_out_funnel_qatb: endpoint {
					remote-endpoint =
					<&funnel_qatb_in_funnel_lpass>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_lpass_in_audio_etm0: endpoint {
					remote-endpoint =
					<&audio_etm0_out_funnel_lpass>;
				};
			};

			port@5 {
				reg = <5>;
				funnel_lpass_in_tpdm_lpass: endpoint {
					remote-endpoint =
					<&tpdm_lpass_out_funnel_lpass>;
				};
			};
		};
	};

	funnel_ddr: funnel@8a57000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;
		reg = <0x08a57000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-ddr";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
		status = "disabled";
		out-ports {
			port@0 {
				reg = <0>;
				funnel_ddr_out_tpda6: endpoint {
					remote-endpoint =
					<&tpda6_in_funnel_ddr>;
					source = <&tpdm_ddr0>;
				};
			};

			port@1 {
				reg = <1>;
				funnel_ddr_out_tpda7: endpoint {
					remote-endpoint =
					<&tpda7_in_funnel_ddr>;
					source = <&tpdm_ddr1>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@ {
				reg = <0>;
				funnel_ddr_in_tpdm_ddr0: endpoint {
					remote-endpoint =
					<&tpdm_ddr0_out_funnel_ddr>;
				};
			};

			port@1 {
				reg = <1>;
				funnel_ddr_in_tpdm_ddr1: endpoint {
					remote-endpoint =
					<&tpdm_ddr1_out_funnel_ddr>;
				};
			};

		};
	};

	funnel_merg: funnel@8045000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb908>;
		reg = <0x8045000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-merg";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		out-ports {
			port {
				funnel_merg_out_tmc_etf: endpoint {
					remote-endpoint =
					<&tmc_etf_in_funnel_merg>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				funnel_merg_in_funnel_in0: endpoint {
					remote-endpoint =
					<&funnel_in0_out_funnel_merg>;
				};
			};

			port@1 {
				reg = <1>;
				funnel_merg_in_funnel_in1: endpoint {
					remote-endpoint =
					<&funnel_in1_out_funnel_merg>;
				};
			};

		};
	};

	tmc_etf: tmc@8047000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb961>;
		reg = <0x8047000 0x1000>;
		reg-names = "tmc-base";

		coresight-name = "coresight-tmc-etf";

		coresight-ctis = <&cti0 &cti6>;
		cti-flush-trig-num = <1>;
		cti-reset-trig-num = <5>;


		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		out-ports {
			port {
				tmc_etf_out_replicator_qdss: endpoint {
					remote-endpoint =
					<&replicator_qdss_in_tmc_etf>;
				};
			};
		};

		in-ports {
			port {
				tmc_etf_in_funnel_merg: endpoint {
					remote-endpoint =
					<&funnel_merg_out_tmc_etf>;
				};
			};
		};
	};

	replicator_qdss: replicator@8046000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb909>;
		reg = <0x8046000 0x1000>;
		reg-names = "replicator-base";

		coresight-name = "coresight-replicator-qdss";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		in-ports {
			port {
				replicator_qdss_in_tmc_etf: endpoint {
					remote-endpoint =
					<&tmc_etf_out_replicator_qdss>;
				};
			};
		};

		out-ports {
			port {
				replicator_qdss_out_tmc_etr: endpoint {
					remote-endpoint =
					<&tmc_etr_in_replicator_qdss>;
				};
			};
		};
	};

	tmc_etr: tmc@8048000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb961>;
		reg = <0x8048000 0x1000>,
			<0x8064000 0x15000>;
		reg-names = "tmc-base","bam-base";

		coresight-name = "coresight-tmc-etr";

		iommus = <&apps_smmu 0x0180 0>,
			<&apps_smmu 0x0160 0>;

		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		arm,buffer-size = <0x400000>;
		arm,scatter-gather;

		coresight-ctis = <&cti0 &cti6>;
		cti-flush-trig-num = <3>;
		cti-reset-trig-num = <5>;

		coresight-csr = <&csr>;

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		interrupts = <GIC_SPI 429 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "byte-cntr-irq";
		qcom,sw-usb;
		qcom,iommu-dma = "bypass";
		qcom,iommu-dma-addr-pool = <0x0 0xffc00000>;

		in-ports {
			port {
				tmc_etr_in_replicator_qdss: endpoint {
					remote-endpoint =
					<&replicator_qdss_out_tmc_etr>;
				};
			};
		};
	};

	cti_cortex_m3: cti@8b30000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8b30000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cortex_m3";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_apss_cti0: cti@98e0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x98e0000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-apss-cti0";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_apss_cti1: cti@98f0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x98f0000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-apss-cti1";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_wcss_cti0: cti@89a4000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x89a4000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-wcss-cti0";

		status = "disabled";
		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_wcss_cti1: cti@89a5000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x89a5000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-wcss-cti1";

		status = "disabled";
		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_wcss_cti2: cti@89a6000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x89a6000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-wcss-cti2";

		status = "disabled";
		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_lpass_lpi: cti@8a21000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8a21000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-lpass-lpi";

		status = "disabled";
		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_lpass_q6: cti@8a2b000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8a2b000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-lpass-q6";

		status = "disabled";
		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_mss_q6: cti@8833000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8833000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-mss-q6";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_isdb_gpu: cti@8941000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8941000 0x1000>;
		reg-names = "cti-base";
		coresight-name = "coresight-cti-isdb-gpu";

		status = "disabled";
		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_mapss: cti@8a02000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8a02000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-mapss";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_dlct_cti0: cti@8b59000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8b59000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-dlct-cti0";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_dlct_cti1: cti@8b5a000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8b5a000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-dlct-cti1";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_dlct_cti2: cti@8b5b000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8b5b000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-dlct-cti2";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_dlct_cti3: cti@8b5c000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8b5c000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-dlct-cti3";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti0: cti@8010000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8010000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti0";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti1: cti@8011000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8011000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti1";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti2: cti@8012000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8012000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti2";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

		//qcom,cti-gpio-trigout = <0>;
		//pinctrl-names = "cti-trigout-pctrl";
		//pinctrl-0 = <&trigout_a>;

	};

	cti3: cti@8013000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8013000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti3";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti4: cti@8014000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8014000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti4";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti5: cti@8015000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8015000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti5";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti6: cti@8016000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8016000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti6";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti7: cti@8017000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8017000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti7";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti8: cti@8018000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8018000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti8";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti9: cti@8019000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x8019000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti9";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti10: cti@801a000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x801a000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti10";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti11: cti@801b000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x801b000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti11";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti12: cti@801c000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x801c000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti12";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti13: cti@801d000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x801d000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti13";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti14: cti@801e000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x801e000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti14";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti15: cti@801f000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb966>;
		reg = <0x801f000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti15";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";
	};
};

