From 7116f4d7b5904690dab0547bc619981ca79129f4 Mon Sep 17 00:00:00 2001 From: Shashikala Katthi Date: Tue, 15 Feb 2022 16:38:31 +0530 Subject: [PATCH] ARM: dts: msm: Add support for both primary and secondary ports on SA8155 On SA8155 the primary USB port is HS capable and secondary USB port is SS capable. Add support for primary USB controller and HSPHY, secondary USB controller and HSPHY, SSPHY for the same. Change-Id: I62e9b10d6a938b72ecc66221a1b2dfa9d34c3fb5 --- qcom/sm8150-usb.dtsi | 317 +++++++++++++++++++++++++++++++++++++++++++ qcom/sm8150.dtsi | 1 + 2 files changed, 318 insertions(+) create mode 100644 qcom/sm8150-usb.dtsi diff --git a/qcom/sm8150-usb.dtsi b/qcom/sm8150-usb.dtsi new file mode 100644 index 00000000..a07e028a --- /dev/null +++ b/qcom/sm8150-usb.dtsi @@ -0,0 +1,317 @@ +#include +#include + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 9 IRQ_TYPE_EDGE_RISING>, + <&pdc 8 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "pwr_event_irq","dp_hs_phy_irq", + "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + /* + * GCC_USB3_SEC_CLKREF_CLK provides ref_clk for both + * USB instances. Hence GCC_USB3_PRIM_CLKREF_CLK is not + * used here. + */ + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,ignore-wakeup-src-in-hostmode; + + interconnect-names = "usb-ddr", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xcd00>; + iommus = <&apps_smmu 0x140 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,usb2-gadget-lpm-disable; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + usb-role-switch; + }; + }; + + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@88e2000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e2000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&L5A>; + vdda18-supply = <&L12A>; + vdda33-supply = <&L2A>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; + qcom,rcal-mask = <0x1e00000>; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* Secondary USB port related controller */ + usb1: ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a800000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 11 IRQ_TYPE_EDGE_RISING>, + <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "pwr_event_irq","dp_hs_phy_irq", + "ss_phy_irq","dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + qcom,default-mode-host; + qcom,ignore-wakeup-src-in-hostmode; + + USB3_GDSC-supply = <&usb30_sec_gdsc>; + clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&gcc GCC_USB30_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + + interconnect-names = "usb-ddr", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0x0a800000 0xd941>; + iommus = <&apps_smmu 0x160 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + interrupts = ; + usb-phy = <&usb2_phy1>, <&usb_qmp_phy>; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,ssp-u3-u0-quirk; + snps,is-utmi-l1-suspend; + snps,usb2-gadget-lpm-disable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,force-gen1; + tx-fifo-resize; + maximum-speed = "super-speed"; + dr_mode = "otg"; + usb-role-switch; + }; + }; + + /* Secondary USB port related High Speed PHY */ + usb2_phy1: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&L5A>; + vdda18-supply = <&L12A>; + vdda33-supply = <&L2A>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70 + 0x01 0xb0>; + qcom,rcal-mask = <0x1e00000>; + pinctrl-names = "default"; + pinctrl-0 = <&usb2phy_ac_en2_default>; + }; + + /* Secondary USB port related QMP PHY */ + usb_qmp_phy: ssphy@88eb000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88eb000 0x1000>, + <0x088eb88c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&L5A>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L8C>; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB3PHY_PHY_SEC_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + }; +}; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 607926a1..43d6cb35 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1528,6 +1528,7 @@ #include "sm8150-gdsc.dtsi" #include "msm-arm-smmu-sm8150.dtsi" #include "sm8150-smp2p.dtsi" +#include "sm8150-usb.dtsi" &emac_gdsc { status = "ok";