diff --git a/qcom/Makefile b/qcom/Makefile
index 05242f35..17d0fefd 100644
--- a/qcom/Makefile
+++ b/qcom/Makefile
@@ -1,4 +1,41 @@
 
+# add-overlay defines the target with following naming convention:
+# <base>-<board>-dtbs = base.dtb board.dtbo
+#
+# Combined dtb target is also generated using the fdt_overlay tool.
+# dtb-y += <base>-<board>.dtb
+
+add-overlays = $(foreach o,$1,$(foreach b,$2,$(eval $(basename $b)-$(basename $o)-dtbs = $b $o) $(basename $b)-$(basename $o).dtb))
+
+
+WAIPIO_BASE_DTB += waipio.dtb waipio-v2.dtb
+WAIPIO_APQ_BASE_DTB += waipiop.dtb waipiop-v2.dtb
+
+WAIPIO_BOARDS += \
+		 waipio-rumi-overlay.dtbo \
+		 waipio-mtp-pm8008-overlay.dtbo \
+		 waipio-cdp-pm8008-overlay.dtbo \
+		 waipio-qrd-pm8008-overlay.dtbo \
+		 waipio-atp-pm8008-overlay.dtbo \
+		 waipio-mtp-pm8010-overlay.dtbo \
+		 waipio-cdp-pm8010-overlay.dtbo \
+		 waipio-qrd-pm8010-overlay.dtbo \
+		 waipio-qrd-pm8010-2s-overlay.dtbo \
+		 waipio-atp-pm8010-overlay.dtbo
+
+NOAPQ_WAIPIO_BOARDS += \
+		       waipiop-hdk-pm8010-overlay.dtbo \
+		       waipio-lemur-mtp-pm8008-overlay.dtbo \
+		       waipio-lemur-mtp-pm8010-overlay.dtbo \
+		       waipio-lemur-cdp-pm8008-overlay.dtbo \
+		       waipio-lemur-cdp-pm8010-overlay.dtbo \
+		       waipio-kiwi-mtp-pm8008-overlay.dtbo \
+		       waipio-kiwi-mtp-pm8010-overlay.dtbo
+
+dtb-$(CONFIG_ARCH_WAIPIO) += \
+	$(call add-overlays, $(WAIPIO_BOARDS) $(NOAPQ_WAIPIO_BOARDS),$(WAIPIO_BASE_DTB))\
+	$(call add-overlays, $(WAIPIO_BOARDS) $(APQ_WAIPIO_BOARDS),$(WAIPIO_APQ_BASE_DTB))
+
 dtb-$(CONFIG_ARCH_KALAMA) += kalama-rumi.dtb \
 	     kalama-mtp.dtb \
 	     kalama-cdp.dtb \
diff --git a/qcom/ipcc-test.dtsi b/qcom/ipcc-test.dtsi
new file mode 100644
index 00000000..bd89d9e9
--- /dev/null
+++ b/qcom/ipcc-test.dtsi
@@ -0,0 +1,31 @@
+#include <dt-bindings/soc/qcom,ipcc.h>
+
+&soc {
+	ipcc_self_ping_apss: ipcc-self-ping-apss {
+		compatible = "qcom,ipcc-self-ping";
+		interrupts-extended = <&ipcc_mproc IPCC_CLIENT_APSS
+			IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_LEVEL_HIGH>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_APSS IPCC_MPROC_SIGNAL_SMP2P>;
+	};
+
+	ipcc_self_ping_cdsp: ipcc-self-ping-cdsp {
+		compatible = "qcom,ipcc-self-ping";
+		interrupts-extended = <&ipcc_mproc IPCC_CLIENT_CDSP
+				IPCC_MPROC_SIGNAL_PING IRQ_TYPE_LEVEL_HIGH>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_PING>;
+	};
+
+	ipcc_self_ping_adsp: ipcc-self-ping-adsp {
+		compatible = "qcom,ipcc-self-ping";
+		interrupts-extended = <&ipcc_mproc IPCC_CLIENT_LPASS
+				IPCC_MPROC_SIGNAL_PING IRQ_TYPE_LEVEL_HIGH>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_PING>;
+	};
+
+	ipcc_self_ping_slpi: ipcc-self-ping-slpi {
+		compatible = "qcom,ipcc-self-ping";
+		interrupts-extended = <&ipcc_mproc IPCC_CLIENT_SLPI
+				IPCC_MPROC_SIGNAL_PING IRQ_TYPE_LEVEL_HIGH>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_PING>;
+	};
+};
diff --git a/qcom/msm-arm-smmu-waipio-vm.dtsi b/qcom/msm-arm-smmu-waipio-vm.dtsi
new file mode 100755
index 00000000..4d79e094
--- /dev/null
+++ b/qcom/msm-arm-smmu-waipio-vm.dtsi
@@ -0,0 +1,31 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	vm-config {
+		vdevices {
+			vsmmu@15000000 {
+				vdevice-type = "vsmmu-v2";
+				smmu-handle = <0x15000000>;
+				num-cbs = <0x2>;
+				num-smrs = <0x3>;
+				patch = "/soc/apps-smmu@15000000";
+			};
+		};
+	};
+};
+
+&soc {
+	apps_smmu: apps-smmu@15000000 {
+		/*
+		 * reg, #global-interrupts & interrupts  properties will
+		 * be added dynamically by bootloader.
+		 */
+		compatible = "qcom,qsmmu-v500", "qcom,virt-smmu";
+		#iommu-cells = <2>;
+		qcom,use-3-lvl-tables;
+		dma-coherent;
+		qcom,actlr =
+			<0x2803 0x0400 0x00000001>,
+			<0x2804 0x0402 0x00000001>;
+	};
+};
diff --git a/qcom/msm-arm-smmu-waipio.dtsi b/qcom/msm-arm-smmu-waipio.dtsi
new file mode 100644
index 00000000..83710386
--- /dev/null
+++ b/qcom/msm-arm-smmu-waipio.dtsi
@@ -0,0 +1,409 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+	kgsl_smmu: kgsl-smmu@3da0000 {
+		compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu";
+		reg = <0x3DA0000 0x40000>,
+			<0x3DE6000 0x20>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,skip-init;
+		qcom,use-3-lvl-tables;
+		qcom,num-context-banks-override = <0x15>;
+		qcom,num-smr-override = <0x18>;
+		#global-interrupts = <1>;
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		dma-coherent;
+
+		qcom,regulator-names = "vdd";
+		vdd-supply = <&gpu_cc_cx_gdsc>;
+
+		clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>,
+			 <&clock_gpucc GPU_CC_HUB_CX_INT_CLK>,
+			 <&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+			 <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
+			 <&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+			 <&clock_gpucc GPU_CC_AHB_CLK>;
+		clock-names =
+			"gpu_cc_cx_gmu",
+			"gpu_cc_hub_cx_int",
+			"gpu_cc_hlos1_vote_gpu_smmu",
+			"gcc_gpu_memnoc_gfx",
+			"gcc_gpu_snoc_dvm_gfx",
+			"gpu_cc_ahb";
+
+		qcom,actlr =
+			/* All CBs of GFX: +15 deep PF */
+			<0x000 0x3ff 0x32B>,
+			<0x400 0x3ff 0x32B>;
+
+		interrupts =	<GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
+
+		gfx_0_tbu: gfx_0_tbu@3de9000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x3de9000 0x1000>,
+				<0x3de6200 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x0 0x400>;
+		};
+
+		gfx_1_tbu: gfx_1_tbu@3ded000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x3ded000 0x1000>,
+				<0x3de6208 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x400 0x400>;
+		};
+	};
+
+	apps_smmu: apps-smmu@15000000 {
+		compatible = "qcom,qsmmu-v500";
+		reg = <0x15000000 0x100000>,
+			<0x151ce000 0x20>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,skip-init;
+		qcom,use-3-lvl-tables;
+		qcom,num-context-banks-override = <0x4e>;
+		qcom,num-smr-override = <0x78>;
+		qcom,handoff-smrs = <3>;
+		#global-interrupts = <1>;
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		dma-coherent;
+		interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
+
+		/* Autogenerated */
+		qcom,actlr =
+			<0x0001 0x24e0 0x00000001>,
+			<0x0001 0x0ce0 0x00000001>,
+			<0x0001 0x1420 0x00000303>,
+			<0x0002 0x3420 0x00000303>,
+			<0x0004 0x3560 0x00000303>,
+			<0x0005 0x3420 0x00000303>,
+			<0x0006 0x3560 0x00000303>,
+			<0x0007 0x3560 0x00000303>,
+			<0x0008 0x3560 0x00000303>,
+			<0x0009 0x3560 0x00000303>,
+			<0x000c 0x3560 0x00000303>,
+			<0x000d 0x3560 0x00000303>,
+			<0x000e 0x3560 0x00000303>,
+			<0x000f 0x3560 0x00000303>,
+			<0x0121 0x2c80 0x00000001>,
+			<0x0165 0x2400 0x00000303>,
+			<0x0800 0x0460 0x00000001>,
+			<0x0880 0x0400 0x00000001>,
+			<0x1000 0x0400 0x00000303>,
+			<0x1003 0x2520 0x00000303>,
+			<0x100a 0x0400 0x00000303>,
+			<0x100b 0x0420 0x00000303>,
+			<0x2000 0x0420 0x00000001>,
+			<0x2002 0x0500 0x00000001>,
+			<0x2003 0x0560 0x00000303>,
+			<0x2040 0x0420 0x00000001>,
+			<0x2042 0x1520 0x00000303>,
+			<0x206b 0x1500 0x00000303>,
+			<0x2080 0x0400 0x00000001>,
+			<0x20a0 0x0400 0x00000001>,
+			<0x20c0 0x0400 0x00000001>,
+			<0x20e0 0x0400 0x00000001>,
+			<0x2100 0x0420 0x00000001>,
+			<0x2101 0x0400 0x00000001>,
+			<0x2161 0x0400 0x00000303>,
+			<0x2180 0x0400 0x00000103>,
+			<0x2181 0x0404 0x00000103>,
+			<0x2182 0x0400 0x00000103>,
+			<0x2183 0x0400 0x00000103>,
+			<0x2184 0x0400 0x00000103>,
+			<0x2187 0x0400 0x00000103>,
+			<0x2800 0x0402 0x00000001>,
+			<0x2801 0x0000 0x00000001>,
+			<0x2803 0x0000 0x00000001>,
+			<0x2806 0x0400 0x00000001>,
+			<0x2c01 0x0000 0x00000001>,
+			<0x2c03 0x0000 0x00000001>;
+
+		anoc_1_tbu: anoc_1_tbu@151d1000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151d1000 0x1000>,
+				<0x151ce200 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x0 0x400>;
+			qcom,micro-idle;
+		};
+
+		anoc_2_tbu: anoc_2_tbu@151d5000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151d5000 0x1000>,
+				<0x151ce208  0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x400 0x400>;
+			qcom,micro-idle;
+		};
+
+		cam_0_tbu: cam_0_tbu@151d9000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151d9000 0x1000>,
+				<0x151ce210 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x800 0x400>;
+			qcom,micro-idle;
+		};
+
+		cam_1_tbu: cam_1_tbu@151dd000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151dd000 0x1000>,
+				<0x151ce218 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0xc00 0x400>;
+			qcom,micro-idle;
+		};
+
+		compute_1_tbu: compute_1_tbu@151e1000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151e1000 0x1000>,
+				<0x151ce220 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1000 0x400>;
+			qcom,micro-idle;
+		};
+
+		compute_0_tbu: compute_0_tbu@151e5000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151e5000 0x1000>,
+				<0x151ce228 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1400 0x400>;
+			qcom,micro-idle;
+		};
+
+		lpass_tbu: lpass_tbu@151e9000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151e9000 0x1000>,
+				<0x151ce230 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1800 0x400>;
+			qcom,micro-idle;
+		};
+
+		pcie_tbu: pcie_tbu@151ed000 {
+			status = "disabled";
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151ed000 0x1000>,
+				<0x151ce238 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1c00 0x400>;
+			qcom,micro-idle;
+		};
+
+		sf_0_tbu: sf_0_tbu@151f1000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151f1000 0x1000>,
+				<0x151ce240 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x2000 0x400>;
+			qcom,micro-idle;
+		};
+
+		sf_1_tbu: sf_1_tbu@151f5000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151f5000 0x1000>,
+				<0x151ce248 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x2400 0x400>;
+			qcom,micro-idle;
+		};
+
+		mdp_0_tbu: mdp_0_tbu@151f9000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151f9000 0x1000>,
+				<0x151ce250 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x2800 0x400>;
+			qcom,micro-idle;
+		};
+
+		mdp_1_tbu: mdp_1_tbu@151fd000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151fd000 0x1000>,
+				<0x151ce258 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x2c00 0x400>;
+			qcom,micro-idle;
+		};
+	};
+
+	dma_dev@0x0 {
+		compatible = "qcom,iommu-dma";
+		memory-region = <&system_cma>;
+	};
+
+	iommu_test_device {
+		compatible = "qcom,iommu-debug-test";
+
+		usecase0_apps {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x7e0 0>;
+		};
+
+		usecase1_apps_fastmap {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x7e0 0>;
+			qcom,iommu-dma = "fastmap";
+		};
+
+		usecase2_apps_atomic {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x7e0 0>;
+			qcom,iommu-dma = "atomic";
+		};
+
+		usecase3_apps_dma {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x7e1 0>;
+			dma-coherent;
+		};
+
+		usecase4_apps_secure {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x7e0 0>;
+			qcom,iommu-dma = "atomic";
+			qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
+		};
+
+		usecase5_kgsl {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&kgsl_smmu 0x7 0x400>;
+		};
+
+		usecase6_kgsl_dma {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&kgsl_smmu 0x407 0x400>;
+			dma-coherent;
+		};
+	};
+};
diff --git a/qcom/msm-rdbg.dtsi b/qcom/msm-rdbg.dtsi
new file mode 100644
index 00000000..bb2adf8d
--- /dev/null
+++ b/qcom/msm-rdbg.dtsi
@@ -0,0 +1,26 @@
+&soc {
+  /* smp2p information */
+	qcom,smp2p_interrupt_rdbg_2_out {
+		compatible = "qcom,smp2p-interrupt-rdbg-2-out";
+		qcom,smem-states = <&smp2p_rdbg2_out 0>;
+		qcom,smem-state-names = "rdbg-smp2p-out";
+	};
+
+	qcom,smp2p_interrupt_rdbg_2_in {
+		compatible = "qcom,smp2p-interrupt-rdbg-2-in";
+		interrupts-extended = <&smp2p_rdbg2_in 0 0>;
+		interrupt-names = "rdbg-smp2p-in";
+	};
+
+	qcom,smp2p_interrupt_rdbg_5_out {
+		compatible = "qcom,smp2p-interrupt-rdbg-5-out";
+		qcom,smem-states = <&smp2p_rdbg5_out 0>;
+		qcom,smem-state-names = "rdbg-smp2p-out";
+	};
+
+	qcom,smp2p_interrupt_rdbg_5_in {
+		compatible = "qcom,smp2p-interrupt-rdbg-5-in";
+		interrupts-extended = <&smp2p_rdbg5_in 0 0>;
+		interrupt-names = "rdbg-smp2p-in";
+	};
+};
diff --git a/qcom/pm8350.dtsi b/qcom/pm8350.dtsi
new file mode 100644
index 00000000..f833cdfc
--- /dev/null
+++ b/qcom/pm8350.dtsi
@@ -0,0 +1,61 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pm8350@1 {
+		compatible = "qcom,spmi-pmic";
+		reg = <1 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8350_tz: qcom,temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8350_gpios: pinctrl@8800 {
+			compatible = "qcom,pm8350-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
+
+&thermal_zones {
+	pm8350_temp_alarm: pm8350_tz {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8350_tz>;
+
+		trips {
+			pm8350_trip0: trip0 {
+				temperature = <95000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			pm8350_trip1: trip1 {
+				temperature = <115000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+
+			pm8350_trip2: trip2 {
+				temperature = <145000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+		};
+	};
+};
diff --git a/qcom/pm8350b.dtsi b/qcom/pm8350b.dtsi
new file mode 100644
index 00000000..455826a1
--- /dev/null
+++ b/qcom/pm8350b.dtsi
@@ -0,0 +1,385 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/input/qcom,hv-haptics.h>
+
+&spmi_bus {
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pm8350b@3 {
+		compatible = "qcom,spmi-pmic";
+		reg = <3 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8350b_tz: qcom,temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8350b_pbs2: qcom,pbs@1900 {
+			compatible = "qcom,qpnp-pbs";
+			reg = <0x1900>;
+		};
+
+		pm8350b_gpios: pinctrl@8800 {
+			compatible = "qcom,pm8350b-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pm8350b_bcl: bcl@4700 {
+			compatible = "qcom,bcl-v5";
+			reg = <0x4700 0x100>;
+			interrupts = <0x3 0x47 0x0 IRQ_TYPE_NONE>,
+					<0x3 0x47 0x1 IRQ_TYPE_NONE>,
+					<0x3 0x47 0x2 IRQ_TYPE_NONE>;
+			interrupt-names = "bcl-lvl0",
+						"bcl-lvl1",
+						"bcl-lvl2";
+			qcom,pmic7-threshold;
+			#thermal-sensor-cells = <1>;
+		};
+
+		bcl_soc:bcl-soc {
+			compatible = "qcom,msm-bcl-soc";
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8350b_haptics: qcom,hv-haptics@f000 {
+			compatible = "qcom,hv-haptics";
+			reg = <0xf000>, <0xf100>, <0xf200>;
+			interrupts = <0x3 0xf0 0x1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "fifo-empty";
+			qcom,vmax-mv = <3600>;
+			qcom,brake-mode = <BRAKE_CLOSE_LOOP>;
+			qcom,brake-pattern = /bits/ 8 <0xff 0x3f 0x1f>;
+			qcom,lra-period-us = <6667>;
+			qcom,drv-sig-shape = <WF_SINE>;
+			qcom,brake-sig-shape = <WF_SINE>;
+			status = "disabled";
+
+			hap_swr_slave_reg: qcom,hap-swr-slave-reg {
+				regulator-name = "hap-swr-slave-reg";
+			};
+
+			effect_0 {
+				/* CLICK */
+				qcom,effect-id = <0>;
+				qcom,wf-vmax-mv = <3600>;
+				qcom,wf-pattern-data =  <0x01f  S_PERIOD_T_LRA  0>,
+							<0x03f  S_PERIOD_T_LRA  0>,
+							<0x05f  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>,
+							<0x17f  S_PERIOD_T_LRA  0>,
+							<0x15f  S_PERIOD_T_LRA  0>,
+							<0x13f  S_PERIOD_T_LRA  0>,
+							<0x11f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <6667>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-pattern-preload;
+				qcom,wf-auto-res-disable;
+			};
+
+			effect_1 {
+				/* DOUBLE_CLICK */
+				qcom,effect-id = <1>;
+				qcom,wf-vmax-mv = <3600>;
+				qcom,wf-pattern-data =  <0x01f  S_PERIOD_T_LRA  0>,
+							<0x03f  S_PERIOD_T_LRA  0>,
+							<0x05f  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>,
+							<0x17f  S_PERIOD_T_LRA  0>,
+							<0x15f  S_PERIOD_T_LRA  0>,
+							<0x13f  S_PERIOD_T_LRA  0>,
+							<0x11f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <6667>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			effect_2 {
+				/* TICK */
+				qcom,effect-id = <2>;
+				qcom,wf-vmax-mv = <3600>;
+				qcom,wf-pattern-data =  <0x01f  S_PERIOD_T_LRA  0>,
+							<0x03f  S_PERIOD_T_LRA  0>,
+							<0x05f  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>,
+							<0x17f  S_PERIOD_T_LRA  0>,
+							<0x15f  S_PERIOD_T_LRA  0>,
+							<0x13f  S_PERIOD_T_LRA  0>,
+							<0x11f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <6667>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			effect_3 {
+				/* THUD */
+				qcom,effect-id = <3>;
+				qcom,wf-vmax-mv = <3600>;
+				qcom,wf-pattern-data =  <0x01f  S_PERIOD_T_LRA  0>,
+							<0x03f  S_PERIOD_T_LRA  0>,
+							<0x05f  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>,
+							<0x17f  S_PERIOD_T_LRA  0>,
+							<0x15f  S_PERIOD_T_LRA  0>,
+							<0x13f  S_PERIOD_T_LRA  0>,
+							<0x11f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <6667>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			effect_4 {
+				/* POP */
+				qcom,effect-id = <4>;
+				qcom,wf-vmax-mv = <3600>;
+				qcom,wf-pattern-data =  <0x01f  S_PERIOD_T_LRA  0>,
+							<0x03f  S_PERIOD_T_LRA  0>,
+							<0x05f  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>,
+							<0x17f  S_PERIOD_T_LRA  0>,
+							<0x15f  S_PERIOD_T_LRA  0>,
+							<0x13f  S_PERIOD_T_LRA  0>,
+							<0x11f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <6667>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			effect_5 {
+				/* HEAVY CLICK */
+				qcom,effect-id = <5>;
+				qcom,wf-vmax-mv = <3600>;
+				qcom,wf-pattern-data =  <0x01f  S_PERIOD_T_LRA  0>,
+							<0x03f  S_PERIOD_T_LRA  0>,
+							<0x05f  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>,
+							<0x17f  S_PERIOD_T_LRA  0>,
+							<0x15f  S_PERIOD_T_LRA  0>,
+							<0x13f  S_PERIOD_T_LRA  0>,
+							<0x11f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <6667>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+		};
+
+		pm8350b_amoled: qcom,amoled {
+			compatible = "qcom,qpnp-amoled-regulator";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			oledb_vreg: oledb@fa00 {
+				reg = <0xfa00>;
+				reg-names = "oledb_base";
+				regulator-name = "oledb";
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <8000000>;
+				qcom,swire-control;
+			};
+
+			ab_vreg: ab@f900 {
+				reg = <0xf900>;
+				reg-names = "ab_base";
+				regulator-name = "ab";
+				regulator-min-microvolt = <4600000>;
+				regulator-max-microvolt = <5200000>;
+				qcom,swire-control;
+			};
+
+			ibb_vreg: ibb@f800 {
+				reg = <0xf800>;
+				reg-names = "ibb_base";
+				regulator-name = "ibb";
+				regulator-min-microvolt = <1400000>;
+				regulator-max-microvolt = <6600000>;
+				qcom,swire-control;
+				regulator-allow-set-load;
+			};
+		};
+
+		qcom,amoled-ecm@f900 {
+			compatible = "qcom,amoled-ecm";
+			reg = <0xf900>;
+			nvmem-names = "amoled-ecm-sdam0", "amoled-ecm-sdam1",
+				      "amoled-ecm-sdam2";
+			nvmem = <&pmk8350_sdam_13>, <&pmk8350_sdam_14>,
+				<&pmk8350_sdam_41>;
+			interrupt-names = "ecm-sdam0", "ecm-sdam1",
+					  "ecm-sdam2";
+			interrupts = <0x0 0x7c 0x1 IRQ_TYPE_EDGE_RISING>,
+				     <0x0 0x7d 0x1 IRQ_TYPE_EDGE_RISING>,
+				     <0x0 0x98 0x1 IRQ_TYPE_EDGE_RISING>;
+		};
+	};
+};
+
+&thermal_zones {
+	pm8350b_temp_alarm: pm8350b_tz {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm8350b_tz>;
+
+		trips {
+			pm8350b_trip0: trip0 {
+				temperature = <95000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			pm8350b_trip1: trip1 {
+				temperature = <115000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+
+			pm8350b_trip2: trip2 {
+				temperature = <145000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+		};
+	};
+
+	pm8350b-ibat-lvl0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm8350b_bcl 0>;
+
+		trips {
+			ibat_lvl0:ibat-lvl0 {
+				temperature = <6000>;
+				hysteresis = <200>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8350b-ibat-lvl1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm8350b_bcl 1>;
+
+		trips {
+			ibat_lvl1:ibat-lvl1 {
+				temperature = <7500>;
+				hysteresis = <200>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8350b-bcl-lvl0 {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm8350b_bcl 5>;
+
+		trips {
+			thermal-engine-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			thermal-hal-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			b_bcl_lvl0: b-bcl-lvl0 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8350b-bcl-lvl1 {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm8350b_bcl 6>;
+
+		trips {
+			thermal-engine-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			thermal-hal-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			b_bcl_lvl1: b-bcl-lvl1 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8350b-bcl-lvl2 {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-sensors = <&pm8350b_bcl 7>;
+
+		trips {
+			thermal-engine-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			thermal-hal-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			b_bcl_lvl2: b-bcl-lvl2 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+	};
+
+	socd {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-sensors = <&bcl_soc>;
+
+		trips {
+			thermal-engine-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			thermal-hal-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			socd_trip:socd-trip {
+				temperature = <90>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+		};
+	};
+};
diff --git a/qcom/pm8350c.dtsi b/qcom/pm8350c.dtsi
new file mode 100644
index 00000000..18213cc1
--- /dev/null
+++ b/qcom/pm8350c.dtsi
@@ -0,0 +1,302 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pm8350c@2 {
+		compatible = "qcom,spmi-pmic";
+		reg = <2 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8350c_tz: qcom,temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8350c_gpios: pinctrl@8800 {
+			compatible = "qcom,pm8350c-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pm8350c_pwm_1: pwms@e800 {
+			compatible = "qcom,pwm-lpg";
+			reg = <0xe800>;
+			reg-names = "lpg-base";
+			#pwm-cells = <2>;
+			qcom,num-lpg-channels = <3>;
+			nvmem = <&pmk8350_sdam_21 &pmk8350_sdam_22>;
+			nvmem-names = "lpg_chan_sdam", "lut_sdam";
+			qcom,lut-sdam-base = <0x45>;
+			qcom,lut-patterns = <0 10 20 30 40 50 60 70 80 90 100
+					     90 80 70 60 50 40 30 20 10 0>;
+			qcom,tick-duration-us = <8000>;
+
+			lpg@1 {
+				qcom,lpg-chan-id = <1>;
+				qcom,ramp-step-ms = <100>;
+				qcom,ramp-low-index = <0>;
+				qcom,ramp-high-index = <19>;
+				qcom,ramp-pattern-repeat;
+				qcom,lpg-sdam-base = <0x48>;
+			};
+
+			lpg@2 {
+				qcom,lpg-chan-id = <2>;
+				qcom,ramp-step-ms = <100>;
+				qcom,ramp-low-index = <0>;
+				qcom,ramp-high-index = <19>;
+				qcom,ramp-pattern-repeat;
+				qcom,lpg-sdam-base = <0x56>;
+			};
+
+			lpg@3 {
+				qcom,lpg-chan-id = <3>;
+				qcom,ramp-step-ms = <100>;
+				qcom,ramp-low-index = <0>;
+				qcom,ramp-high-index = <19>;
+				qcom,ramp-pattern-repeat;
+				qcom,lpg-sdam-base = <0x64>;
+			};
+		};
+
+		pm8350c_pwm_2: pwms@eb00 {
+			compatible = "qcom,pwm-lpg";
+			reg = <0xeb00>;
+			reg-names = "lpg-base";
+			#pwm-cells = <2>;
+			qcom,num-lpg-channels = <1>;
+		};
+
+		pm8350c_rgb: qcom,leds@ef00 {
+			compatible = "qcom,tri-led";
+			reg = <0xef00>;
+
+			red {
+				label = "red";
+				pwms = <&pm8350c_pwm_1 0 1000000>;
+				led-sources = <0>;
+				linux,default-trigger = "timer";
+			};
+
+			green {
+				label = "green";
+				pwms = <&pm8350c_pwm_1 1 1000000>;
+				led-sources = <1>;
+				linux,default-trigger = "timer";
+			};
+
+			blue {
+				label = "blue";
+				pwms = <&pm8350c_pwm_1 2 1000000>;
+				led-sources = <2>;
+				linux,default-trigger = "timer";
+			};
+		};
+
+		pm8350c_bcl: bcl@4700 {
+			compatible = "qcom,bcl-v5";
+			reg = <0x4700 0x100>;
+			interrupts = <0x2 0x47 0x0 IRQ_TYPE_NONE>,
+					<0x2 0x47 0x1 IRQ_TYPE_NONE>,
+					<0x2 0x47 0x2 IRQ_TYPE_NONE>;
+			interrupt-names = "bcl-lvl0",
+						"bcl-lvl1",
+						"bcl-lvl2";
+			qcom,pmic7-threshold;
+			#thermal-sensor-cells = <1>;
+		};
+
+		pm8350c_flash: qcom,flash_led@ee00 {
+			compatible = "qcom,pm8350c-flash-led";
+			reg = <0xee00>;
+			interrupts = <0x2 0xee 0x0 IRQ_TYPE_EDGE_RISING>,
+				     <0x2 0xee 0x3 IRQ_TYPE_EDGE_RISING>,
+				     <0x2 0xee 0x4 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "led-fault-irq",
+					  "all-ramp-down-done-irq",
+					  "all-ramp-up-done-irq";
+			qcom,thermal-derate-current = <200 500>;
+			qcom,hw-strobe-gpios = <&pm8350c_gpios 1 0>;
+			status = "disabled";
+
+			pm8350c_flash0: qcom,flash_0 {
+				label = "flash";
+				qcom,led-name = "led:flash_0";
+				qcom,max-current-ma = <1500>;
+				qcom,default-led-trigger = "flash0_trigger";
+				qcom,id = <0>;
+				qcom,duration-ms = <1280>;
+				qcom,ires-ua = <12500>;
+			};
+
+			pm8350c_flash1: qcom,flash_1 {
+				label = "flash";
+				qcom,led-name = "led:flash_1";
+				qcom,max-current-ma = <1500>;
+				qcom,default-led-trigger = "flash1_trigger";
+				qcom,id = <1>;
+				qcom,duration-ms = <1280>;
+				qcom,ires-ua = <12500>;
+			};
+
+			pm8350c_flash2: qcom,flash_2 {
+				label = "flash";
+				qcom,led-name = "led:flash_2";
+				qcom,max-current-ma = <1500>;
+				qcom,default-led-trigger = "flash2_trigger";
+				qcom,id = <2>;
+				qcom,duration-ms = <1280>;
+				qcom,ires-ua = <12500>;
+			};
+
+			pm8350c_flash3: qcom,flash_3 {
+				label = "flash";
+				qcom,led-name = "led:flash_3";
+				qcom,max-current-ma = <1500>;
+				qcom,default-led-trigger = "flash3_trigger";
+				qcom,id = <3>;
+				qcom,duration-ms = <1280>;
+				qcom,ires-ua = <12500>;
+			};
+
+			pm8350c_torch0: qcom,torch_0 {
+				label = "torch";
+				qcom,led-name = "led:torch_0";
+				qcom,max-current-ma = <500>;
+				qcom,default-led-trigger = "torch0_trigger";
+				qcom,id = <0>;
+				qcom,ires-ua = <12500>;
+			};
+
+			pm8350c_torch1: qcom,torch_1 {
+				label = "torch";
+				qcom,led-name = "led:torch_1";
+				qcom,max-current-ma = <500>;
+				qcom,default-led-trigger = "torch1_trigger";
+				qcom,id = <1>;
+				qcom,ires-ua = <12500>;
+			};
+
+			pm8350c_torch2: qcom,torch_2 {
+				label = "torch";
+				qcom,led-name = "led:torch_2";
+				qcom,max-current-ma = <500>;
+				qcom,default-led-trigger = "torch2_trigger";
+				qcom,id = <2>;
+				qcom,ires-ua = <12500>;
+			};
+
+			pm8350c_torch3: qcom,torch_3 {
+				label = "torch";
+				qcom,led-name = "led:torch_3";
+				qcom,max-current-ma = <500>;
+				qcom,default-led-trigger = "torch3_trigger";
+				qcom,id = <3>;
+				qcom,ires-ua = <12500>;
+			};
+
+			pm8350c_switch0: qcom,led_switch_0 {
+				label = "switch";
+				qcom,led-name = "led:switch_0";
+				qcom,default-led-trigger = "switch0_trigger";
+			};
+
+			pm8350c_switch1: qcom,led_switch_1 {
+				label = "switch";
+				qcom,led-name = "led:switch_1";
+				qcom,default-led-trigger = "switch1_trigger";
+			};
+
+			pm8350c_switch2: qcom,led_switch_2 {
+				label = "switch";
+				qcom,led-name = "led:switch_2";
+				qcom,default-led-trigger = "switch2_trigger";
+			};
+		};
+	};
+};
+
+&thermal_zones {
+	pm8350c_temp_alarm: pm8350c_tz {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8350c_tz>;
+
+		trips {
+			pm8350c_trip0: trip0 {
+				temperature = <95000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			pm8350c_trip1: trip1 {
+				temperature = <115000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+
+			pm8350c_trip2: trip2 {
+				temperature = <145000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+		};
+	};
+
+	pm8350c-bcl-lvl0 {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8350c_bcl 5>;
+
+		trips {
+			c_bcl_lvl0: c-bcl-lvl0 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8350c-bcl-lvl1 {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8350c_bcl 6>;
+
+		trips {
+			c_bcl_lvl1: c-bcl-lvl1 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8350c-bcl-lvl2 {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8350c_bcl 7>;
+
+		trips {
+			c_bcl_lvl2: c-bcl-lvl2 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+	};
+};
diff --git a/qcom/pm8450.dtsi b/qcom/pm8450.dtsi
new file mode 100644
index 00000000..3e6292f1
--- /dev/null
+++ b/qcom/pm8450.dtsi
@@ -0,0 +1,61 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pm8450@7 {
+		compatible = "qcom,spmi-pmic";
+		reg = <7 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8450_tz: qcom,temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8450_gpios: pinctrl@8800 {
+			compatible = "qcom,pm8450-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
+
+&thermal_zones {
+	pm8450_temp_alarm: pm8450_tz {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8450_tz>;
+
+		trips {
+			pm8450_trip0: trip0 {
+				temperature = <95000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			pm8450_trip1: trip1 {
+				temperature = <115000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+
+			pm8450_trip2: trip2 {
+				temperature = <145000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+		};
+	};
+};
diff --git a/qcom/pmk8350.dtsi b/qcom/pmk8350.dtsi
new file mode 100644
index 00000000..0b35d6cd
--- /dev/null
+++ b/qcom/pmk8350.dtsi
@@ -0,0 +1,253 @@
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/qcom,qpnp-power-on.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pm8350b.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pmr735b.h>
+
+&spmi_bus {
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	pmk8350: qcom,pmk8350@0 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pon_pbs@800 {
+			compatible = "qcom,qpnp-power-on";
+			reg = <0x800>;
+			qcom,system-reset;
+			qcom,store-hard-reset-reason;
+		};
+
+		pon_hlos@1300 {
+			compatible = "qcom,qpnp-power-on";
+			reg = <0x1300>;
+			interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>,
+				     <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "kpdpwr", "resin";
+
+			qcom,pon_1 {
+				qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
+				linux,code = <KEY_POWER>;
+			};
+
+			qcom,pon_2 {
+				qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
+				linux,code = <KEY_VOLUMEDOWN>;
+			};
+		};
+
+		pmk8350_vadc: vadc@3100 {
+			compatible = "qcom,spmi-adc7";
+			reg = <0x3100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "eoc-int-en-set";
+			#io-channel-cells = <1>;
+			io-channel-ranges;
+
+			/* PMK8350 Channel nodes */
+			pmk8350_ref_gnd {
+				reg = <PMK8350_ADC7_REF_GND>;
+				label = "pmk8350_ref_gnd";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pmk8350_vref_1p25 {
+				reg = <PMK8350_ADC7_1P25VREF>;
+				label = "pmk8350_vref_1p25";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pmk8350_die_temp {
+				reg = <PMK8350_ADC7_DIE_TEMP>;
+				label = "pmk8350_die_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pmk8350_xo_therm {
+				reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+				label = "pmk8350_xo_therm";
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			/* PM8350 Channel nodes */
+			pm8350_ref_gnd {
+				reg = <PM8350_ADC7_REF_GND>;
+				label = "pm8350_ref_gnd";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm8350_vref_1p25 {
+				reg = <PM8350_ADC7_1P25VREF>;
+				label = "pm8350_vref_1p25";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm8350_die_temp {
+				reg = <PM8350_ADC7_DIE_TEMP>;
+				label = "pm8350_die_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm8350_vph_pwr {
+				reg = <PM8350_ADC7_VPH_PWR>;
+				label = "pm8350_vph_pwr";
+				qcom,pre-scaling = <1 3>;
+			};
+
+			/* PM8350b Channel nodes */
+			pm8350b_ref_gnd {
+				reg = <PM8350B_ADC7_REF_GND>;
+				label = "pm8350b_ref_gnd";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm8350b_vref_1p25 {
+				reg = <PM8350B_ADC7_1P25VREF>;
+				label = "pm8350b_vref_1p25";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm8350b_die_temp {
+				reg = <PM8350B_ADC7_DIE_TEMP>;
+				label = "pm8350b_die_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm8350b_vph_pwr {
+				reg = <PM8350B_ADC7_VPH_PWR>;
+				label = "pm8350b_vph_pwr";
+				qcom,pre-scaling = <1 3>;
+			};
+
+			pm8350b_vbat_sns {
+				reg = <PM8350B_ADC7_VBAT_SNS>;
+				label = "pm8350b_vbat_sns";
+				qcom,pre-scaling = <1 3>;
+			};
+
+			/* PMR735a Channel nodes */
+			pmr735a_ref_gnd {
+				reg = <PMR735A_ADC7_REF_GND>;
+				label = "pmr735a_ref_gnd";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pmr735a_vref_1p25 {
+				reg = <PMR735A_ADC7_1P25VREF>;
+				label = "pmr735a_vref_1p25";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pmr735a_die_temp {
+				reg = <PMR735A_ADC7_DIE_TEMP>;
+				label = "pmr735a_die_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			/* PMR735b Channel nodes */
+			pmr735b_ref_gnd {
+				reg = <PMR735B_ADC7_REF_GND>;
+				label = "pmr735b_ref_gnd";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pmr735b_vref_1p25 {
+				reg = <PMR735B_ADC7_1P25VREF>;
+				label = "pmr735b_vref_1p25";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pmr735b_die_temp {
+				reg = <PMR735B_ADC7_DIE_TEMP>;
+				label = "pmr735b_die_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+		};
+
+		pmk8350_adc_tm: adc_tm@3400 {
+			compatible = "qcom,adc-tm7";
+			reg = <0x3400>;
+			interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "threshold";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#thermal-sensor-cells = <1>;
+		};
+
+		pmk8350_sdam_2: sdam@7100 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7100>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			restart_reason: restart@48 {
+				reg = <0x48 0x1>;
+				bits = <1 7>;
+			};
+		};
+
+		pmk8350_sdam_5: sdam@7400 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7400>;
+		};
+
+		pmk8350_sdam_13: sdam@7c00 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7c00>;
+		};
+
+		pmk8350_sdam_14: sdam@7d00 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7d00>;
+		};
+
+		pmk8350_sdam_21: sdam@8400 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x8400>;
+		};
+
+		pmk8350_sdam_22: sdam@8500 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x8500>;
+		};
+
+		pmk8350_sdam_41: sdam@9800 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x9800>;
+		};
+
+		pmk8350_sdam_46: sdam@9d00 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x9d00>;
+		};
+
+		pmk8350_gpios: pinctrl@b000 {
+			compatible = "qcom,pmk8350-gpio";
+			reg = <0xb000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pmk8350_rtc: rtc@6100 {
+			compatible = "qcom,pmk8350-rtc";
+			reg = <0x6100>, <0x6200>;
+			reg-names = "rtc", "alarm";
+			interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
+		};
+	};
+};
diff --git a/qcom/pmr735a.dtsi b/qcom/pmr735a.dtsi
new file mode 100644
index 00000000..d1459e15
--- /dev/null
+++ b/qcom/pmr735a.dtsi
@@ -0,0 +1,61 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pmr735a@4 {
+		compatible = "qcom,spmi-pmic";
+		reg = <4 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmr735a_tz: qcom,temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pmr735a_gpios: pinctrl@8800 {
+			compatible = "qcom,pmr735a-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
+
+&thermal_zones {
+	pmr735a_temp_alarm: pmr735a_tz {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pmr735a_tz>;
+
+		trips {
+			pmr735a_trip0: trip0 {
+				temperature = <95000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			pmr735a_trip1: trip1 {
+				temperature = <115000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+
+			pmr735a_trip2: trip2 {
+				temperature = <145000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+		};
+	};
+};
diff --git a/qcom/pmr735b.dtsi b/qcom/pmr735b.dtsi
new file mode 100644
index 00000000..50f05e4a
--- /dev/null
+++ b/qcom/pmr735b.dtsi
@@ -0,0 +1,61 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pmr735b@5 {
+		compatible = "qcom,spmi-pmic";
+		reg = <5 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmr735b_tz: qcom,temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pmr735b_gpios: pinctrl@8800 {
+			compatible = "qcom,pmr735b-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
+
+&thermal_zones {
+	pmr735b_temp_alarm: pmr735b_tz {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pmr735b_tz>;
+
+		trips {
+			pmr735b_trip0: trip0 {
+				temperature = <95000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			pmr735b_trip1: trip1 {
+				temperature = <115000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+
+			pmr735b_trip2: trip2 {
+				temperature = <145000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+		};
+	};
+};
diff --git a/qcom/sdxlemur-external-soc.dtsi b/qcom/sdxlemur-external-soc.dtsi
new file mode 100644
index 00000000..d09cd50c
--- /dev/null
+++ b/qcom/sdxlemur-external-soc.dtsi
@@ -0,0 +1,51 @@
+&soc {
+	mdm0: qcom,remoteproc-esoc0 {
+		cell-index = <0>;
+		#address-cells = <0>;
+		interrupt-parent = <&mdm0>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0xffffffff>;
+		interrupt-names =
+			"err_fatal_irq",
+			"status_irq";
+		interrupt-map = <0 &tlmm 36 0x3
+				 1 &tlmm 40 0x3>;
+		/* modem attributes */
+		qcom,ramdump-delay-ms = <3000>;
+		qcom,ramdump-timeout-ms = <120000>;
+		qcom,vddmin-modes = "normal";
+		qcom,vddmin-drive-strength = <8>;
+		qcom,sfr-query;
+		qcom,sysmon-id = <20>;
+		qcom,ssctl-instance-id = <0x10>;
+		qcom,support-shutdown;
+		qcom,pil-force-shutdown;
+		pinctrl-names = "default", "mdm_active", "mdm_suspend";
+		pinctrl-0 = <&ap2mdm_pon_reset_default>;
+		pinctrl-1 = <&ap2mdm_active &mdm2ap_active>;
+		pinctrl-2 = <&ap2mdm_sleep &mdm2ap_sleep>;
+		qcom,mdm2ap-errfatal-gpio = <&tlmm 36 0x00>;
+		qcom,ap2mdm-errfatal-gpio = <&tlmm 37 0x00>;
+		qcom,mdm2ap-status-gpio   = <&tlmm 40 0x00>;
+		qcom,ap2mdm-status-gpio   = <&tlmm 41 0x00>;
+		qcom,ap2mdm-soft-reset-gpio = <&pm8450_gpios 1 0>;
+
+		reg-names = "l10c";
+		l10c-supply = <&L10C>;
+		l10c-uV-uA = <1200000 100000>;
+
+		qcom,esoc-skip-restart-for-mdm-crash;
+		status = "ok";
+	};
+};
+
+&pm8450_gpios {
+	ap2mdm_pon_reset {
+		ap2mdm_pon_reset_default: ap2mdm_pon_reset_default {
+			/* MDM PON control*/
+			pins = "gpio1";
+			function = "normal";
+			power-source = <1>; /* 1.8V */
+		};
+	};
+};
diff --git a/qcom/waipio-atp-pm8008-overlay.dts b/qcom/waipio-atp-pm8008-overlay.dts
new file mode 100644
index 00000000..bf511e3f
--- /dev/null
+++ b/qcom/waipio-atp-pm8008-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "waipio-atp.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio ATP with PM8008";
+	compatible = "qcom,waipio-atp", "qcom,waipio", "qcom,atp";
+	qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
+	qcom,board-id = <0x10021 0>;
+};
diff --git a/qcom/waipio-atp-pm8008.dts b/qcom/waipio-atp-pm8008.dts
new file mode 100644
index 00000000..fec5c217
--- /dev/null
+++ b/qcom/waipio-atp-pm8008.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipio.dtsi"
+#include "waipio-atp.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio ATP with PM8008";
+	compatible = "qcom,waipio-atp", "qcom,waipio", "qcom,atp";
+	qcom,board-id = <33 0>;
+};
diff --git a/qcom/waipio-atp-pm8010-overlay.dts b/qcom/waipio-atp-pm8010-overlay.dts
new file mode 100644
index 00000000..413fb5d4
--- /dev/null
+++ b/qcom/waipio-atp-pm8010-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "waipio-atp.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio ATP with PM8010";
+	compatible = "qcom,waipio-atp", "qcom,waipio", "qcom,atp";
+	qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
+	qcom,board-id = <0x10021 0>;
+};
diff --git a/qcom/waipio-atp-pm8010.dts b/qcom/waipio-atp-pm8010.dts
new file mode 100644
index 00000000..94de84a9
--- /dev/null
+++ b/qcom/waipio-atp-pm8010.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipio.dtsi"
+#include "waipio-atp.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio ATP with PM8010";
+	compatible = "qcom,waipio-atp", "qcom,waipio", "qcom,atp";
+	qcom,board-id = <0x10021 0>;
+};
diff --git a/qcom/waipio-atp.dtsi b/qcom/waipio-atp.dtsi
new file mode 100644
index 00000000..188efe5a
--- /dev/null
+++ b/qcom/waipio-atp.dtsi
@@ -0,0 +1 @@
+#include "waipio-mtp.dtsi"
diff --git a/qcom/waipio-cdp-pm8008-overlay.dts b/qcom/waipio-cdp-pm8008-overlay.dts
new file mode 100644
index 00000000..23047240
--- /dev/null
+++ b/qcom/waipio-cdp-pm8008-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "waipio-cdp.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio CDP with PM8008";
+	compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
+	qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
+	qcom,board-id = <0x10001 0>;
+};
diff --git a/qcom/waipio-cdp-pm8008.dts b/qcom/waipio-cdp-pm8008.dts
new file mode 100644
index 00000000..e44a7e53
--- /dev/null
+++ b/qcom/waipio-cdp-pm8008.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipio.dtsi"
+#include "waipio-cdp.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio CDP with PM8008";
+	compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
+	qcom,board-id = <1 0>;
+};
diff --git a/qcom/waipio-cdp-pm8010-overlay.dts b/qcom/waipio-cdp-pm8010-overlay.dts
new file mode 100644
index 00000000..bd5641e7
--- /dev/null
+++ b/qcom/waipio-cdp-pm8010-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "waipio-cdp.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio CDP with PM8010";
+	compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
+	qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
+	qcom,board-id = <0x10001 0>;
+};
diff --git a/qcom/waipio-cdp-pm8010.dts b/qcom/waipio-cdp-pm8010.dts
new file mode 100644
index 00000000..a276d4a0
--- /dev/null
+++ b/qcom/waipio-cdp-pm8010.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipio.dtsi"
+#include "waipio-cdp.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio CDP with PM8010";
+	compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
+	qcom,board-id = <0x10001 0>;
+};
diff --git a/qcom/waipio-cdp.dtsi b/qcom/waipio-cdp.dtsi
new file mode 100644
index 00000000..46046079
--- /dev/null
+++ b/qcom/waipio-cdp.dtsi
@@ -0,0 +1,222 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "waipio-pmic-overlay.dtsi"
+#include "waipio-thermal-overlay.dtsi"
+
+&ufsphy_mem {
+	compatible = "qcom,ufs-phy-qmp-v4-waipio";
+
+	vdda-phy-supply = <&pm8350_l5>;
+	vdda-pll-supply = <&pm8350_l6>;
+	vdda-phy-max-microamp = <173000>;
+	vdda-pll-max-microamp = <24900>;
+
+	status = "ok";
+};
+
+&ufshc_mem {
+	vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+
+	vcc-supply = <&pm8350_l7>;
+	vcc-max-microamp = <1100000>;
+
+	vccq-supply = <&pm8350_l9>;
+	vccq-max-microamp = <1200000>;
+
+	qcom,vddp-ref-clk-supply = <&pm8350_l9>;
+	qcom,vddp-ref-clk-max-microamp = <100>;
+
+	qcom,vccq-parent-supply = <&pm8350_s12>;
+	qcom,vccq-parent-max-microamp = <210000>;
+
+	status = "ok";
+};
+
+&sdhc_2 {
+	status = "ok";
+	vdd-supply = <&pm8350c_l9>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 800000>;
+
+	vdd-io-supply = <&pm8350c_l6>;
+	qcom,vdd-io-voltage-level = <1800000 2960000>;
+	qcom,vdd-io-current-level = <0 22000>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_on>;
+	pinctrl-1 = <&sdc2_off>;
+
+	cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
+};
+
+&soc {
+	gpio_keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_vol_up_default>;
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&pm8350_gpios 6 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEUP>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+			linux,can-disable;
+		};
+	};
+};
+
+&pm8350b_haptics {
+	status = "ok";
+};
+
+&pm8350c_switch0 {
+	qcom,led-mask = <9>; /* Channels 1 & 4 */
+	qcom,symmetry-en;
+};
+
+&pm8350c_switch1 {
+	qcom,led-mask = <6>; /* Channels 2 & 3 */
+	qcom,symmetry-en;
+};
+
+&pm8350c_switch2 {
+	qcom,led-mask = <15>; /* All Channels */
+	qcom,symmetry-en;
+};
+
+&pm8350c_flash {
+	status = "ok";
+};
+
+&qupv3_se9_i2c {
+	status = "ok";
+	qcom,clk-freq-out = <1000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	nq@28 {
+		compatible = "qcom,sn-nci";
+		reg = <0x28>;
+		qcom,sn-irq = <&tlmm 46 0x00>;
+		qcom,sn-ven = <&tlmm 34 0x00>;
+		qcom,sn-firm = <&tlmm 45 0x00>;
+		qcom,sn-clkreq = <&tlmm 35 0x00>;
+		qcom,sn-vdd-1p8-supply = <&S10B>;
+		qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
+		qcom,sn-vdd-1p8-current = <157000>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <46 0>;
+		interrupt-names = "nfc_irq";
+		pinctrl-names = "nfc_active", "nfc_suspend";
+		pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
+		pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
+	};
+};
+
+&qupv3_se4_i2c {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	status = "ok";
+	qcom,i2c-touch-active = "focaltech,fts_ts";
+
+	focaltech@38 {
+		compatible = "focaltech,fts_ts";
+		reg = <0x38>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <21 0x2008>;
+		focaltech,reset-gpio = <&tlmm 20 0x00>;
+		focaltech,irq-gpio = <&tlmm 21 0x2008>;
+		focaltech,max-touch-number = <5>;
+		focaltech,display-coords = <0 0 1080 2340>;
+		focaltech,touch-type = "primary";
+
+		vdd-supply = <&L3C>;
+		vcc_i2c-supply = <&L8C>;
+
+		pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release";
+		pinctrl-0 = <&ts_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+		pinctrl-2 = <&ts_release>;
+		focaltech,trusted-touch-mode = "vm_mode";
+		focaltech,touch-environment = "pvm";
+		focaltech,trusted-touch-spi-irq = <754>;
+		focaltech,trusted-touch-io-bases = <0xF110000 0xF111000 0xF112000 0xF113000
+						0xF114000 0xF115000  0x990000 0x00910000>;
+		focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000
+						0x1000 0x1000 0x1000 0x4000>;
+	};
+
+	atmel_mxt_ts@4a {
+		compatible = "atmel,maxtouch";
+		reg = <0x4a>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <21 0x2008>;
+		avdd-supply = <&L3C>;
+		vdd-supply = <&L8C>;
+		pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
+		pinctrl-0 = <&ts_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+
+		atmel,xy_switch;
+		atmel,inverty;
+		atmel,invertx;
+		reset-gpios = <&tlmm 20 0x00>;
+		irq-gpios = <&tlmm 21 0x2008>;
+		atmel,panel-coords = <0 0 479 799>;
+		atmel,display-coords = <0 0 339 729>;
+	};
+
+	synaptics_dsx@22 {
+		compatible = "synaptics,dsx-i2c";
+		reg = <0x22>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <21 0x2008>;
+		vdd-supply = <&L8C>;
+		avdd-supply = <&L3C>;
+		pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release";
+		pinctrl-0 = <&ts_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+		pinctrl-2 = <&ts_release>;
+		synaptics,pwr-reg-name = "avdd";
+		synaptics,bus-reg-name = "vdd";
+		synaptics,ub-i2c-addr = <0x22>;
+		synaptics,max-y-for-2d = <1859>;
+		synaptics,irq-gpio = <&tlmm 21 0x2008>;
+		synaptics,reset-gpio = <&tlmm 20 0x00>;
+		synaptics,irq-on-state = <0>;
+		synaptics,power-delay-ms = <200>;
+		synaptics,reset-delay-ms = <200>;
+		synaptics,reset-on-state = <0>;
+		synaptics,reset-active-ms = <20>;
+	};
+};
+
+&usb0 {
+	usb-role-switch;
+
+	dwc3@a600000 {
+		usb-role-switch;
+		dr_mode = "otg";
+	};
+
+	port {
+		usb_port0: endpoint {
+			remote-endpoint = <&usb_port0_connector>;
+		};
+	};
+};
+
+&ucsi {
+	connector {
+		port {
+			usb_port0_connector: endpoint {
+				remote-endpoint = <&usb_port0>;
+			};
+		};
+	};
+};
diff --git a/qcom/waipio-coresight.dtsi b/qcom/waipio-coresight.dtsi
new file mode 100644
index 00000000..4dbeb233
--- /dev/null
+++ b/qcom/waipio-coresight.dtsi
@@ -0,0 +1,4015 @@
+&soc {
+	ssc_etm0 {
+		compatible = "qcom,coresight-remote-etm";
+
+		coresight-name = "coresight-ssc-etm0";
+		qcom,inst-id = <8>;
+		atid = <34>;
+
+		out-ports {
+			port {
+				ssc_etm0_out_funnel_ssc: endpoint {
+					remote-endpoint =
+						<&funnel_ssc_in_ssc_etm0>;
+				};
+			};
+		};
+	};
+
+	audio_etm0 {
+		compatible = "qcom,coresight-remote-etm";
+
+		coresight-name = "coresight-audio-etm0";
+		qcom,inst-id = <5>;
+		atid = <40>;
+
+		out-ports {
+			port {
+				audio_etm0_out_funnel_lpass_lpi: endpoint {
+					remote-endpoint =
+					<&funnel_lpass_lpi_in_audio_etm0>;
+				};
+			};
+		};
+	};
+
+	tpdm_lpass_lpi: tpdm_lpass_lpi {
+		compatible = "qcom,coresight-dummy";
+		coresight-name = "coresight-tpdm-lpass-lpi";
+		qcom,dummy-source;
+
+		atid = <26>;
+
+		out-ports {
+			port {
+				tpdm_lpass_lpi_out_funnel_lpass_lpi: endpoint {
+					remote-endpoint =
+					<&funnel_lpass_lpi_in_tpdm_lpass_lpi>;
+				};
+			};
+		};
+	};
+
+	lpass_stm: lpass_stm {
+		compatible = "qcom,coresight-dummy";
+		coresight-name = "coresight-lpass-stm";
+		qcom,dummy-source;
+
+		atid = <25>;
+
+		out-ports {
+			port {
+				lpass_stm_out_funnel_lpass_lpi: endpoint {
+					remote-endpoint =
+					<&funnel_lpass_lpi_in_lpass_stm>;
+				};
+			};
+		};
+	};
+
+	sensor_stm: sensor_stm {
+		compatible = "qcom,coresight-dummy";
+		coresight-name = "coresight-sensor-stm";
+		qcom,dummy-source;
+
+		atid = <23>;
+
+		out-ports {
+			port {
+				sensor_stm_out_funnel_ssc: endpoint {
+					remote-endpoint =
+					<&funnel_ssc_in_sensor_stm>;
+				};
+			};
+		};
+	};
+
+	tpdm_swao_prio_0: tpdm@10b09000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10b09000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <71>;
+		coresight-name = "coresight-tpdm-swao-prio-0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_swao_prio_0_out_tpda_aoss_0: endpoint {
+					remote-endpoint =
+					<&tpda_aoss_0_in_tpdm_swao_prio_0>;
+				};
+			};
+		};
+	};
+
+	tpdm_swao_prio_1: tpdm@10b0a000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10b0a000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <71>;
+		coresight-name = "coresight-tpdm-swao-prio-1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_swao_prio_1_out_tpda_aoss_1: endpoint {
+					remote-endpoint =
+					<&tpda_aoss_1_in_tpdm_swao_prio_1>;
+				};
+			};
+		};
+	};
+
+	tpdm_swao_prio_2: tpdm@10b0b000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10b0b000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <71>;
+		coresight-name = "coresight-tpdm-swao-prio-2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_swao_prio_2_out_tpda_aoss_2: endpoint {
+					remote-endpoint =
+					<&tpda_aoss_2_in_tpdm_swao_prio_2>;
+				};
+			};
+		};
+	};
+
+	tpdm_swao_prio_3: tpdm@10b0c000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10b0c000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <71>;
+		coresight-name = "coresight-tpdm-swao-prio-3";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_swao_prio_3_out_tpda_aoss_3: endpoint {
+					remote-endpoint =
+					<&tpda_aoss_3_in_tpdm_swao_prio_3>;
+				};
+			};
+		};
+	};
+
+	tpdm_lpass: tpdm@10844000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10844000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-lpass";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		atid = <78>;
+		out-ports {
+			port {
+				tpdm_lpass_out_funnel_lpass: endpoint {
+					remote-endpoint =
+					<&funnel_lpass_in_tpdm_lpass>;
+				};
+			};
+		};
+	};
+
+	tpdm_ddr_ch02: tpdm@10d20000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10d20000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-ddr-ch02";
+
+		atid = <78>;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_ddr_ch02_out_funnel_ddr_ch02: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_ch02_in_tpdm_ddr_ch02>;
+				};
+			};
+		};
+	};
+
+	tpdm_ddr_ch13: tpdm@10d30000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10d30000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <78>;
+		coresight-name = "coresight-tpdm-ddr-ch13";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_ddr_ch13_out_funnel_ddr_ch13: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_ch13_in_tpdm_ddr_ch13>;
+				};
+			};
+		};
+	};
+
+	tpdm_ddr: tpdm@10d00000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10d00000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <78>;
+		coresight-name = "coresight-tpdm-ddr";
+
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_ddr_dl0_0_out_funnel_ddr_dl0: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_dl0_in_tpdm_ddr_dl0_0>;
+				};
+			};
+		};
+	};
+
+	tpdm_shrm: tpdm@10d01000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10d01000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <78>;
+		status = "disabled";
+		coresight-name = "coresight-tpdm-shrm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_ddr_dl0_1_out_funnel_ddr_dl0: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_dl0_in_tpdm_ddr_dl0_1>;
+				};
+			};
+		};
+	};
+
+	tpdm_video: tpdm@10830000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10830000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <78>;
+		coresight-name = "coresight-tpdm-video";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_video_out_funnel_video: endpoint {
+					remote-endpoint =
+					<&funnel_video_in_tpdm_video>;
+				};
+			};
+		};
+	};
+
+	tpdm_mdss: tpdm@10c60000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10c60000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <78>;
+		coresight-name = "coresight-tpdm-mdss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_mdss_out_funnel_multimedia: endpoint {
+					remote-endpoint =
+					<&funnel_multimedia_in_tpdm_mdss>;
+				};
+			};
+		};
+	};
+
+	tpdm_mm: tpdm@10c08000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10c08000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <78>;
+		coresight-name = "coresight-tpdm-mm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_dlmm_out_funnel_multimedia: endpoint {
+					remote-endpoint =
+					<&funnel_multimedia_in_tpdm_dlmm>;
+				};
+			};
+		};
+	};
+
+	tpdm_rdpm: tpdm@10c38000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10c38000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <78>;
+		coresight-name = "coresight-tpdm-rdpm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_dlwt0_out_funnel_dl_west: endpoint {
+					remote-endpoint =
+					<&funnel_dl_west_in_tpdm_dlwt0>;
+				};
+			};
+		};
+	};
+
+	tpdm_rdpm_mx: tpdm@10c39000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10c39000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <78>;
+		coresight-name = "coresight-tpdm-rdpm-mx";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_dlwt1_out_funnel_dl_west: endpoint {
+					remote-endpoint =
+					<&funnel_dl_west_in_tpdm_dlwt1>;
+				};
+			};
+		};
+	};
+
+	tpdm_turing: tpdm@10980000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10980000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-turing";
+
+		atid = <78>;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_turing_out_funnel_turing: endpoint {
+					remote-endpoint =
+					<&funnel_turing_in_tpdm_turing>;
+				};
+			};
+		};
+	};
+
+	tpdm_turing_llm: tpdm_turing_llm {
+		compatible = "qcom,coresight-dummy";
+		coresight-name = "coresight-tpdm-turing-llm";
+		qcom,dummy-source;
+
+		atid = <78>;
+
+		out-ports {
+			port {
+				tpdm_turing_llm_out_funnel_turing: endpoint {
+					remote-endpoint =
+					<&funnel_turing_in_tpdm_turing_llm>;
+				};
+			};
+		};
+	};
+
+	tpdm_gpu: tpdm@10900000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10900000 0x1000>;
+		reg-names = "tpdm-base";
+
+		status = "disabled";
+
+		coresight-name = "coresight-tpdm-gpu";
+		atid = <78>;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_gpu_out_funnel_gfx_dl: endpoint {
+					remote-endpoint =
+					<&funnel_gfx_dl_in_tpdm_gpu>;
+				};
+			};
+		};
+	};
+
+	tpdm_prng: tpdm@10841000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10841000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-prng";
+
+		atid = <78>;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_prng_out_tpda_dl_center_19: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_19_in_tpdm_prng>;
+				};
+			};
+		};
+	};
+
+	tpdm_qm: tpdm@109d0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x109d0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <78>;
+		coresight-name = "coresight-tpdm-qm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_qm_out_tpda_dl_center_20: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_20_in_tpdm_qm>;
+				};
+			};
+		};
+	};
+
+	tpdm_gcc: tpdm@1082c000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x1082c000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <78>;
+		coresight-name = "coresight-tpdm-gcc";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_gcc_out_tpda_dl_center_21: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_21_in_tpdm_gcc>;
+				};
+			};
+		};
+	};
+
+	tpdm_vsense: tpdm@10840000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10840000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <78>;
+		coresight-name = "coresight-tpdm-vsense";
+
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_vsense_out_tpda_dl_center_22: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_22_in_tpdm_vsense>;
+				};
+			};
+		};
+	};
+
+	tpdm_ipa: tpdm@10c22000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10c22000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <78>;
+		coresight-name = "coresight-tpdm-ipa";
+		status = "disabled";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_ipa_out_tpda_dl_center_23: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_23_in_tpdm_ipa>;
+				};
+			};
+		};
+	};
+
+	tpdm_pimem: tpdm@10850000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10850000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <78>;
+		coresight-name = "coresight-tpdm-pimem";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_pimem_out_tpda_dl_center_25: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_25_in_tpdm_pimem>;
+				};
+			};
+		};
+	};
+
+	tpdm_dlct: tpdm@10c28000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10c28000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <78>;
+		coresight-name = "coresight-tpdm-dlct";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_dlct_out_tpda_dl_center_26: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_26_in_tpdm_dlct>;
+				};
+			};
+		};
+	};
+
+	tpdm_ipcc: tpdm@10c29000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10c29000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <78>;
+		coresight-name = "coresight-tpdm-ipcc";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_ipcc_out_tpda_dl_center_27: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_27_in_tpdm_ipcc>;
+				};
+			};
+		};
+	};
+
+	tpdm_swao_1: tpdm@10b0d000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10b0d000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <71>;
+		coresight-name = "coresight-tpdm-swao-1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_swao_out_tpda_aoss_4: endpoint {
+					remote-endpoint =
+					<&tpda_aoss_4_in_tpdm_swao>;
+				};
+			};
+		};
+	};
+
+	snoc: snoc {
+		compatible = "qcom,coresight-dummy";
+		coresight-name = "coresight-snoc";
+		qcom,dummy-source;
+
+		atid = <125>;
+		out-ports {
+			port {
+				snoc_out_funnel_in0: endpoint {
+					remote-endpoint =
+					<&funnel_in0_in_snoc>;
+				};
+			};
+		};
+	};
+
+	tpdm_spdm: tpdm@1000f000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x1000f000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <65>;
+		coresight-name = "coresight-tpdm-spdm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_spdm_out_tpda_qdss_1: endpoint {
+					remote-endpoint =
+					<&tpda_qdss_1_in_tpdm_spdm>;
+				};
+			};
+		};
+	};
+
+	stm: stm@10002000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb962>;
+		reg = <0x10002000 0x1000>,
+			<0x16280000 0x180000>;
+		reg-names = "stm-base", "stm-stimulus-base";
+
+		atid = <16>;
+		coresight-name = "coresight-stm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				stm_out_funnel_in0: endpoint {
+					remote-endpoint =
+					<&funnel_in0_in_stm>;
+				};
+			};
+		};
+	};
+
+	tpdm_dcc: tpdm@10003000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10003000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <65>;
+		coresight-name = "coresight-tpdm-dcc";
+
+		qcom,hw-enable-check;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_dcc_out_tpda_qdss_0: endpoint {
+					remote-endpoint =
+					<&tpda_qdss_0_in_tpdm_dcc>;
+				};
+			};
+		};
+	};
+
+	turing_etm0: turing_etm0 {
+		compatible = "qcom,coresight-remote-etm";
+
+		coresight-name = "coresight-turing-etm0";
+		qcom,inst-id = <13>;
+
+		atid = <38 39>;
+
+		out-ports {
+			port {
+				turing_etm0_out_funnel_turing_dup: endpoint {
+					remote-endpoint =
+						<&funnel_turing_dup_in_turing_etm0>;
+				};
+			};
+		};
+	};
+
+	tpdm_spss: tpdm@10880000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10880000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <70>;
+		coresight-name = "coresight-tpdm-spss";
+		status = "disabled";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_spss_out_tpda_spss: endpoint {
+					remote-endpoint =
+					<&tpda_spss_in_tpdm_spss>;
+				};
+			};
+		};
+	};
+
+	tpda_spss: tpda@10882000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x10882000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-spss";
+		status = "disabled";
+
+		qcom,tpda-atid = <70>;
+		qcom,cmb-elem-size = <0 32>;
+		qcom,dsb-elem-size = <0 32>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpda_spss_out_funnel_spss: endpoint {
+					remote-endpoint =
+					<&funnel_spss_in_tpda_spss>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tpda_spss_in_tpdm_spss: endpoint {
+					remote-endpoint =
+					<&tpdm_spss_out_tpda_spss>;
+				};
+			};
+
+		};
+	};
+
+	tpdm_dl_south: tpdm@109c0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x109c0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <75>;
+		coresight-name = "coresight-tpdm-dl-south";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_dl_south_out_tpda_dl_south_2: endpoint {
+					remote-endpoint =
+					<&tpda_dl_south_2_in_tpdm_dl_south>;
+				};
+			};
+		};
+	};
+
+	tpdm_dl_north: tpdm@10ac0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10ac0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <97>;
+		coresight-name = "coresight-tpdm-dl-north";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_dl_north_out_tpda_dl_north_2: endpoint {
+					remote-endpoint =
+					<&tpda_dl_north_2_in_tpdm_dl_north>;
+				};
+			};
+		};
+	};
+
+	tpdm_llm_silver: tpdm@138a0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x138a0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <66>;
+		coresight-name = "coresight-tpdm-llm-silver";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_llm_silver_out_tpda_apss_0: endpoint {
+					remote-endpoint =
+					<&tpda_apss_0_in_tpdm_llm_silver>;
+				};
+			};
+		};
+	};
+
+	tpdm_llm_gold: tpdm@138b0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x138b0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <66>;
+		coresight-name = "coresight-tpdm-llm-gold";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_llm_gold_out_tpda_apss_1: endpoint {
+					remote-endpoint =
+					<&tpda_apss_1_in_tpdm_llm_gold>;
+				};
+			};
+		};
+	};
+
+	tpdm_apss_llm: tpdm@138c0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x138c0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <66>;
+		coresight-name = "coresight-tpdm-apss-llm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_apss_llm_out_tpda_apss_2: endpoint {
+					remote-endpoint =
+					<&tpda_apss_2_in_tpdm_apss_llm>;
+				};
+			};
+		};
+	};
+
+	tpdm_actpm: tpdm@13860000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x13860000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <66>;
+		coresight-name = "coresight-tpdm-actpm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_apss0_out_tpda_apss_3: endpoint {
+					remote-endpoint =
+					<&tpda_apss_3_in_tpdm_apss0>;
+				};
+			};
+		};
+	};
+
+	tpdm_apss: tpdm@13861000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x13861000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <66>;
+		coresight-name = "coresight-tpdm-apss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_apps1_out_tpda_apss_4: endpoint {
+					remote-endpoint =
+					<&tpda_apss_4_in_tpdm_apps1>;
+				};
+			};
+		};
+	};
+
+	tpdm_modem_0: tpdm@10800000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10800000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <67>;
+		coresight-name = "coresight-tpdm-modem-0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_modem_0_out_tpda_modem_0: endpoint {
+					remote-endpoint =
+					<&tpda_modem_0_in_tpdm_modem_0>;
+				};
+			};
+		};
+	};
+
+	tpdm_modem_1: tpdm@10801000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10801000 0x1000>;
+		reg-names = "tpdm-base";
+
+		status = "disabled";
+		atid = <67>;
+		coresight-name = "coresight-tpdm-modem-1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_modem_1_out_tpda_modem_1: endpoint {
+					remote-endpoint =
+					<&tpda_modem_1_in_tpdm_modem_1>;
+				};
+			};
+		};
+	};
+
+	modem_etm0 {
+		compatible = "qcom,coresight-remote-etm";
+
+		coresight-name = "coresight-modem-etm0";
+		qcom,inst-id = <2>;
+
+		atid = <36 37>;
+		out-ports {
+			port {
+				modem_etm0_out_funnel_modem_q6_dup: endpoint {
+					remote-endpoint =
+						<&funnel_modem_q6_dup_in_modem_etm0>;
+				};
+			};
+		};
+	};
+
+	modem2_etm0 {
+		compatible = "qcom,coresight-remote-etm";
+
+		coresight-name = "coresight-modem2-etm0";
+		qcom,inst-id = <11>;
+
+		atid = <39>;
+		out-ports {
+			port {
+				modem2_etm0_out_funnel_modem: endpoint {
+					remote-endpoint =
+						<&funnel_modem_in_modem2_etm0>;
+				};
+			};
+		};
+	};
+
+	modem_diag: modem_diag {
+		compatible = "qcom,coresight-dummy";
+		coresight-name = "coresight-modem-diag";
+		qcom,dummy-source;
+
+		atid = <50>;
+		out-ports {
+			port {
+				modem_diag_out_funnel_modem_q6: endpoint {
+					remote-endpoint =
+					<&funnel_modem_q6_in_modem_diag>;
+				};
+			};
+		};
+	};
+
+	tpdm_sdcc2: tpdm@10c21000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10c21000 0x1000>;
+		reg-names = "tpdm-base";
+
+		status = "disabled";
+		atid = <97>;
+		coresight-name = "coresight-tpdm-sdcc-2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_sdcc2_out_tpda_dl_north_1: endpoint {
+					remote-endpoint =
+					<&tpda_dl_north_1_in_tpdm_sdcc2>;
+				};
+			};
+		};
+	};
+
+	tpdm_sdcc4: tpdm@10c20000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10c20000 0x1000>;
+		reg-names = "tpdm-base";
+
+		status = "disabled";
+		atid = <75>;
+		coresight-name = "coresight-tpdm-sdcc-4";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_sdcc4_out_tpda_dl_south_1: endpoint {
+					remote-endpoint =
+					<&tpda_dl_south_1_in_tpdm_sdcc4>;
+				};
+			};
+		};
+	};
+
+	tpdm_tmess_prng: tpdm@10cc9000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10cc9000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <85>;
+		coresight-name = "coresight-tpdm-tmess-prng";
+
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_tmess_prng_out_tpda_tmess_0: endpoint {
+					remote-endpoint =
+					<&tpda_tmess_0_in_tpdm_tmess_prng>;
+				};
+			};
+		};
+	};
+
+	tpdm_tmess_0: tpdm@10cc1000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10cc1000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <85>;
+		coresight-name = "coresight-tpdm-tmess-0";
+
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_tmess_0_out_tpda_tmess_1: endpoint {
+					remote-endpoint =
+					<&tpda_tmess_1_in_tpdm_tmess_0>;
+				};
+			};
+		};
+	};
+
+	tpdm_tmess_1: tpdm@10cc0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10cc0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <85>;
+		coresight-name = "coresight-tpdm-tmess-1";
+
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_tmess_1_out_tpda_tmess_2: endpoint {
+					remote-endpoint =
+					<&tpda_tmess_2_in_tpdm_tmess_1>;
+				};
+			};
+		};
+	};
+
+	funnel_ssc: funnel@10b24000 {
+		compatible = "arm,coresight-static-funnel";
+		coresight-name = "coresight-funnel-ssc";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_ssc_in_ssc_etm0: endpoint {
+					remote-endpoint =
+					<&ssc_etm0_out_funnel_ssc>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_ssc_in_sensor_stm: endpoint {
+					remote-endpoint =
+					<&sensor_stm_out_funnel_ssc>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				funnel_ssc_out_funnel_aoss: endpoint {
+					remote-endpoint =
+					<&funnel_aoss_in_funnel_ssc>;
+				};
+			};
+
+		};
+	};
+
+	funnel_lpass_lpi: funnel@10b44000 {
+		compatible = "arm,coresight-static-funnel";
+		coresight-name = "coresight-funnel-lpass_lpi";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_lpass_lpi_in_audio_etm0: endpoint {
+					remote-endpoint =
+					<&audio_etm0_out_funnel_lpass_lpi>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_lpass_lpi_in_lpass_stm: endpoint {
+					remote-endpoint =
+					<&lpass_stm_out_funnel_lpass_lpi>;
+				};
+			};
+
+			port@5 {
+				reg = <5>;
+				funnel_lpass_lpi_in_tpdm_lpass_lpi: endpoint {
+					remote-endpoint =
+					<&tpdm_lpass_lpi_out_funnel_lpass_lpi>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_lpass_lpi_out_funnel_aoss: endpoint {
+					remote-endpoint =
+					<&funnel_aoss_in_funnel_lpass_lpi>;
+				};
+			};
+
+		};
+	};
+
+	funnel_gfx_dl: funnel@10902000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10902000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-gfx_dl";
+
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				funnel_gfx_dl_in_tpdm_gpu: endpoint {
+					remote-endpoint =
+					<&tpdm_gpu_out_funnel_gfx_dl>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_gfx_dl_out_tpda_dl_center_17: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_17_in_funnel_gfx_dl>;
+				};
+			};
+
+		};
+	};
+
+	funnel_video: funnel@10832000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10832000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-video";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				funnel_video_in_tpdm_video: endpoint {
+					remote-endpoint =
+					<&tpdm_video_out_funnel_video>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_video_out_funnel_multimedia: endpoint {
+					remote-endpoint =
+					<&funnel_multimedia_in_funnel_video>;
+				};
+			};
+
+		};
+	};
+
+	funnel_multimedia: funnel@10c0b000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10c0b000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-multimedia";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_multimedia_in_funnel_video: endpoint {
+					remote-endpoint =
+					<&funnel_video_out_funnel_multimedia>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_multimedia_in_tpdm_mdss: endpoint {
+					remote-endpoint =
+					<&tpdm_mdss_out_funnel_multimedia>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				funnel_multimedia_in_tpdm_dlmm: endpoint {
+					remote-endpoint =
+					<&tpdm_dlmm_out_funnel_multimedia>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_multimedia_out_funnel_dl_west: endpoint {
+					remote-endpoint =
+					<&funnel_dl_west_in_funnel_multimedia>;
+				};
+			};
+
+		};
+	};
+
+	funnel_lpass: funnel@10846000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10846000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-lpass";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				funnel_lpass_in_tpdm_lpass: endpoint {
+					remote-endpoint =
+					<&tpdm_lpass_out_funnel_lpass>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_lpass_out_tpda_dl_center_4: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_4_in_funnel_lpass>;
+				};
+			};
+
+		};
+	};
+
+	funnel_ddr_ch02: funnel@10d22000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10d22000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-ddr_ch02";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				funnel_ddr_ch02_in_tpdm_ddr_ch02: endpoint {
+					remote-endpoint =
+					<&tpdm_ddr_ch02_out_funnel_ddr_ch02>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_ddr_ch02_out_funnel_ddr_dl0: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_dl0_in_funnel_ddr_ch02>;
+				};
+			};
+
+		};
+	};
+
+	funnel_ddr_ch13: funnel@10d32000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10d32000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-ddr_ch13";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				funnel_ddr_ch13_in_tpdm_ddr_ch13: endpoint {
+					remote-endpoint =
+					<&tpdm_ddr_ch13_out_funnel_ddr_ch13>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_ddr_ch13_out_funnel_ddr_dl0: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_dl0_in_funnel_ddr_ch13>;
+				};
+			};
+
+		};
+	};
+
+	gladiator: gladiator {
+		compatible = "qcom,coresight-dummy";
+		coresight-name = "coresight-gladiator";
+		qcom,dummy-source;
+
+		atid = <96>;
+
+		out-ports {
+			port {
+				gladiator_out_funnel_ddr_dl1: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_dl1_in_gladiator>;
+				};
+			};
+		};
+	};
+
+	funnel_ddr_dl1: funnel@10d0f000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10d0f000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-ddr_dl1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@6 {
+				reg = <6>;
+				funnel_ddr_dl1_in_gladiator: endpoint {
+					remote-endpoint =
+					<&gladiator_out_funnel_ddr_dl1>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_ddr_dl1_out_funnel_ddr_dl0: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_dl0_in_funnel_ddr_dl1>;
+				};
+			};
+		};
+
+	};
+
+	funnel_ddr_dl0: funnel@10d05000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10d05000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-ddr_dl0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				funnel_ddr_dl0_in_funnel_ddr_ch13: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_ch13_out_funnel_ddr_dl0>;
+				};
+			};
+
+			port@0 {
+				reg = <0>;
+				funnel_ddr_dl0_in_funnel_ddr_ch02: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_ch02_out_funnel_ddr_dl0>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				funnel_ddr_dl0_in_tpdm_ddr_dl0_1: endpoint {
+					remote-endpoint =
+					<&tpdm_ddr_dl0_1_out_funnel_ddr_dl0>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				funnel_ddr_dl0_in_tpdm_ddr_dl0_0: endpoint {
+					remote-endpoint =
+					<&tpdm_ddr_dl0_0_out_funnel_ddr_dl0>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				funnel_ddr_dl0_in_funnel_ddr_dl1: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_dl1_out_funnel_ddr_dl0>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_ddr_dl0_out_tpda_dl_center_5: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_5_in_funnel_ddr_dl0>;
+					source = <&tpdm_ddr_ch02>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_ddr_dl0_out_tpda_dl_center_6: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_6_in_funnel_ddr_dl0>;
+					source = <&tpdm_ddr_ch13>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				funnel_ddr_dl0_out_tpda_dl_center_7: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_7_in_funnel_ddr_dl0>;
+					source = <&tpdm_ddr>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				funnel_ddr_dl0_out_tpda_dl_center_8: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_8_in_funnel_ddr_dl0>;
+					source = <&tpdm_shrm>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				funnel_ddr_dl0_out_funnel_dl_center: endpoint {
+					remote-endpoint =
+					<&funnel_dl_center_in_funnel_ddr_dl0>;
+				};
+			};
+		};
+	};
+
+	funnel_turing_dup: funnel@10986000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10986000 0x1000>,
+			<0x10985000 0x1000>;
+		reg-names = "funnel-base-dummy", "funnel-base-real";
+
+		coresight-name = "coresight-funnel-turing_dup";
+
+		qcom,duplicate-funnel;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@3 {
+				reg = <3>;
+				funnel_turing_dup_in_turing_etm0: endpoint {
+					remote-endpoint =
+					<&turing_etm0_out_funnel_turing_dup>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_turing_dup_out_funnel_turing: endpoint {
+					remote-endpoint =
+					<&funnel_turing_in_funnel_turing_dup>;
+				};
+			};
+
+		};
+	};
+
+	funnel_turing: funnel@10985000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10985000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-turing";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_turing_in_tpdm_turing: endpoint {
+					remote-endpoint =
+					<&tpdm_turing_out_funnel_turing>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_turing_in_tpdm_turing_llm: endpoint {
+					remote-endpoint =
+					<&tpdm_turing_llm_out_funnel_turing>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				funnel_turing_in_funnel_turing_dup: endpoint {
+					remote-endpoint =
+					<&funnel_turing_dup_out_funnel_turing>;
+				};
+			};
+
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_turing_out_tpda_dl_center_15: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_15_in_funnel_turing>;
+					source = <&tpdm_turing>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_turing_out_tpda_dl_center_16: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_16_in_funnel_turing>;
+					source = <&tpdm_turing_llm>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				funnel_turing_out_funnel_dl_center: endpoint {
+					remote-endpoint =
+					<&funnel_dl_center_in_funnel_turing>;
+				};
+			};
+
+		};
+	};
+
+	funnel_spss: funnel@10883000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10883000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-spss";
+		status = "disabled";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				funnel_spss_in_tpda_spss: endpoint {
+					remote-endpoint =
+					<&tpda_spss_out_funnel_spss>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_spss_out_funnel_dl_north: endpoint {
+					remote-endpoint =
+					<&funnel_dl_north_in_funnel_spss>;
+				};
+			};
+
+		};
+	};
+
+	funnel_dl_west: funnel@10c3a000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10c3a000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-dl_west";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_dl_west_in_funnel_multimedia: endpoint {
+					remote-endpoint =
+					<&funnel_multimedia_out_funnel_dl_west>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_dl_west_in_tpdm_dlwt0: endpoint {
+					remote-endpoint =
+					<&tpdm_dlwt0_out_funnel_dl_west>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				funnel_dl_west_in_tpdm_dlwt1: endpoint {
+					remote-endpoint =
+					<&tpdm_dlwt1_out_funnel_dl_west>;
+				};
+			};
+
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_dl_west_out_tpda_dl_center_9: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_9_in_funnel_dl_west>;
+					source = <&tpdm_video>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_dl_west_out_tpda_dl_center_10: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_10_in_funnel_dl_west>;
+					source = <&tpdm_mdss>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				funnel_dl_west_out_tpda_dl_center_12: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_12_in_funnel_dl_west>;
+					source = <&tpdm_mm>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				funnel_dl_west_out_tpda_dl_center_13: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_13_in_funnel_dl_west>;
+					source = <&tpdm_rdpm>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				funnel_dl_west_out_tpda_dl_center_14: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_14_in_funnel_dl_west>;
+					source = <&tpdm_rdpm_mx>;
+				};
+			};
+
+		};
+	};
+
+	tpda_dl_south: tpda@109c1000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+
+		reg = <0x109c1000 0x1000>;
+		reg-names = "tpda-base";
+
+		qcom,tpda-atid = <75>;
+
+		qcom,dsb-elem-size = <2 32>;
+		qcom,cmb-elem-size = <1 32>;
+
+		coresight-name = "coresight-tpda-dl_south";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				tpda_dl_south_1_in_tpdm_sdcc4: endpoint {
+					remote-endpoint =
+					<&tpdm_sdcc4_out_tpda_dl_south_1>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				tpda_dl_south_2_in_tpdm_dl_south: endpoint {
+					remote-endpoint =
+					<&tpdm_dl_south_out_tpda_dl_south_2>;
+				};
+			};
+
+		};
+
+		out-ports {
+
+			port {
+				tpda_dl_south_out_funnel_dl_south: endpoint {
+					remote-endpoint =
+					<&funnel_dl_south_in_tpda_dl_south>;
+				};
+			};
+
+		};
+	};
+
+	funnel_dl_south: funnel@109c2000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x109c2000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-dl_south";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				funnel_dl_south_in_tpda_dl_south: endpoint {
+					remote-endpoint =
+					<&tpda_dl_south_out_funnel_dl_south>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_dl_south_out_funnel_in1: endpoint {
+					remote-endpoint =
+					<&funnel_in1_in_funnel_dl_south>;
+				};
+			};
+
+		};
+	};
+
+	tpda_tmess: tpda@10cc7000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+
+		reg = <0x10cc7000 0x1000>;
+		reg-names = "tpda-base";
+
+		qcom,cmb-elem-size = <0 32>,
+				     <1 32>,
+				     <2 32>;
+
+		qcom,tpda-atid = <85>;
+
+		status = "disabled";
+		coresight-name = "coresight-tpda-tmess";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				tpda_tmess_1_in_tpdm_tmess_0: endpoint {
+					remote-endpoint =
+					<&tpdm_tmess_0_out_tpda_tmess_1>;
+				};
+			};
+
+			port@0 {
+				reg = <0>;
+				tpda_tmess_0_in_tpdm_tmess_prng: endpoint {
+					remote-endpoint =
+					<&tpdm_tmess_prng_out_tpda_tmess_0>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				tpda_tmess_2_in_tpdm_tmess_1: endpoint {
+					remote-endpoint =
+					<&tpdm_tmess_1_out_tpda_tmess_2>;
+				};
+			};
+
+		};
+
+		out-ports {
+
+			port {
+				tpda_tmess_out_funnel_tmess: endpoint {
+					remote-endpoint =
+					<&funnel_tmess_in_tpda_tmess>;
+				};
+			};
+
+		};
+	};
+
+	funnel_tmess: funnel@10cc8000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10cc8000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-tmess";
+
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				funnel_tmess_in_tpda_tmess: endpoint {
+					remote-endpoint =
+					<&tpda_tmess_out_funnel_tmess>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_tmess_out_funnel_dl_north: endpoint {
+					remote-endpoint =
+					<&funnel_dl_north_in_funnel_tmess>;
+				};
+			};
+
+		};
+	};
+
+	tpda_dl_north: tpda@10ac1000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+
+		reg = <0x10ac1000 0x1000>;
+		reg-names = "tpda-base";
+
+		qcom,tpda-atid = <97>;
+		qcom,dsb-elem-size = <2 32>;
+		qcom,cmb-elem-size = <1 32>;
+
+		coresight-name = "coresight-tpda-dl_north";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				tpda_dl_north_1_in_tpdm_sdcc2: endpoint {
+					remote-endpoint =
+					<&tpdm_sdcc2_out_tpda_dl_north_1>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				tpda_dl_north_2_in_tpdm_dl_north: endpoint {
+					remote-endpoint =
+					<&tpdm_dl_north_out_tpda_dl_north_2>;
+				};
+			};
+
+		};
+
+		out-ports {
+
+			port {
+				tpda_dl_north_out_funnel_dl_north: endpoint {
+					remote-endpoint =
+					<&funnel_dl_north_in_tpda_dl_north>;
+				};
+			};
+
+		};
+	};
+
+	funnel_dl_north: funnel@10ac2000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10ac2000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-dl_north";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_dl_north_in_tpda_dl_north: endpoint {
+					remote-endpoint =
+					<&tpda_dl_north_out_funnel_dl_north>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				funnel_dl_north_in_funnel_spss: endpoint {
+					remote-endpoint =
+					<&funnel_spss_out_funnel_dl_north>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				funnel_dl_north_in_funnel_tmess: endpoint {
+					remote-endpoint =
+					<&funnel_tmess_out_funnel_dl_north>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_dl_north_out_funnel_in1: endpoint {
+					remote-endpoint =
+					<&funnel_in1_in_funnel_dl_north>;
+				};
+			};
+
+		};
+	};
+
+	tpda_modem: tpda@10803000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+
+		reg = <0x10803000 0x1000>;
+		reg-names = "tpda-base";
+		qcom,tpda-atid = <67>;
+
+		qcom,dsb-elem-size = <0 32>;
+		qcom,cmb-elem-size = <0 64>;
+
+		coresight-name = "coresight-tpda-modem";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tpda_modem_0_in_tpdm_modem_0: endpoint {
+					remote-endpoint =
+					<&tpdm_modem_0_out_tpda_modem_0>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				tpda_modem_1_in_tpdm_modem_1: endpoint {
+					remote-endpoint =
+					<&tpdm_modem_1_out_tpda_modem_1>;
+				};
+			};
+
+		};
+
+		out-ports {
+
+			port {
+				tpda_modem_out_funnel_modem: endpoint {
+					remote-endpoint =
+					<&funnel_modem_in_tpda_modem>;
+				};
+			};
+
+		};
+	};
+
+	funnel_modem_q6_dup: funnel@1080d000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x1080d000 0x1000>,
+			<0x1080c000 0x1000>;
+		reg-names = "funnel-base-dummy", "funnel-base-real";
+
+		coresight-name = "coresight-funnel-modem_q6_dup";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		qcom,duplicate-funnel;
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_modem_q6_dup_in_modem_etm0: endpoint {
+					remote-endpoint =
+					<&modem_etm0_out_funnel_modem_q6_dup>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_modem_q6_dup_out_funnel_modem_q6: endpoint {
+					remote-endpoint =
+					<&funnel_modem_q6_in_funnel_modem_q6_dup>;
+				};
+			};
+
+		};
+	};
+
+	funnel_modem_q6: funnel@1080c000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x1080c000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-modem_q6";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				funnel_modem_q6_in_funnel_modem_q6_dup: endpoint {
+					remote-endpoint =
+					<&funnel_modem_q6_dup_out_funnel_modem_q6>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				funnel_modem_q6_in_modem_diag: endpoint {
+					remote-endpoint =
+					<&modem_diag_out_funnel_modem_q6>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_modem_q6_out_funnel_modem: endpoint {
+					remote-endpoint =
+					<&funnel_modem_in_funnel_modem_q6>;
+				};
+			};
+
+		};
+	};
+
+	funnel_modem: funnel@10804000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10804000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-modem";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				funnel_modem_in_modem2_etm0: endpoint {
+					remote-endpoint =
+					<&modem2_etm0_out_funnel_modem>;
+				};
+			};
+
+			port@0 {
+				reg = <0>;
+				funnel_modem_in_tpda_modem: endpoint {
+					remote-endpoint =
+					<&tpda_modem_out_funnel_modem>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				funnel_modem_in_funnel_modem_q6: endpoint {
+					remote-endpoint =
+					<&funnel_modem_q6_out_funnel_modem>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_modem_out_funnel_in1: endpoint {
+					remote-endpoint =
+					<&funnel_in1_in_funnel_modem>;
+				};
+			};
+
+		};
+	};
+
+	tpda_apss: tpda@13863000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+
+		reg = <0x13863000 0x1000>;
+		reg-names = "tpda-base";
+
+		qcom,tpda-atid = <66>;
+
+		qcom,dsb-elem-size = <2 32>,
+					<4 32>;
+		qcom,cmb-elem-size = <0 32>,
+				     <1 32>,
+				     <3 64>;
+
+		coresight-name = "coresight-tpda-apss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tpda_apss_0_in_tpdm_llm_silver: endpoint {
+					remote-endpoint =
+					<&tpdm_llm_silver_out_tpda_apss_0>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				tpda_apss_1_in_tpdm_llm_gold: endpoint {
+					remote-endpoint =
+					<&tpdm_llm_gold_out_tpda_apss_1>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				tpda_apss_3_in_tpdm_apss0: endpoint {
+					remote-endpoint =
+					<&tpdm_apss0_out_tpda_apss_3>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				tpda_apss_2_in_tpdm_apss_llm: endpoint {
+					remote-endpoint =
+					<&tpdm_apss_llm_out_tpda_apss_2>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				tpda_apss_4_in_tpdm_apps1: endpoint {
+					remote-endpoint =
+					<&tpdm_apps1_out_tpda_apss_4>;
+				};
+			};
+
+		};
+
+		out-ports {
+
+			port {
+				tpda_apss_out_funnel_apss: endpoint {
+					remote-endpoint =
+					<&funnel_apss_in_tpda_apss>;
+				};
+			};
+
+		};
+	};
+
+	funnel_apss: funnel@13810000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x13810000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-apss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@2 {
+				reg = <2>;
+				funnel_apss_in_tpda_apss: endpoint {
+					remote-endpoint =
+					<&tpda_apss_out_funnel_apss>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_apss_out_funnel_in1: endpoint {
+					remote-endpoint =
+					<&funnel_in1_in_funnel_apss>;
+				};
+			};
+
+		};
+	};
+
+	tpda_dl_center: tpda@10c2e000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+
+		reg = <0x10c2e000 0x1000>;
+		reg-names = "tpda-base";
+
+		qcom,tpda-atid = <78>;
+
+		qcom,dsb-elem-size = <5 32>,
+							 <6 32>,
+							 <7 32>,
+							 <9 32>,
+							 <10 32>,
+							 <12 32>,
+							 <15 32>,
+							 <17 32>,
+							 <20 32>,
+							 <21 32>,
+							 <25 32>,
+							 <26 32>;
+
+		qcom,cmb-elem-size = <7 32>,
+							 <8 32>,
+							 <10 32>,
+							 <13 32>,
+							 <14 64>,
+							 <16 32>,
+							 <19 64>,
+							 <22 32>,
+							 <23 32>,
+							 <25 64>,
+							 <27 64>;
+
+		coresight-name = "coresight-tpda-dl_center";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@a {
+				reg = <10>;
+				tpda_dl_center_10_in_funnel_dl_west: endpoint {
+					remote-endpoint =
+					<&funnel_dl_west_out_tpda_dl_center_10>;
+				};
+			};
+
+			port@d {
+				reg = <13>;
+				tpda_dl_center_13_in_funnel_dl_west: endpoint {
+					remote-endpoint =
+					<&funnel_dl_west_out_tpda_dl_center_13>;
+				};
+			};
+
+			port@c {
+				reg = <12>;
+				tpda_dl_center_12_in_funnel_dl_west: endpoint {
+					remote-endpoint =
+					<&funnel_dl_west_out_tpda_dl_center_12>;
+				};
+			};
+
+			port@f {
+				reg = <15>;
+				tpda_dl_center_15_in_funnel_turing: endpoint {
+					remote-endpoint =
+					<&funnel_turing_out_tpda_dl_center_15>;
+				};
+			};
+
+			port@e {
+				reg = <14>;
+				tpda_dl_center_14_in_funnel_dl_west: endpoint {
+					remote-endpoint =
+					<&funnel_dl_west_out_tpda_dl_center_14>;
+				};
+			};
+
+			port@11 {
+				reg = <17>;
+				tpda_dl_center_17_in_funnel_gfx_dl: endpoint {
+					remote-endpoint =
+					<&funnel_gfx_dl_out_tpda_dl_center_17>;
+				};
+			};
+
+			port@10 {
+				reg = <16>;
+				tpda_dl_center_16_in_funnel_turing: endpoint {
+					remote-endpoint =
+					<&funnel_turing_out_tpda_dl_center_16>;
+				};
+			};
+
+			port@13 {
+				reg = <19>;
+				tpda_dl_center_19_in_tpdm_prng: endpoint {
+					remote-endpoint =
+					<&tpdm_prng_out_tpda_dl_center_19>;
+				};
+			};
+
+			port@17 {
+				reg = <23>;
+				tpda_dl_center_23_in_tpdm_ipa: endpoint {
+					remote-endpoint =
+					<&tpdm_ipa_out_tpda_dl_center_23>;
+				};
+			};
+
+			port@16 {
+				reg = <22>;
+				tpda_dl_center_22_in_tpdm_vsense: endpoint {
+					remote-endpoint =
+					<&tpdm_vsense_out_tpda_dl_center_22>;
+				};
+			};
+
+			port@1a {
+				reg = <26>;
+				tpda_dl_center_26_in_tpdm_dlct: endpoint {
+					remote-endpoint =
+					<&tpdm_dlct_out_tpda_dl_center_26>;
+				};
+			};
+
+			port@14 {
+				reg = <20>;
+				tpda_dl_center_20_in_tpdm_qm: endpoint {
+					remote-endpoint =
+					<&tpdm_qm_out_tpda_dl_center_20>;
+				};
+			};
+
+			port@1b {
+				reg = <27>;
+				tpda_dl_center_27_in_tpdm_ipcc: endpoint {
+					remote-endpoint =
+					<&tpdm_ipcc_out_tpda_dl_center_27>;
+				};
+			};
+
+			port@5 {
+				reg = <5>;
+				tpda_dl_center_5_in_funnel_ddr_dl0: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_dl0_out_tpda_dl_center_5>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				tpda_dl_center_4_in_funnel_lpass: endpoint {
+					remote-endpoint =
+					<&funnel_lpass_out_tpda_dl_center_4>;
+				};
+			};
+
+			port@7 {
+				reg = <7>;
+				tpda_dl_center_7_in_funnel_ddr_dl0: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_dl0_out_tpda_dl_center_7>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				tpda_dl_center_6_in_funnel_ddr_dl0: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_dl0_out_tpda_dl_center_6>;
+				};
+			};
+
+			port@9 {
+				reg = <9>;
+				tpda_dl_center_9_in_funnel_dl_west: endpoint {
+					remote-endpoint =
+					<&funnel_dl_west_out_tpda_dl_center_9>;
+				};
+			};
+
+			port@8 {
+				reg = <8>;
+				tpda_dl_center_8_in_funnel_ddr_dl0: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_dl0_out_tpda_dl_center_8>;
+				};
+			};
+
+			port@19 {
+				reg = <25>;
+				tpda_dl_center_25_in_tpdm_pimem: endpoint {
+					remote-endpoint =
+					<&tpdm_pimem_out_tpda_dl_center_25>;
+				};
+			};
+
+			port@15 {
+				reg = <21>;
+				tpda_dl_center_21_in_tpdm_gcc: endpoint {
+					remote-endpoint =
+					<&tpdm_gcc_out_tpda_dl_center_21>;
+				};
+			};
+
+		};
+
+		out-ports {
+
+			port {
+				tpda_dl_center_out_funnel_dl_center: endpoint {
+					remote-endpoint =
+					<&funnel_dl_center_in_tpda_dl_center>;
+				};
+			};
+
+		};
+	};
+
+	funnel_dl_center: funnel@10c2f000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10c2f000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-dl_center";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_dl_center_in_tpda_dl_center: endpoint {
+					remote-endpoint =
+					<&tpda_dl_center_out_funnel_dl_center>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				funnel_dl_center_in_funnel_ddr_dl0: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_dl0_out_funnel_dl_center>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				funnel_dl_center_in_funnel_turing: endpoint {
+					remote-endpoint =
+					<&funnel_turing_out_funnel_dl_center>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_dl_center_out_funnel_in1: endpoint {
+					remote-endpoint =
+					<&funnel_in1_in_funnel_dl_center>;
+				};
+			};
+
+		};
+	};
+
+	tpda_qdss: tpda@10004000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+
+		reg = <0x10004000 0x1000>;
+		reg-names = "tpda-base";
+
+		qcom,tpda-atid = <65>;
+		coresight-name = "coresight-tpda-qdss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				tpda_qdss_1_in_tpdm_spdm: endpoint {
+					remote-endpoint =
+					<&tpdm_spdm_out_tpda_qdss_1>;
+				};
+			};
+
+			port@0 {
+				reg = <0>;
+				tpda_qdss_0_in_tpdm_dcc: endpoint {
+					remote-endpoint =
+					<&tpdm_dcc_out_tpda_qdss_0>;
+				};
+			};
+
+		};
+
+		out-ports {
+
+			port {
+				tpda_qdss_out_funnel_in0: endpoint {
+					remote-endpoint =
+					<&funnel_in0_in_tpda_qdss>;
+				};
+			};
+
+		};
+	};
+
+	funnel_in0: funnel@10041000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10041000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-in0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_in0_in_snoc: endpoint {
+					remote-endpoint =
+					<&snoc_out_funnel_in0>;
+				};
+			};
+
+			port@7 {
+				reg = <7>;
+				funnel_in0_in_stm: endpoint {
+					remote-endpoint =
+					<&stm_out_funnel_in0>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				funnel_in0_in_tpda_qdss: endpoint {
+					remote-endpoint =
+					<&tpda_qdss_out_funnel_in0>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_in0_out_funnel_qdss: endpoint {
+					remote-endpoint =
+					<&funnel_qdss_in_funnel_in0>;
+				};
+			};
+
+		};
+	};
+
+	funnel_in1: funnel@10042000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10042000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-in1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_in1_in_funnel_dl_south: endpoint {
+					remote-endpoint =
+					<&funnel_dl_south_out_funnel_in1>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_in1_in_funnel_dl_north: endpoint {
+					remote-endpoint =
+					<&funnel_dl_north_out_funnel_in1>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				funnel_in1_in_funnel_apss: endpoint {
+					remote-endpoint =
+					<&funnel_apss_out_funnel_in1>;
+				};
+			};
+
+			port@5 {
+				reg = <5>;
+				funnel_in1_in_funnel_modem: endpoint {
+					remote-endpoint =
+					<&funnel_modem_out_funnel_in1>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				funnel_in1_in_funnel_dl_center: endpoint {
+					remote-endpoint =
+					<&funnel_dl_center_out_funnel_in1>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_in1_out_funnel_qdss: endpoint {
+					remote-endpoint =
+					<&funnel_qdss_in_funnel_in1>;
+				};
+			};
+
+		};
+	};
+
+	funnel_qdss: funnel@10045000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10045000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-qdss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				funnel_qdss_in_funnel_in1: endpoint {
+					remote-endpoint =
+					<&funnel_in1_out_funnel_qdss>;
+				};
+			};
+
+			port@0 {
+				reg = <0>;
+				funnel_qdss_in_funnel_in0: endpoint {
+					remote-endpoint =
+					<&funnel_in0_out_funnel_qdss>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_qdss_out_funnel_aoss: endpoint {
+					remote-endpoint =
+					<&funnel_aoss_in_funnel_qdss>;
+				};
+			};
+
+		};
+	};
+
+	tpda_aoss: tpda@10b08000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+
+		reg = <0x10b08000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-aoss";
+
+		qcom,tpda-atid = <71>;
+
+		qcom,cmb-elem-size = <0 64>,
+				     <1 64>,
+				     <2 64>,
+				     <3 64>;
+
+		qcom,dsb-elem-size = <4 32>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tpda_aoss_0_in_tpdm_swao_prio_0: endpoint {
+					remote-endpoint =
+					<&tpdm_swao_prio_0_out_tpda_aoss_0>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				tpda_aoss_1_in_tpdm_swao_prio_1: endpoint {
+					remote-endpoint =
+					<&tpdm_swao_prio_1_out_tpda_aoss_1>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				tpda_aoss_2_in_tpdm_swao_prio_2: endpoint {
+					remote-endpoint =
+					<&tpdm_swao_prio_2_out_tpda_aoss_2>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				tpda_aoss_3_in_tpdm_swao_prio_3: endpoint {
+					remote-endpoint =
+					<&tpdm_swao_prio_3_out_tpda_aoss_3>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				tpda_aoss_4_in_tpdm_swao: endpoint {
+					remote-endpoint =
+					<&tpdm_swao_out_tpda_aoss_4>;
+				};
+			};
+
+		};
+
+		out-ports {
+
+			port {
+				tpda_aoss_out_funnel_aoss: endpoint {
+					remote-endpoint =
+					<&funnel_aoss_in_tpda_aoss>;
+				};
+			};
+
+		};
+	};
+
+	funnel_aoss: funnel@10b04000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x10b04000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-aoss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@3 {
+				reg = <3>;
+				funnel_aoss_in_funnel_ssc: endpoint {
+					remote-endpoint =
+					<&funnel_ssc_out_funnel_aoss>;
+				};
+			};
+
+			port@5 {
+				reg = <5>;
+				funnel_aoss_in_funnel_lpass_lpi: endpoint {
+					remote-endpoint =
+					<&funnel_lpass_lpi_out_funnel_aoss>;
+				};
+			};
+
+			port@7 {
+				reg = <7>;
+				funnel_aoss_in_funnel_qdss: endpoint {
+					remote-endpoint =
+					<&funnel_qdss_out_funnel_aoss>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				funnel_aoss_in_tpda_aoss: endpoint {
+					remote-endpoint =
+					<&tpda_aoss_out_funnel_aoss>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_aoss_out_tmc_etf: endpoint {
+					remote-endpoint =
+					<&tmc_etf_in_funnel_aoss>;
+				};
+			};
+
+		};
+	};
+
+	dummy_eud: dummy_sink {
+		compatible = "qcom,coresight-dummy";
+
+		coresight-name = "coresight-eud";
+
+		qcom,dummy-sink;
+		in-ports {
+			port {
+				eud_in_replicator_swao: endpoint {
+					remote-endpoint =
+						<&replicator_swao_out_eud>;
+				};
+			};
+		};
+	};
+
+	tmc_etf: tmc@10b05000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb961>;
+		reg = <0x10b05000 0x1000>;
+		reg-names = "tmc-base";
+
+		coresight-name = "coresight-tmc-etf";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				tmc_etf_in_funnel_aoss: endpoint {
+					remote-endpoint =
+					<&funnel_aoss_out_tmc_etf>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				tmc_etf_out_replicator_swao: endpoint {
+					remote-endpoint =
+					<&replicator_swao_in_tmc_etf>;
+				};
+			};
+		};
+	};
+
+	replicator_swao: replicator@10b06000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb909>;
+		reg = <0x10b06000 0x1000>;
+		reg-names = "replicator-base";
+
+		coresight-name = "coresight-replicator_swao";
+
+		qcom,replicator-loses-context;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				replicator_swao_in_tmc_etf: endpoint {
+					remote-endpoint =
+					<&tmc_etf_out_replicator_swao>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				replicator_swao_out_replicator_qdss: endpoint {
+					remote-endpoint =
+					<&replicator_qdss_in_replicator_swao>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				replicator_swao_out_eud: endpoint {
+					remote-endpoint =
+					  <&eud_in_replicator_swao>;
+				};
+			};
+		};
+	};
+
+	replicator_qdss: replicator@10046000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb909>;
+		reg = <0x10046000 0x1000>;
+		reg-names = "replicator-base";
+
+		coresight-name = "coresight-replicator_qdss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				replicator_qdss_in_replicator_swao: endpoint {
+					remote-endpoint =
+					<&replicator_swao_out_replicator_qdss>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				replicator_qdss_out_replicator_etr: endpoint {
+					remote-endpoint =
+					<&replicator_etr_in_replicator_qdss>;
+				};
+			};
+		};
+	};
+
+	replicator_etr: replicator@1004e000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb909>;
+		reg = <0x1004e000 0x1000>;
+		reg-names = "replicator-base";
+
+		coresight-name = "coresight-replicator_etr";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				replicator_etr_in_replicator_qdss: endpoint {
+					remote-endpoint =
+					<&replicator_qdss_out_replicator_etr>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				replicator_etr_out_tmc_etr: endpoint {
+					remote-endpoint =
+					<&tmc_etr_in_replicator_etr>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				replicator_etr_out_tmc_etr1: endpoint {
+					remote-endpoint =
+					<&tmc_etr1_in_replicator_etr>;
+				};
+			};
+		};
+	};
+
+	tmc_etr: tmc@10048000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb961>;
+		reg = <0x10048000 0x1000>,
+			<0x10064000 0x16000>;
+		reg-names = "tmc-base", "bam-base";
+
+		qcom,iommu-dma = "bypass";
+		iommus = <&apps_smmu 0x0600 0>,
+			<&apps_smmu 0x0520 0>;
+
+		qcom,iommu-dma-addr-pool = <0x0 0xffc00000>;
+
+		qcom,sw-usb;
+		dma-coherent;
+		coresight-name = "coresight-tmc-etr";
+
+		coresight-csr = <&csr>;
+		csr-atid-offset = <0xf4>;
+		csr-irqctrl-offset = <0x6c>;
+		byte-cntr-name = "byte-cntr";
+		byte-cntr-class-name = "coresight-tmc-etr-stream";
+
+		interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "byte-cntr-irq";
+
+		arm,scatter-gather;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				tmc_etr_in_replicator_etr: endpoint {
+					remote-endpoint =
+					<&replicator_etr_out_tmc_etr>;
+				};
+			};
+		};
+	};
+
+	tmc_etr1: tmc@1004f000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb961>;
+		reg = <0x1004f000 0x1000>;
+		reg-names = "tmc-base";
+
+		coresight-name = "coresight-tmc-etr1";
+
+		iommus = <&apps_smmu 0x0620 0>;
+		qcom,iommu-dma-addr-pool = <0x0 0xffc00000>;
+
+		coresight-csr = <&csr>;
+		csr-atid-offset = <0x104>;
+		csr-irqctrl-offset = <0x70>;
+		byte-cntr-name = "byte-cntr1";
+		byte-cntr-class-name = "coresight-tmc-etr1-stream";
+
+		interrupts = <GIC_SPI 269 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "byte-cntr-irq";
+
+		arm,scatter-gather;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				tmc_etr1_in_replicator_etr: endpoint {
+					remote-endpoint =
+					<&replicator_etr_out_tmc_etr1>;
+				};
+			};
+		};
+	};
+
+	csr: csr@10001000 {
+		compatible = "qcom,coresight-csr";
+		reg = <0x10001000 0x1000>;
+		reg-names = "csr-base";
+
+		coresight-name = "coresight-csr";
+		qcom,usb-bam-support;
+		qcom,hwctrl-set-support;
+		qcom,set-byte-cntr-support;
+
+		qcom,blk-size = <1>;
+	};
+
+	swao_csr: csr@10b11000 {
+		compatible = "qcom,coresight-csr";
+		reg = <0x10b11000 0x1000>,
+		      <0x10b110f8 0x50>;
+		reg-names = "csr-base", "msr-base";
+
+		coresight-name = "coresight-swao-csr";
+		qcom,timestamp-support;
+		qcom,msr-support;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,blk-size = <1>;
+	};
+
+	qc_cti: cti@10010000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10010000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-qc_cti";
+
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti0: cti@10c2a000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10c2a000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-cti0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti1: cti@10c2b000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10c2b000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-cti1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	dlmm_cti0: cti@10c09000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10c09000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-dlmm_cti0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	dlmm_cti1: cti@10c0a000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10c0a000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-dlmm_cti1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	ddr_dl_0_cti_0: cti@10d02000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10d02000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-ddr_dl_0_cti_0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	ddr_dl_0_cti_1: cti@10d03000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10d03000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-ddr_dl_0_cti_1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	ddr_dl_0_cti_2: cti@10d04000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10d04000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-ddr_dl_0_cti_2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	ddr_dl_1_cti_0: cti@10d0c000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10d0c000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-ddr_dl_1_cti_0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	ddr_dl_1_cti_1: cti@10d0d000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10d0d000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-ddr_dl_1_cti_1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	ddr_dl_1_cti_2: cti@10d0e000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10d0e000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-ddr_dl_1_cti_2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	ddr_ch02_dl_cti_0: cti@10d21000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10d21000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-ddr_ch02_dl_cti_0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	ddr_ch13_dl_cti_0: cti@10d31000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10d31000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-ddr_ch13_dl_cti_0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	lpass_dl_cti: cti@10845000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10845000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-lpass_dl_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	gpu_isdb_cti: cti@10961000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10961000 0x1000>;
+
+		status = "disabled";
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-gpu_isdb_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	gpu_cortex_m3: cti@10962000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10962000 0x1000>;
+
+		status = "disabled";
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-gpu_cortex_m3";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	iris_dl_cti: cti@10831000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10831000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-iris_dl_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	mdss_dl_cti: cti@10c61000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10c61000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-mdss_dl_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	turing_dl_cti_0: cti@10982000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10982000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-turing_dl_cti_0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	turing_dl_cti_2: cti@10984000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10984000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-turing_dl_cti_2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	turing_q6_cti: cti@1098b000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x1098b000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-turing_q6_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	swao_cti: cti@10b00000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10b00000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-swao_cti";
+
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	ssc_cti_noc: cti@10b2e000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10b2e000 0x1000>;
+
+		status = "disabled";
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-ssc_cti_noc";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+
+	ssc_cti0_q6: cti@10b2b000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10b2b000 0x1000>;
+
+		status = "disabled";
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-ssc_cti0_q6";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	ssc_cti1: cti@10b21000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10b21000 0x1000>;
+
+		status = "disabled";
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-ssc_cti1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	ssc_cortex_m3: cti@10b20000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10b20000 0x1000>;
+
+		status = "disabled";
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-ssc_cortex_m3";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cortex_m3: cti@10b13000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10b13000 0x1000>;
+
+		status = "disabled";
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-cortex_m3";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	lpass_lpi_cti: cti@10b41000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10b41000 0x1000>;
+
+		status = "disabled";
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-lpass_lpi_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	lpass_q6_cti: cti@10b4b000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10b4b000 0x1000>;
+
+		status = "disabled";
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-lpass_q6_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	apss_cti0: cti@138e0000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x138e0000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-apss_cti0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	apss_cti1: cti@138f0000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x138f0000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-apss_cti1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	apss_cti2: cti@13900000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x13900000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-apss_cti2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	riscv_cti: cti@1382b000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x1382b000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-riscv_cti";
+
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	mss_q6_cti: cti@1080b000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x1080b000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-mss_q6_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	mss_vq6_cti: cti@10813000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10813000 0x1000>;
+
+		status = "disabled";
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-mss_vq6_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	tmess_cti_0: cti@10cc2000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10cc2000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-tmess_cti_0";
+
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	tmess_cti_1: cti@10cc3000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10cc3000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-tmess_cti_1";
+
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	tmess_cti_2: cti@10cc4000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10cc4000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-tmess_cti_2";
+
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+
+	tmess_cti_3: cti@10cc5000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10cc5000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-tmess_cti_3";
+
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	tmess_cti_4: cti@10cc6000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10cc6000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-tmess_cti_4";
+
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	tmess_cpu: cti@10cd1000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10cd1000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-tmess_cpu";
+
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	modem_tp_cti: cti@10802000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10802000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-modem_tp_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	apss_atb_cti: cti@13862000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x13862000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-apss_atb_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	ddrss_shrm2: cti@10d11000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10d11000 0x1000>;
+
+		status = "disabled";
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-ddrss_shrm2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	sp_sc300: cti@10884000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10884000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-sp_sc300";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	spss_cti: cti@10881000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10881000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-spss_cti";
+
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cpu0: cti@12010000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x12010000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-cpu0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cpu1: cti@12020000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x12020000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-cpu1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cpu2: cti@12030000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x12030000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-cpu2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cpu3: cti@12040000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x12040000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-cpu3";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cpu4: cti@12050000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x12050000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-cpu4";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cpu5: cti@112060000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x12060000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-cpu5";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cpu6: cti@12070000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x12070000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-cpu6";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cpu7: cti@12080000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x12080000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-cpu7";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	ipcb_tgu: tgu@10b0e000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb999>;
+		reg = <0x10b0e000 0x1000>;
+		reg-names = "tgu-base";
+		tgu-steps = <3>;
+		tgu-conditions = <4>;
+		tgu-regs = <4>;
+		tgu-timer-counters = <8>;
+
+		coresight-name = "coresight-tgu-ipcb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+};
diff --git a/qcom/waipio-debug.dtsi b/qcom/waipio-debug.dtsi
new file mode 100644
index 00000000..2fe71b81
--- /dev/null
+++ b/qcom/waipio-debug.dtsi
@@ -0,0 +1,2783 @@
+#include <dt-bindings/soc/qcom,dcc_v2.h>
+
+&reserved_memory {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	ranges;
+
+	dump_mem: mem_dump_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0 0x3400000>;
+	};
+};
+
+&soc {
+	dcc: dcc_v2@100ff000 {
+		compatible = "qcom,dcc-v2";
+		reg = <0x100ff000 0x1000>,
+		      <0x10080000 0x18000>;
+
+		qcom,transaction_timeout = <0>;
+
+		reg-names = "dcc-base", "dcc-ram-base";
+		dcc-ram-offset = <0>;
+
+		link_list_0 {
+			qcom,curr-link-list = <6>;
+			qcom,data-sink = "sram";
+			qcom,link-list = <DCC_READ 0x1780005c 1 0>,
+				<DCC_READ 0x1781005c 1 0>,
+				<DCC_READ 0x1782005c 1 0>,
+				<DCC_READ 0x1783005c 1 0>,
+				<DCC_READ 0x1784005c 1 0>,
+				<DCC_READ 0x1785005c 1 0>,
+				<DCC_READ 0x1786005c 1 0>,
+				<DCC_READ 0x1787005c 1 0>,
+				<DCC_READ 0x1740003c 1 0>,
+				<DCC_READ 0x17600238 1 0>,
+				<DCC_READ 0x17600240 11 0>,
+				<DCC_READ 0x17600404 3 0>,
+				<DCC_READ 0x1760041c 3 0>,
+				<DCC_READ 0x17600434 1 0>,
+				<DCC_READ 0x1760043c 1 0>,
+				<DCC_READ 0x17600440 1 0>,
+				<DCC_READ 0x17400438 1 0>,
+				<DCC_READ 0x17600044 1 0>,
+				<DCC_READ 0x17600500 1 0>,
+				<DCC_READ 0x17600504 5 0>,
+				<DCC_READ 0x17900908 1 0>,
+				<DCC_READ 0x17900c18 1 0>,
+				<DCC_READ 0x17901908 1 0>,
+				<DCC_READ 0x17901c18 1 0>,
+				<DCC_READ 0x17b90810 1 0>,
+				<DCC_READ 0x17b90c50 1 0>,
+				<DCC_READ 0x17b90814 1 0>,
+				<DCC_READ 0x17b90c54 1 0>,
+				<DCC_READ 0x17b90818 1 0>,
+				<DCC_READ 0x17b90c58 1 0>,
+				<DCC_READ 0x17b93a84 2 0>,
+				<DCC_READ 0x17ba0810 1 0>,
+				<DCC_READ 0x17ba0c50 1 0>,
+				<DCC_READ 0x17ba0814 1 0>,
+				<DCC_READ 0x17ba0c54 1 0>,
+				<DCC_READ 0x17ba0818 1 0>,
+				<DCC_READ 0x17ba0c58 1 0>,
+				<DCC_READ 0x17ba3a84 2 0>,
+				<DCC_READ 0x17b93500 80 0>,
+				<DCC_READ 0x17ba3500 80 0>,
+				<DCC_READ 0x17a80000 5 0>,
+				<DCC_READ 0x17a8002c 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_READ 0x17a82000 5 0>,
+				<DCC_READ 0x17a8202c 1 0>,
+				<DCC_READ 0x17a82038 1 0>,
+				<DCC_READ 0x17a84000 5 0>,
+				<DCC_READ 0x17a8402c 1 0>,
+				<DCC_READ 0x17a84038 1 0>,
+				<DCC_READ 0x17a86000 5 0>,
+				<DCC_READ 0x17a8602c 1 0>,
+				<DCC_READ 0x17a86038 1 0>,
+				<DCC_READ 0x17aa0000 44 0>,
+				<DCC_READ 0x17aa00fc 16 0>,
+				<DCC_READ 0x17aa0200 2 0>,
+				<DCC_READ 0x17aa0300 1 0>,
+				<DCC_READ 0x17aa0400 1 0>,
+				<DCC_READ 0x17aa0500 1 0>,
+				<DCC_READ 0x17aa0600 1 0>,
+				<DCC_READ 0x17aa0700 5 0>,
+				<DCC_WRITE 0x17a80000 0xf 0>,
+				<DCC_READ 0x17a80000 1 0>,
+				<DCC_WRITE 0x17a80024 0x0 0>,
+				<DCC_READ 0x17a80024 1 0>,
+				<DCC_WRITE 0x17a80020 0x0 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_WRITE 0x17a80020 0x400 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_WRITE 0x17a80020 0x800 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_WRITE 0x17a80020 0xc00 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_WRITE 0x17a80020 0x1000 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_WRITE 0x17a80020 0x1400 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_WRITE 0x17a80020 0x1800 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_WRITE 0x17a80020 0x1c00 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_WRITE 0x17a80020 0x2000 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_WRITE 0x17a80020 0x2400 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_WRITE 0x17a80020 0x2800 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_WRITE 0x17a80020 0x2c00 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_WRITE 0x17a80020 0x3000 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_WRITE 0x17a80020 0x3400 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_WRITE 0x17a80020 0x3800 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_WRITE 0x17a80020 0x3c00 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_WRITE 0x17a80024 0x40000 0>,
+				<DCC_READ 0x17a80024 1 0>,
+				<DCC_WRITE 0x17a80020 0x0 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_WRITE 0x17a80020 0x400 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_WRITE 0x17a80020 0x8000 0>,
+				<DCC_READ 0x17a80020 1 0>,
+				<DCC_LOOP 32 0 0>,
+				<DCC_READ 0x17a80038 1 0>,
+				<DCC_LOOP 1 0 0>,
+				<DCC_WRITE 0x17a82000 0xf 0>,
+				<DCC_READ 0x17a82000 1 0>,
+				<DCC_WRITE 0x17a82024 0x0 0>,
+				<DCC_READ 0x17a82024 1 0>,
+				<DCC_WRITE 0x17a82020 0x0 0>,
+				<DCC_READ 0x17a82020 1 0>,
+				<DCC_READ 0x17a82038 1 0>,
+				<DCC_WRITE 0x17a82020 0x400 0>,
+				<DCC_READ 0x17a82020 1 0>,
+				<DCC_READ 0x17a82038 1 0>,
+				<DCC_WRITE 0x17a82020 0x800 0>,
+				<DCC_READ 0x17a82020 1 0>,
+				<DCC_READ 0x17a82038 1 0>,
+				<DCC_WRITE 0x17a82020 0xc00 0>,
+				<DCC_READ 0x17a82020 1 0>,
+				<DCC_READ 0x17a82038 1 0>,
+				<DCC_WRITE 0x17a82020 0x1000 0>,
+				<DCC_READ 0x17a82020 1 0>,
+				<DCC_READ 0x17a82038 1 0>,
+				<DCC_WRITE 0x17a82020 0x1400 0>,
+				<DCC_READ 0x17a82020 1 0>,
+				<DCC_READ 0x17a82038 1 0>,
+				<DCC_WRITE 0x17a82020 0x1800 0>,
+				<DCC_READ 0x17a82020 1 0>,
+				<DCC_READ 0x17a82038 1 0>,
+				<DCC_WRITE 0x17a82020 0x1c00 0>,
+				<DCC_READ 0x17a82020 1 0>,
+				<DCC_READ 0x17a82038 1 0>,
+				<DCC_WRITE 0x17a82020 0x2000 0>,
+				<DCC_READ 0x17a82020 1 0>,
+				<DCC_READ 0x17a82038 1 0>,
+				<DCC_WRITE 0x17a82020 0x2400 0>,
+				<DCC_READ 0x17a82020 1 0>,
+				<DCC_READ 0x17a82038 1 0>,
+				<DCC_WRITE 0x17a82020 0x2800 0>,
+				<DCC_READ 0x17a82020 1 0>,
+				<DCC_READ 0x17a82038 1 0>,
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+				<DCC_READ 0x19381ea0 1 0>,
+				<DCC_READ 0x19383e64 1 0>,
+				<DCC_READ 0x19383ea0 1 0>,
+				<DCC_READ 0x1938527c 1 0>,
+				<DCC_READ 0x19385290 1 0>,
+				<DCC_READ 0x193854ec 1 0>,
+				<DCC_READ 0x193854f4 1 0>,
+				<DCC_READ 0x19385514 1 0>,
+				<DCC_READ 0x1938551c 1 0>,
+				<DCC_READ 0x19385524 1 0>,
+				<DCC_READ 0x19385548 1 0>,
+				<DCC_READ 0x19385550 1 0>,
+				<DCC_READ 0x19385558 1 0>,
+				<DCC_READ 0x193855b8 1 0>,
+				<DCC_READ 0x193855c0 1 0>,
+				<DCC_READ 0x193855ec 1 0>,
+				<DCC_READ 0x19385870 1 0>,
+				<DCC_READ 0x193858a0 1 0>,
+				<DCC_READ 0x193858a8 1 0>,
+				<DCC_READ 0x193858b0 1 0>,
+				<DCC_READ 0x193858b8 1 0>,
+				<DCC_READ 0x193858d8 1 0>,
+				<DCC_READ 0x193858dc 1 0>,
+				<DCC_READ 0x193858f4 1 0>,
+				<DCC_READ 0x193858fc 1 0>,
+				<DCC_READ 0x19385920 1 0>,
+				<DCC_READ 0x19385928 1 0>,
+				<DCC_READ 0x19385944 1 0>,
+				<DCC_READ 0x19386314 1 0>,
+				<DCC_READ 0x19386454 1 0>,
+				<DCC_READ 0x19386594 1 0>,
+				<DCC_READ 0x19386604 1 0>,
+				<DCC_READ 0x1938660c 1 0>,
+				<DCC_READ 0x19681e64 1 0>,
+				<DCC_READ 0x19681ea0 1 0>,
+				<DCC_READ 0x19683e64 1 0>,
+				<DCC_READ 0x19683ea0 1 0>,
+				<DCC_READ 0x1968527c 1 0>,
+				<DCC_READ 0x19685290 1 0>,
+				<DCC_READ 0x196854ec 1 0>,
+				<DCC_READ 0x196854f4 1 0>,
+				<DCC_READ 0x19685514 1 0>,
+				<DCC_READ 0x1968551c 1 0>,
+				<DCC_READ 0x19685524 1 0>,
+				<DCC_READ 0x19685548 1 0>,
+				<DCC_READ 0x19685550 1 0>,
+				<DCC_READ 0x19685558 1 0>,
+				<DCC_READ 0x196855b8 1 0>,
+				<DCC_READ 0x196855c0 1 0>,
+				<DCC_READ 0x196855ec 1 0>,
+				<DCC_READ 0x19685870 1 0>,
+				<DCC_READ 0x196858a0 1 0>,
+				<DCC_READ 0x196858a8 1 0>,
+				<DCC_READ 0x196858b0 1 0>,
+				<DCC_READ 0x196858b8 1 0>,
+				<DCC_READ 0x196858d8 1 0>,
+				<DCC_READ 0x196858dc 1 0>,
+				<DCC_READ 0x196858f4 1 0>,
+				<DCC_READ 0x196858fc 1 0>,
+				<DCC_READ 0x19685920 1 0>,
+				<DCC_READ 0x19685928 1 0>,
+				<DCC_READ 0x19685944 1 0>,
+				<DCC_READ 0x19686314 1 0>,
+				<DCC_READ 0x19686454 1 0>,
+				<DCC_READ 0x19686594 1 0>,
+				<DCC_READ 0x19686604 1 0>,
+				<DCC_READ 0x1968660c 1 0>,
+				<DCC_READ 0x19781e64 1 0>,
+				<DCC_READ 0x19781ea0 1 0>,
+				<DCC_READ 0x19783e64 1 0>,
+				<DCC_READ 0x19783ea0 1 0>,
+				<DCC_READ 0x1978527c 1 0>,
+				<DCC_READ 0x19785290 1 0>,
+				<DCC_READ 0x197854ec 1 0>,
+				<DCC_READ 0x197854f4 1 0>,
+				<DCC_READ 0x19785514 1 0>,
+				<DCC_READ 0x1978551c 1 0>,
+				<DCC_READ 0x19785524 1 0>,
+				<DCC_READ 0x19785548 1 0>,
+				<DCC_READ 0x19785550 1 0>,
+				<DCC_READ 0x19785558 1 0>,
+				<DCC_READ 0x197855b8 1 0>,
+				<DCC_READ 0x197855c0 1 0>,
+				<DCC_READ 0x197855ec 1 0>,
+				<DCC_READ 0x19785870 1 0>,
+				<DCC_READ 0x197858a0 1 0>,
+				<DCC_READ 0x197858a8 1 0>,
+				<DCC_READ 0x197858b0 1 0>,
+				<DCC_READ 0x197858b8 1 0>,
+				<DCC_READ 0x197858d8 1 0>,
+				<DCC_READ 0x197858dc 1 0>,
+				<DCC_READ 0x197858f4 1 0>,
+				<DCC_READ 0x197858fc 1 0>,
+				<DCC_READ 0x19785920 1 0>,
+				<DCC_READ 0x19785928 1 0>,
+				<DCC_READ 0x19785944 1 0>,
+				<DCC_READ 0x19786314 1 0>,
+				<DCC_READ 0x19786454 1 0>,
+				<DCC_READ 0x19786594 1 0>,
+				<DCC_READ 0x19786604 1 0>,
+				<DCC_READ 0x1978660c 1 0>,
+				<DCC_READ 0x610110 1 0>,
+				<DCC_READ 0x610114 1 0>,
+				<DCC_READ 0x610118 1 0>,
+				<DCC_READ 0x61011c 1 0>,
+				<DCC_READ 0x610120 1 0>,
+				<DCC_READ 0x1908e01c 1 0>,
+				<DCC_READ 0x1908e030 1 0>,
+				<DCC_READ 0x19032020 1 0>,
+				<DCC_READ 0x19032024 1 0>,
+				<DCC_WRITE 0x19030040 0x1 1>,
+				<DCC_WRITE 0x1903005c 0x22c000 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c001 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c002 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c003 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c004 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c005 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c006 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c007 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c008 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c009 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c00a 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c00b 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c00c 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c00d 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c00e 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c00f 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c010 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c011 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c012 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c013 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c014 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c015 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c016 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c017 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c018 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c019 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c01a 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c01b 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c01c 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c01d 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c01e 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c01f 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c300 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c341 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_WRITE 0x1903005c 0x22c7b1 1>,
+				<DCC_READ 0x19030010 1 0>,
+				<DCC_READ 0x32302028 1 0>,
+				<DCC_READ 0x320a4404 1 0>,
+				<DCC_READ 0x320a4408 1 0>,
+				<DCC_READ 0x323b0404 1 0>,
+				<DCC_READ 0x323b0408 1 0>,
+				<DCC_READ 0xb2b1020 1 0>,
+				<DCC_READ 0xb2b1024 1 0>;
+		};
+
+		link_list_1 {
+			qcom,curr-link-list = <4>;
+			qcom,data-sink = "sram";
+			qcom,link-list = <DCC_READ 0x190e0010 1 0>,
+				<DCC_READ 0x190e0020 8 0>,
+				<DCC_READ 0x190e0248 1 0>,
+				<DCC_READ 0x195f0010 1 0>,
+				<DCC_READ 0x195f0020 8 0>,
+				<DCC_READ 0x195f0248 1 0>,
+				<DCC_READ 0x199f0010 1 0>,
+				<DCC_READ 0x199f0020 8 0>,
+				<DCC_READ 0x199f0248 1 0>,
+				<DCC_READ 0x190e5018 1 0>,
+				<DCC_READ 0x190e5008 1 0>,
+				<DCC_LOOP 0x6  0 0>,
+				<DCC_READ 0x190e5010 2 0>,
+				<DCC_LOOP 0x1 0 0>,
+				<DCC_READ 0x195f2018 1 0>,
+				<DCC_READ 0x195f2008 1 0>,
+				<DCC_LOOP 0x3  0 0>,
+				<DCC_READ 0x195f2010 2 0>,
+				<DCC_LOOP 0x1 0 0>,
+				<DCC_READ 0x199f2018 1 0>,
+				<DCC_READ 0x199f2008 1 0>,
+				<DCC_LOOP 0x3  0 0>,
+				<DCC_READ 0x199f2010 2 0>,
+				<DCC_LOOP 0x1 0 0>,
+				<DCC_READ 0x3c40010 1 0>,
+				<DCC_READ 0x3c40020 8 0>,
+				<DCC_READ 0x3c4b048 1 0>,
+				<DCC_READ 0x3c41018 1 0>,
+				<DCC_READ 0x3c41008 1 0>,
+				<DCC_LOOP 0x5  0 0>,
+				<DCC_READ 0x3c41010 2 0>,
+				<DCC_LOOP 0x1 0 0>,
+				<DCC_READ 0x1740008 1 0>,
+				<DCC_READ 0x1740020 8 0>,
+				<DCC_READ 0x174c048 1 0>,
+				<DCC_READ 0x1741018 1 0>,
+				<DCC_READ 0x1741008 1 0>,
+				<DCC_LOOP 0xb  0 0>,
+				<DCC_READ 0x1741010 2 0>,
+				<DCC_LOOP 0x1 0 0>,
+				<DCC_READ 0x1680010 1 0>,
+				<DCC_READ 0x1680020 8 0>,
+				<DCC_READ 0x1681048 1 0>,
+				<DCC_READ 0x1682018 1 0>,
+				<DCC_READ 0x1682008 1 0>,
+				<DCC_LOOP 0x7  0 0>,
+				<DCC_READ 0x1682010 2 0>,
+				<DCC_LOOP 0x1 0 0>,
+				<DCC_READ 0x16e0010 1 0>,
+				<DCC_READ 0x16e0020 8 0>,
+				<DCC_READ 0x16e8048 1 0>,
+				<DCC_READ 0x1700010 1 0>,
+				<DCC_READ 0x1700020 8 0>,
+				<DCC_READ 0x1708048 1 0>,
+				<DCC_READ 0x16c0010 1 0>,
+				<DCC_READ 0x16c0020 8 0>,
+				<DCC_READ 0x16cc048 1 0>,
+				<DCC_READ 0x16e6018 1 0>,
+				<DCC_READ 0x16e6008 1 0>,
+				<DCC_LOOP 0x4  0 0>,
+				<DCC_READ 0x16e6010 2 0>,
+				<DCC_LOOP 0x1 0 0>,
+				<DCC_READ 0x16c2018 1 0>,
+				<DCC_READ 0x16c2008 1 0>,
+				<DCC_LOOP 0x4  0 0>,
+				<DCC_READ 0x16c2010 2 0>,
+				<DCC_LOOP 0x1 0 0>,
+				<DCC_READ 0x1706118 1 0>,
+				<DCC_READ 0x1706108 1 0>,
+				<DCC_LOOP 0x3  0 0>,
+				<DCC_READ 0x1706110 2 0>,
+				<DCC_LOOP 0x1 0 0>,
+				<DCC_READ 0x1706098 1 0>,
+				<DCC_READ 0x1706088 1 0>,
+				<DCC_LOOP 0x3  0 0>,
+				<DCC_READ 0x1706090 2 0>,
+				<DCC_LOOP 0x1 0 0>,
+				<DCC_READ 0x1706018 1 0>,
+				<DCC_READ 0x1706008 1 0>,
+				<DCC_LOOP 0x5  0 0>,
+				<DCC_READ 0x1706010 2 0>,
+				<DCC_LOOP 0x1 0 0>,
+				<DCC_READ 0x1500010 1 0>,
+				<DCC_READ 0x1500020 8 0>,
+				<DCC_READ 0x1500248 2 0>,
+				<DCC_READ 0x1500258 1 0>,
+				<DCC_READ 0x1500448 1 0>,
+				<DCC_READ 0x1510098 1 0>,
+				<DCC_READ 0x1510088 1 0>,
+				<DCC_LOOP 0x2  0 0>,
+				<DCC_READ 0x1510090 2 0>,
+				<DCC_LOOP 0x1 0 0>,
+				<DCC_READ 0x1513018 1 0>,
+				<DCC_READ 0x1513008 1 0>,
+				<DCC_LOOP 0x3  0 0>,
+				<DCC_READ 0x1513010 2 0>,
+				<DCC_LOOP 0x1 0 0>,
+				<DCC_READ 0x1512018 1 0>,
+				<DCC_READ 0x1512008 1 0>,
+				<DCC_LOOP 0x4  0 0>,
+				<DCC_READ 0x1512010 2 0>,
+				<DCC_LOOP 0x1 0 0>,
+				<DCC_READ 0x1511018 1 0>,
+				<DCC_READ 0x1511008 1 0>,
+				<DCC_LOOP 0x2  0 0>,
+				<DCC_READ 0x1511010 2 0>,
+				<DCC_LOOP 0x1 0 0>,
+				<DCC_READ 0x1514018 1 0>,
+				<DCC_READ 0x1514008 1 0>,
+				<DCC_LOOP 0x3  0 0>,
+				<DCC_READ 0x1514010 2 0>,
+				<DCC_LOOP 0x1 0 0>,
+				<DCC_READ 0x1510018 1 0>,
+				<DCC_READ 0x1510008 1 0>,
+				<DCC_LOOP 0xb  0 0>,
+				<DCC_READ 0x1510010 2 0>,
+				<DCC_LOOP 0x1 0 0>,
+				<DCC_READ 0x17100104 29 0>,
+				<DCC_READ 0x17100204 29 0>,
+				<DCC_READ 0x17100384 29 0>,
+				<DCC_READ 0xb281024 1 0>,
+				<DCC_READ 0xbde1034 1 0>,
+				<DCC_READ 0xb201020 2 0>,
+				<DCC_READ 0xb211020 2 0>,
+				<DCC_READ 0xb221020 2 0>,
+				<DCC_READ 0xb231020 2 0>,
+				<DCC_READ 0xb204520 1 0>,
+				<DCC_READ 0x17a00010 1 0>,
+				<DCC_READ 0x17a10010 1 0>,
+				<DCC_READ 0x17a20010 1 0>,
+				<DCC_READ 0x17a30010 1 0>,
+				<DCC_READ 0x17a00030 1 0>,
+				<DCC_READ 0x17a10030 1 0>,
+				<DCC_READ 0x17a20030 1 0>,
+				<DCC_READ 0x17a30030 1 0>,
+				<DCC_READ 0x17a00038 1 0>,
+				<DCC_READ 0x17a10038 1 0>,
+				<DCC_READ 0x17a20038 1 0>,
+				<DCC_READ 0x17a30038 1 0>,
+				<DCC_READ 0x17a00040 1 0>,
+				<DCC_READ 0x17a10040 1 0>,
+				<DCC_READ 0x17a20040 1 0>,
+				<DCC_READ 0x17a30040 1 0>,
+				<DCC_READ 0x17a00048 1 0>,
+				<DCC_READ 0x17a00400 3 0>,
+				<DCC_READ 0x17a10400 3 0>,
+				<DCC_READ 0x17a20400 3 0>,
+				<DCC_READ 0x17a30400 3 0>,
+				<DCC_READ 0xc230000 6 0>;
+		};
+	};
+
+	mem_dump {
+		compatible = "qcom,mem-dump";
+		memory-region = <&dump_mem>;
+
+		c0_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x0>;
+		};
+
+		c100_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x1>;
+		};
+
+		c200_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x2>;
+		};
+
+		c300_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x3>;
+		};
+
+		c400_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x4>;
+		};
+
+		c500_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x5>;
+		};
+
+		c600_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x6>;
+		};
+
+		c700_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x7>;
+		};
+
+		complex0_scan {
+			qcom,dump-size = <0x4a100>;
+			qcom,dump-id = <0x130>;
+		};
+
+		complex1_scan {
+			qcom,dump-size = <0x4a100>;
+			qcom,dump-id = <0x131>;
+		};
+
+		gold0_scan {
+			qcom,dump-size = <0x5f700>;
+			qcom,dump-id = <0x132>;
+		};
+
+		gold1_scan {
+			qcom,dump-size = <0x5f700>;
+			qcom,dump-id = <0x133>;
+		};
+
+		gold2_scan {
+			qcom,dump-size = <0x5f700>;
+			qcom,dump-id = <0x134>;
+		};
+
+		gold3_scan {
+			qcom,dump-size = <0x81100>;
+			qcom,dump-id = <0x135>;
+		};
+
+		l3slice0scan {
+			qcom,dump-size = <0x4cd00>;
+			qcom,dump-id = <0x136>;
+		};
+
+		l3slice1scan {
+			qcom,dump-size = <0x14e00>;
+			qcom,dump-id = <0x137>;
+		};
+
+		l3slice2scan {
+			qcom,dump-size = <0x14e00>;
+			qcom,dump-id = <0x138>;
+		};
+
+		l3slice3scan {
+			qcom,dump-size = <0x14e00>;
+			qcom,dump-id = <0x139>;
+		};
+
+		mhm_scan {
+			qcom,dump-size = <0x5a700>;
+			qcom,dump-id = <0x161>;
+		};
+
+		l1_icache0 {
+			qcom,dump-size = <0x9100>;
+			qcom,dump-id = <0x60>;
+		};
+
+		l1_icache100 {
+			qcom,dump-size = <0x9100>;
+			qcom,dump-id = <0x61>;
+		};
+
+		l1_icache200 {
+			qcom,dump-size = <0x9100>;
+			qcom,dump-id = <0x62>;
+		};
+
+		l1_icache300 {
+			qcom,dump-size = <0x9100>;
+			qcom,dump-id = <0x63>;
+		};
+
+		l1_icache400 {
+			qcom,dump-size = <0x11100>;
+			qcom,dump-id = <0x64>;
+		};
+
+		l1_icache500 {
+			qcom,dump-size = <0x11100>;
+			qcom,dump-id = <0x65>;
+		};
+
+		l1_icache600 {
+			qcom,dump-size = <0x11100>;
+			qcom,dump-id = <0x66>;
+		};
+
+		l1_icache700 {
+			qcom,dump-size = <0x22100>;
+			qcom,dump-id = <0x67>;
+		};
+
+		l1_dcache0 {
+			qcom,dump-size = <0x9100>;
+			qcom,dump-id = <0x80>;
+		};
+
+		l1_dcache100 {
+			qcom,dump-size = <0x9100>;
+			qcom,dump-id = <0x81>;
+		};
+
+		l1_dcache200 {
+			qcom,dump-size = <0x9100>;
+			qcom,dump-id = <0x82>;
+		};
+
+		l1_dcache300 {
+			qcom,dump-size = <0x9100>;
+			qcom,dump-id = <0x83>;
+		};
+
+		l1_dcache400 {
+			qcom,dump-size = <0xd100>;
+			qcom,dump-id = <0x84>;
+		};
+
+		l1_dcache500 {
+			qcom,dump-size = <0xd100>;
+			qcom,dump-id = <0x85>;
+		};
+
+		l1_dcache600 {
+			qcom,dump-size = <0xd100>;
+			qcom,dump-id = <0x86>;
+		};
+
+		l1_dcache700 {
+			qcom,dump-size = <0x1a100>;
+			qcom,dump-id = <0x87>;
+		};
+
+		l1_itlb400 {
+			qcom,dump-size = <0x600>;
+			qcom,dump-id = <0x24>;
+		};
+
+		l1_itlb500 {
+			qcom,dump-size = <0x600>;
+			qcom,dump-id = <0x25>;
+		};
+
+		l1_itlb600 {
+			qcom,dump-size = <0x600>;
+			qcom,dump-id = <0x26>;
+		};
+
+		l1_itlb700 {
+			qcom,dump-size = <0x600>;
+			qcom,dump-id = <0x27>;
+		};
+
+		l1_dtlb400 {
+			qcom,dump-size = <0x600>;
+			qcom,dump-id = <0x44>;
+		};
+
+		l1_dtlb500 {
+			qcom,dump-size = <0x600>;
+			qcom,dump-id = <0x45>;
+		};
+
+		l1_dtlb600 {
+			qcom,dump-size = <0x600>;
+			qcom,dump-id = <0x46>;
+		};
+
+		l1_dtlb700 {
+			qcom,dump-size = <0x600>;
+			qcom,dump-id = <0x47>;
+		};
+
+		l2_cache0 {
+			qcom,dump-size = <0x14100>;
+			qcom,dump-id = <0xc0>;
+		};
+
+		l2_cache100 {
+			qcom,dump-size = <0x14100>;
+			qcom,dump-id = <0xc1>;
+		};
+
+		l2_cache200 {
+			qcom,dump-size = <0x14100>;
+			qcom,dump-id = <0xc2>;
+		};
+
+		l2_cache300 {
+			qcom,dump-size = <0x14100>;
+			qcom,dump-id = <0xc3>;
+		};
+
+		l2_cache400 {
+			qcom,dump-size = <0xd0100>;
+			qcom,dump-id = <0xc4>;
+		};
+
+		l2_cache500 {
+			qcom,dump-size = <0xd0100>;
+			qcom,dump-id = <0xc5>;
+		};
+
+		l2_cache600 {
+			qcom,dump-size = <0xd0100>;
+			qcom,dump-id = <0xc6>;
+		};
+
+		l2_cache700 {
+			qcom,dump-size = <0x1a0100>;
+			qcom,dump-id = <0xc7>;
+		};
+
+		l2_tlb0 {
+			qcom,dump-size = <0x2100>;
+			qcom,dump-id = <0x120>;
+		};
+
+		l2_tlb100 {
+			qcom,dump-size = <0x2100>;
+			qcom,dump-id = <0x121>;
+		};
+
+		l2_tlb200 {
+			qcom,dump-size = <0x2100>;
+			qcom,dump-id = <0x122>;
+		};
+
+		l2_tlb300 {
+			qcom,dump-size = <0x2100>;
+			qcom,dump-id = <0x123>;
+		};
+
+		l2_tlb400 {
+			qcom,dump-size = <0xc100>;
+			qcom,dump-id = <0x124>;
+		};
+
+		l2_tlb500 {
+			qcom,dump-size = <0xc100>;
+			qcom,dump-id = <0x125>;
+		};
+
+		l2_tlb600 {
+			qcom,dump-size = <0xc100>;
+			qcom,dump-id = <0x126>;
+		};
+
+		l2_tlb700 {
+			qcom,dump-size = <0xc100>;
+			qcom,dump-id = <0x127>;
+		};
+
+		l1dcdirty0 {
+			qcom,dump-size = <0x1100>;
+			qcom,dump-id = <0x170>;
+		};
+
+		l1dcdirty100 {
+			qcom,dump-size = <0x1100>;
+			qcom,dump-id = <0x171>;
+		};
+
+		l1dcdirty200 {
+			qcom,dump-size = <0x1100>;
+			qcom,dump-id = <0x172>;
+		};
+
+		l1dcdirty300 {
+			qcom,dump-size = <0x1100>;
+			qcom,dump-id = <0x173>;
+		};
+
+		l1dcmte0 {
+			qcom,dump-size = <0x1100>;
+			qcom,dump-id = <0x180>;
+		};
+
+		l1dcmte100 {
+			qcom,dump-size = <0x1100>;
+			qcom,dump-id = <0x181>;
+		};
+
+		l1dcmte200 {
+			qcom,dump-size = <0x1100>;
+			qcom,dump-id = <0x182>;
+		};
+
+		l1dcmte300 {
+			qcom,dump-size = <0x1100>;
+			qcom,dump-id = <0x183>;
+		};
+
+		l2dcmte0 {
+			qcom,dump-size = <0x4100>;
+			qcom,dump-id = <0x190>;
+		};
+
+		l2dcmte100 {
+			qcom,dump-size = <0x4100>;
+			qcom,dump-id = <0x191>;
+		};
+
+		l2dcmte200 {
+			qcom,dump-size = <0x4100>;
+			qcom,dump-id = <0x192>;
+		};
+
+		l2dcmte300 {
+			qcom,dump-size = <0x4100>;
+			qcom,dump-id = <0x193>;
+		};
+
+		l0mopca400 {
+			qcom,dump-size = <0x6100>;
+			qcom,dump-id = <0x1a4>;
+		};
+
+		l0mopca500 {
+			qcom,dump-size = <0x6100>;
+			qcom,dump-id = <0x1a5>;
+		};
+
+		l0mopca600 {
+			qcom,dump-size = <0x6100>;
+			qcom,dump-id = <0x1a6>;
+		};
+
+		l0mopca700 {
+			qcom,dump-size = <0xc100>;
+			qcom,dump-id = <0x1a7>;
+		};
+
+		l1btb400 {
+			qcom,dump-size = <0x10100>;
+			qcom,dump-id = <0x1b4>;
+		};
+
+		l1btb500 {
+			qcom,dump-size = <0x10100>;
+			qcom,dump-id = <0x1b5>;
+		};
+
+		l1btb600 {
+			qcom,dump-size = <0x10100>;
+			qcom,dump-id = <0x1b6>;
+		};
+
+		l1btb700 {
+			qcom,dump-size = <0x10100>;
+			qcom,dump-id = <0x1b7>;
+		};
+
+		l1ghb400 {
+			qcom,dump-size = <0x4100>;
+			qcom,dump-id = <0x1c4>;
+		};
+
+		l1ghb500 {
+			qcom,dump-size = <0x4100>;
+			qcom,dump-id = <0x1c5>;
+		};
+
+		l1ghb600 {
+			qcom,dump-size = <0x4100>;
+			qcom,dump-id = <0x1c6>;
+		};
+
+		l1ghb700 {
+			qcom,dump-size = <0x8100>;
+			qcom,dump-id = <0x1c7>;
+		};
+
+		l1bim400 {
+			qcom,dump-size = <0x2100>;
+			qcom,dump-id = <0x1d4>;
+		};
+
+		l1bim500 {
+			qcom,dump-size = <0x2100>;
+			qcom,dump-id = <0x1d5>;
+		};
+
+		l1bim600 {
+			qcom,dump-size = <0x2100>;
+			qcom,dump-id = <0x1d6>;
+		};
+
+		l1bim700 {
+			qcom,dump-size = <0x4100>;
+			qcom,dump-id = <0x1d7>;
+		};
+
+		l2victim400 {
+			qcom,dump-size = <0x2100>;
+			qcom,dump-id = <0x1e4>;
+		};
+
+		l2victim500 {
+			qcom,dump-size = <0x2100>;
+			qcom,dump-id = <0x1e5>;
+		};
+
+		l2victim600 {
+			qcom,dump-size = <0x2100>;
+			qcom,dump-id = <0x1e6>;
+		};
+
+		l2victim700 {
+			qcom,dump-size = <0x2100>;
+			qcom,dump-id = <0x1e7>;
+		};
+
+		cpuss_reg {
+			qcom,dump-size = <0x30000>;
+			qcom,dump-id = <0xef>;
+		};
+
+		gemnoc {
+			qcom,dump-size = <0x100000>;
+			qcom,dump-id = <0x162>;
+		};
+
+		rpmh {
+			qcom,dump-size = <0x2000000>;
+			qcom,dump-id = <0xec>;
+		};
+
+		rpm_sw {
+			qcom,dump-size = <0x28000>;
+			qcom,dump-id = <0xea>;
+		};
+
+		pmic {
+			qcom,dump-size = <0x200000>;
+			qcom,dump-id = <0xe4>;
+		};
+
+		fcm {
+			qcom,dump-size = <0x8400>;
+			qcom,dump-id = <0xee>;
+		};
+
+		etf_swao {
+			qcom,dump-size = <0x10000>;
+			qcom,dump-id = <0xf1>;
+		};
+
+		etr_reg {
+			qcom,dump-size = <0x1000>;
+			qcom,dump-id = <0x100>;
+		};
+
+		etfswao_reg {
+			qcom,dump-size = <0x1000>;
+			qcom,dump-id = <0x102>;
+		};
+
+		etr1_reg {
+			qcom,dump-size = <0x1000>;
+			qcom,dump-id = <0x105>;
+		};
+
+		misc_data {
+			qcom,dump-size = <0x1000>;
+			qcom,dump-id = <0xe8>;
+		};
+
+		etf_slpi {
+			qcom,dump-size = <0x4000>;
+			qcom,dump-id = <0xf3>;
+		};
+
+		etfslpi_reg {
+			qcom,dump-size = <0x1000>;
+			qcom,dump-id = <0x103>;
+		};
+
+		etf_lpass {
+			qcom,dump-size = <0x4000>;
+			qcom,dump-id = <0xf4>;
+		};
+
+		etflpass_reg {
+			qcom,dump-size = <0x1000>;
+			qcom,dump-id = <0x104>;
+		};
+
+		llcc1dc {
+			qcom,dump-size = <0x171000>;
+			qcom,dump-id = <0x140>;
+		};
+
+		llcc2dc {
+			qcom,dump-size = <0x171000>;
+			qcom,dump-id = <0x141>;
+		};
+
+		llcc3dc {
+			qcom,dump-size = <0x171000>;
+			qcom,dump-id = <0x142>;
+		};
+
+		llcc4dc {
+			qcom,dump-size = <0x171000>;
+			qcom,dump-id = <0x143>;
+		};
+	};
+};
diff --git a/qcom/waipio-dma-heaps.dtsi b/qcom/waipio-dma-heaps.dtsi
new file mode 100644
index 00000000..d0dd7819
--- /dev/null
+++ b/qcom/waipio-dma-heaps.dtsi
@@ -0,0 +1,71 @@
+#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h>
+
+&soc {
+	qcom,dma-heaps {
+		compatible = "qcom,dma-heaps";
+
+		qcom,adsp {
+			qcom,dma-heap-name = "qcom,adsp";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&sdsp_mem>;
+		};
+
+		qcom,secure_cdsp {
+			qcom,dma-heap-name = "qcom,secure-cdsp";
+			qcom,dma-heap-type = <HEAP_TYPE_SECURE_CARVEOUT>;
+			memory-region = <&cdsp_secure_heap>;
+			qcom,token = <0x20000000>;
+		};
+
+		qcom,sp_hlos {
+			qcom,dma-heap-name = "qcom,sp-hlos";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&sp_mem>;
+		};
+
+		qcom,secure_sp_modem {
+			qcom,dma-heap-name = "qcom,secure-sp-modem";
+			qcom,dma-heap-type = <HEAP_TYPE_SECURE_CARVEOUT>;
+			memory-region = <&spu_modem_shared_mem>;
+			qcom,token = <0x10800000>;
+		};
+
+		qcom,secure_sp_tz {
+			qcom,dma-heap-name = "qcom,secure-sp-tz";
+			qcom,dma-heap-type = <HEAP_TYPE_SECURE_CARVEOUT>;
+			memory-region = <&spu_tz_shared_mem>;
+			qcom,token = <0x01000000>;
+		};
+
+		qcom,user_contig {
+			qcom,dma-heap-name = "qcom,user-contig";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&user_contig_mem>;
+		};
+
+		qcom,qseecom {
+			qcom,dma-heap-name = "qcom,qseecom";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&qseecom_mem>;
+		};
+
+		qcom,qseecom_ta {
+			qcom,dma-heap-name = "qcom,qseecom-ta";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&qseecom_ta_mem>;
+		};
+
+		qcom,display {
+			qcom,dma-heap-name = "qcom,display";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			qcom,max-align = <9>;
+			memory-region = <&non_secure_display_memory>;
+		};
+
+		qcom,audio_ml {
+			qcom,dma-heap-name = "qcom,audio-ml";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&audio_cma_mem>;
+		};
+	};
+};
diff --git a/qcom/waipio-eva.dtsi b/qcom/waipio-eva.dtsi
new file mode 100644
index 00000000..c76f1f1d
--- /dev/null
+++ b/qcom/waipio-eva.dtsi
@@ -0,0 +1,110 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,ipcc.h>
+#include <dt-bindings/interconnect/qcom,waipio.h>
+#include <dt-bindings/clock/qcom,videocc-waipio.h>
+
+&soc {
+	msm_cvp: qcom,cvp@ab00000 {
+		compatible = "qcom,msm-cvp", "qcom,waipio-cvp";
+		status = "ok";
+		reg = <0xab00000 0x100000>;
+		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+
+		/* LLCC Cache */
+		cache-slice-names = "cvp";
+
+		/* Supply */
+		cvp-supply = <&video_cc_mvs1c_gdsc>;
+		cvp-core-supply = <&video_cc_mvs1_gdsc>;
+
+		/* Clocks */
+		clock-names = "gcc_video_axi1", "cvp_clk", "core_clk",
+				"video_cc_mvs1_clk_src";
+		clock-ids = <GCC_VIDEO_AXI1_CLK VIDEO_CC_MVS1C_CLK
+			VIDEO_CC_MVS1_CLK VIDEO_CC_MVS1_CLK_SRC>;
+		clocks = <&clock_gcc GCC_VIDEO_AXI1_CLK>,
+			<&clock_videocc VIDEO_CC_MVS1C_CLK>,
+			<&clock_videocc VIDEO_CC_MVS1_CLK>,
+			<&clock_videocc VIDEO_CC_MVS1_CLK_SRC>;
+		qcom,proxy-clock-names = "gcc_video_axi1",
+			"cvp_clk", "core_clk", "video_cc_mvs1_clk_src";
+
+		qcom,clock-configs = <0x0 0x0 0x0 0x1>;
+		qcom,allowed-clock-rates = <350000000 450000000 500000000 550000000>;
+
+		resets = <&clock_gcc GCC_VIDEO_AXI1_CLK_ARES>,
+			<&clock_videocc VIDEO_CC_MVS1C_CLK_ARES>;
+		reset-names = "cvp_axi_reset", "cvp_core_reset";
+		reset-power-status = <0x2 0x2>;
+
+		qcom,reg-presets = <0xB0088 0x0>;
+		qcom,ipcc-reg = <0x400000 0x100000>;
+		qcom,gcc-reg = <0x110000 0x40000>;
+
+		pas-id = <26>;
+		memory-region = <&cvp_mem>;
+
+		/* CVP Firmware ELF image name */
+		cvp,firmware-name = "evass";
+
+		/* Buses */
+		cvp_cnoc {
+			compatible = "qcom,msm-cvp,bus";
+			label = "cvp-cnoc";
+			qcom,bus-master = <MASTER_APPSS_PROC>;
+			qcom,bus-slave = <SLAVE_VENUS_CFG>;
+			qcom,bus-governor = "performance";
+			qcom,bus-range-kbps = <1000 1000>;
+		};
+
+		cvp_bus_ddr {
+			compatible = "qcom,msm-cvp,bus";
+			label = "cvp-ddr";
+			qcom,bus-master = <MASTER_VIDEO_PROC>;
+			qcom,bus-slave = <SLAVE_EBI1>;
+			qcom,bus-governor = "performance";
+			qcom,bus-range-kbps = <1000 6533000>;
+		};
+
+		/* MMUs */
+		cvp_non_secure_cb {
+			compatible = "qcom,msm-cvp,context-bank";
+			label = "cvp_hlos";
+			iommus =
+				<&apps_smmu 0x21a0 0x400>;
+			buffer-types = <0xfff>;
+			dma-coherent;
+			qcom,iommu-faults = "non-fatal";
+			qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>;
+		};
+
+
+		cvp_secure_nonpixel_cb {
+			compatible = "qcom,msm-cvp,context-bank";
+			label = "cvp_sec_nonpixel";
+			iommus =
+				<&apps_smmu 0x21a4 0x400>;
+			buffer-types = <0x741>;
+			qcom,iommu-faults = "non-fatal";
+			qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>;
+			qcom,iommu-vmid = <0xB>;
+		};
+
+		cvp_secure_pixel_cb {
+			compatible = "qcom,msm-cvp,context-bank";
+			label = "cvp_sec_pixel";
+			iommus =
+				<&apps_smmu 0x21a3 0x400>;
+			buffer-types = <0x106>;
+			qcom,iommu-faults = "non-fatal";
+			qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>;
+			qcom,iommu-vmid = <0xA>;
+		};
+
+		/* Memory Heaps */
+		qcom,msm-cvp,mem_cdsp {
+			compatible = "qcom,msm-cvp,mem-cdsp";
+			memory-region = <&cdsp_eva_mem>;
+		};
+	};
+};
diff --git a/qcom/waipio-gpu.dtsi b/qcom/waipio-gpu.dtsi
new file mode 100644
index 00000000..5abc8a6e
--- /dev/null
+++ b/qcom/waipio-gpu.dtsi
@@ -0,0 +1,283 @@
+
+#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
+
+&soc {
+	msm_gpu: qcom,kgsl-3d0@3d00000 {
+		compatible = "qcom,adreno-gpu-c500", "qcom,kgsl-3d0";
+		status = "ok";
+		reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,
+			<0x03d50000 0x10000>, <0x3d8b000 0x2000>,
+			<0x03d9e000 0x1000>, <0x10900000 0x80000>;
+		reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc",
+			"isense_cntl", "cx_misc", "qdss_gfx";
+		interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "kgsl_3d0_irq";
+
+		clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
+			<&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+			<&clock_gpucc GPU_CC_AHB_CLK>,
+			<&aoss_qmp QDSS_CLK>;
+		clock-names = "gcc_gpu_memnoc_gfx",
+				"gcc_gpu_snoc_dvm_gfx",
+				"gpu_cc_ahb", "apb_pclk";
+
+		qcom,gpu-model = "Adreno730v1";
+
+		qcom,initial-pwrlevel = <8>;
+
+		qcom,no-nap;
+
+		qcom,min-access-length = <32>;
+
+		qcom,ubwc-mode = <4>;
+
+		qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
+
+		qcom,tzone-names = "gpuss-0", "gpuss-1";
+
+		interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
+		interconnect-names = "gpu_icc_path";
+
+		qcom,bus-table-cnoc =
+			<0>,   /* Off */
+			<100>; /* On */
+
+		qcom,bus-table-ddr =
+			<MHZ_TO_KBPS(0, 4)>,    /* index=0  */
+			<MHZ_TO_KBPS(200, 4)>,  /* index=1  */
+			<MHZ_TO_KBPS(451, 4)>,  /* index=2  */
+			<MHZ_TO_KBPS(547, 4)>,  /* index=3  */
+			<MHZ_TO_KBPS(681, 4)>,  /* index=4  */
+			<MHZ_TO_KBPS(768, 4)>,  /* index=5  */
+			<MHZ_TO_KBPS(1555, 4)>, /* index=6  */
+			<MHZ_TO_KBPS(1708, 4)>, /* index=7  */
+			<MHZ_TO_KBPS(2092, 4)>, /* index=8  */
+			<MHZ_TO_KBPS(2736, 4)>, /* index=9  */
+			<MHZ_TO_KBPS(3196, 4)>; /* index=10  */
+
+		zap-shader {
+			memory-region = <&gpu_micro_code_mem>;
+		};
+
+		/* Power levels */
+		qcom,gpu-pwrlevels {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			compatible = "qcom,gpu-pwrlevels";
+
+			qcom,gpu-pwrlevel@0 {
+				reg = <0>;
+				qcom,gpu-freq = <818000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
+
+				qcom,bus-freq = <10>;
+				qcom,bus-min = <10>;
+				qcom,bus-max = <10>;
+
+				qcom,acd-level = <0x882c5ffd>;
+			};
+
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
+				qcom,gpu-freq = <791000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+
+				qcom,bus-freq = <10>;
+				qcom,bus-min = <9>;
+				qcom,bus-max = <10>;
+
+				qcom,acd-level = <0x882c5ffd>;
+			};
+
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
+				qcom,gpu-freq = <734000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+
+				qcom,bus-freq = <10>;
+				qcom,bus-min = <9>;
+				qcom,bus-max = <10>;
+
+				qcom,acd-level = <0x882d5ffd>;
+			};
+
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
+				qcom,gpu-freq = <640000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+
+				qcom,bus-freq = <10>;
+				qcom,bus-min = <6>;
+				qcom,bus-max = <10>;
+
+				qcom,acd-level = <0xa82d5ffd>;
+			};
+
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
+				qcom,gpu-freq = <599000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+
+				qcom,bus-freq = <8>;
+				qcom,bus-min = <6>;
+				qcom,bus-max = <9>;
+
+				qcom,acd-level = <0x882e5ffd>;
+			};
+
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
+				qcom,gpu-freq = <545000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+
+				qcom,bus-freq = <8>;
+				qcom,bus-min = <6>;
+				qcom,bus-max = <9>;
+
+				qcom,acd-level = <0x882e5ffd>;
+			};
+
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
+				qcom,gpu-freq = <492000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <6>;
+				qcom,bus-max = <8>;
+
+				qcom,acd-level = <0x882e5ffd>;
+			};
+
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
+				qcom,gpu-freq = <421000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <3>;
+				qcom,bus-max = <8>;
+
+				qcom,acd-level = <0xa82e5ffd>;
+			};
+
+			qcom,gpu-pwrlevel@8 {
+				reg = <8>;
+				qcom,gpu-freq = <350000000>;
+				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+
+				qcom,bus-freq = <2>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <5>;
+
+				qcom,acd-level = <0x882f5ffd>;
+			};
+		};
+
+		qcom,gpu-mempools {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "qcom,gpu-mempools";
+
+			/* 4K Page Pool configuration */
+			qcom,gpu-mempool@0 {
+				reg = <0>;
+				qcom,mempool-page-size = <4096>;
+				qcom,mempool-reserved = <2048>;
+			};
+			/* 8K Page Pool configuration */
+			qcom,gpu-mempool@1 {
+				reg = <1>;
+				qcom,mempool-page-size = <8192>;
+				qcom,mempool-reserved = <1024>;
+			};
+			/* 64K Page Pool configuration */
+			qcom,gpu-mempool@2 {
+				reg = <2>;
+				qcom,mempool-page-size = <65536>;
+				qcom,mempool-reserved = <256>;
+			};
+			/* 128K Page Pool configuration */
+			qcom,gpu-mempool@3 {
+				reg = <3>;
+				qcom,mempool-page-size = <131072>;
+				qcom,mempool-reserved = <128>;
+			};
+			/* 256K Page Pool configuration */
+			qcom,gpu-mempool@4 {
+				reg = <4>;
+				qcom,mempool-page-size = <262144>;
+				qcom,mempool-reserved = <80>;
+			};
+			/* 1M Page Pool configuration */
+			qcom,gpu-mempool@5 {
+				reg = <5>;
+				qcom,mempool-page-size = <1048576>;
+				qcom,mempool-reserved = <32>;
+			};
+		};
+	};
+
+	kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
+		compatible = "qcom,kgsl-smmu-v2";
+		reg = <0x03da0000 0x40000>;
+
+		vddcx-supply = <&gpu_cc_cx_gdsc>;
+
+		gfx3d_user: gfx3d_user {
+			compatible = "qcom,smmu-kgsl-cb";
+			iommus = <&kgsl_smmu 0x0 0x400>;
+			qcom,iommu-dma = "disabled";
+		};
+
+		gfx3d_lpac: gfx3d_lpac {
+			compatible = "qcom,smmu-kgsl-cb";
+			iommus = <&kgsl_smmu 0x1 0x400>;
+			qcom,iommu-dma = "disabled";
+		};
+
+		gfx3d_secure: gfx3d_secure {
+			compatible = "qcom,smmu-kgsl-cb";
+			iommus = <&kgsl_smmu 0x2 0x400>;
+			qcom,iommu-dma = "disabled";
+		};
+	};
+
+	gmu: qcom,gmu@3d69000 {
+		compatible = "qcom,genc-gmu";
+
+		reg = <0x3d68000 0x37000>,
+		      <0xb290000 0x10000>,
+		      <0x03D40000 0x10000>;
+
+		reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0";
+
+		interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
+			<0 305 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hfi", "gmu";
+
+		regulator-names = "vddcx", "vdd";
+
+		vddcx-supply = <&gpu_cc_cx_gdsc>;
+		vdd-supply = <&gpu_cc_gx_gdsc>;
+
+		clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>,
+			<&clock_gpucc GPU_CC_CXO_CLK>,
+			<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
+			<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
+			<&clock_gpucc GPU_CC_AHB_CLK>,
+			<&clock_gpucc GPU_CC_HUB_CX_INT_CLK>,
+			<&aoss_qmp>;
+
+		clock-names = "gmu_clk", "cxo_clk", "axi_clk",
+			"memnoc_clk", "ahb_clk", "hub_clk", "apb_pclk";
+
+
+		iommus = <&kgsl_smmu 0x5 0x400>;
+		qcom,iommu-dma = "disabled";
+
+		mboxes = <&qmp_aop 0>;
+		mbox-names = "aop";
+	};
+};
diff --git a/qcom/waipio-hdk.dtsi b/qcom/waipio-hdk.dtsi
new file mode 100644
index 00000000..4d933b8b
--- /dev/null
+++ b/qcom/waipio-hdk.dtsi
@@ -0,0 +1 @@
+#include "waipio-qrd.dtsi"
diff --git a/qcom/waipio-kiwi-mtp-pm8008-overlay.dts b/qcom/waipio-kiwi-mtp-pm8008-overlay.dts
new file mode 100644
index 00000000..9b3a679b
--- /dev/null
+++ b/qcom/waipio-kiwi-mtp-pm8008-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "waipio-mtp.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio with kiwi";
+	compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
+	qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
+	qcom,board-id = <0x02010008 0>;
+};
diff --git a/qcom/waipio-kiwi-mtp-pm8010-overlay.dts b/qcom/waipio-kiwi-mtp-pm8010-overlay.dts
new file mode 100644
index 00000000..f99f0a49
--- /dev/null
+++ b/qcom/waipio-kiwi-mtp-pm8010-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "waipio-mtp.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio with Kiwi";
+	compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
+	qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
+	qcom,board-id = <0x02010008 0>;
+};
diff --git a/qcom/waipio-lemur-cdp-pm8008-overlay.dts b/qcom/waipio-lemur-cdp-pm8008-overlay.dts
new file mode 100644
index 00000000..020ffdbf
--- /dev/null
+++ b/qcom/waipio-lemur-cdp-pm8008-overlay.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+#include "waipio-mtp.dtsi"
+#include "waipio-pm8008.dtsi"
+#include "sdxlemur-external-soc.dtsi"
+#include "waipio-lemur.dtsi"
+
+/ {
+	model = "WAIPIO LEMUR CDP";
+	compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
+	qcom,msm-id = <457 0x10000>;
+	qcom,board-id = <0x01010001 0x1>;
+};
diff --git a/qcom/waipio-lemur-cdp-pm8010-overlay.dts b/qcom/waipio-lemur-cdp-pm8010-overlay.dts
new file mode 100644
index 00000000..fba97341
--- /dev/null
+++ b/qcom/waipio-lemur-cdp-pm8010-overlay.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+#include "waipio-mtp.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+#include "sdxlemur-external-soc.dtsi"
+#include "waipio-lemur.dtsi"
+
+/ {
+	model = "WAIPIO LEMUR CDP";
+	compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
+	qcom,msm-id = <457 0x10000>;
+	qcom,board-id = <0x01010001 0x1>;
+};
diff --git a/qcom/waipio-lemur-mtp-pm8008-overlay.dts b/qcom/waipio-lemur-mtp-pm8008-overlay.dts
new file mode 100644
index 00000000..5eb976ef
--- /dev/null
+++ b/qcom/waipio-lemur-mtp-pm8008-overlay.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+#include "waipio-mtp.dtsi"
+#include "waipio-pm8008.dtsi"
+#include "sdxlemur-external-soc.dtsi"
+#include "waipio-lemur.dtsi"
+
+/ {
+	model = "WAIPIO LEMUR MTP";
+	compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
+	qcom,msm-id = <457 0x10000>;
+	qcom,board-id = <0x01010008 0x1>;
+};
diff --git a/qcom/waipio-lemur-mtp-pm8010-overlay.dts b/qcom/waipio-lemur-mtp-pm8010-overlay.dts
new file mode 100644
index 00000000..76ccd847
--- /dev/null
+++ b/qcom/waipio-lemur-mtp-pm8010-overlay.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+#include "waipio-mtp.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+#include "sdxlemur-external-soc.dtsi"
+#include "waipio-lemur.dtsi"
+
+/ {
+	model = "WAIPIO LEMUR MTP";
+	compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
+	qcom,msm-id = <457 0x10000>;
+	qcom,board-id = <0x01010008 0x1>;
+};
diff --git a/qcom/waipio-lemur.dtsi b/qcom/waipio-lemur.dtsi
new file mode 100644
index 00000000..c49d169b
--- /dev/null
+++ b/qcom/waipio-lemur.dtsi
@@ -0,0 +1,252 @@
+#include <dt-bindings/interconnect/qcom,waipio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+
+&mdm0 {
+	compatible = "qcom,ext-lemur";
+	qcom,mdm-link-info = "0308_01.01.00";
+};
+
+&modem_pas {
+	status = "disabled";
+};
+
+&pcie1 {
+	qcom,target-link-width = <1>; /* force X1 lane width */
+	qcom,no-l0s-supported;
+	qcom,target-link-speed = <4>; /* Set max link speed to Gen4 */
+	qcom,vreg-0p9-voltage-level = <912000 912000 193000>;
+	qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+					RPMH_REGULATOR_LEVEL_NOM 0>;
+	qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+					RPMH_REGULATOR_LEVEL_NOM 0>;
+	qcom,bw-scale = /* Gen1 */
+			<RPMH_REGULATOR_LEVEL_LOW_SVS
+			RPMH_REGULATOR_LEVEL_LOW_SVS
+			19200000
+			/* Gen2 */
+			RPMH_REGULATOR_LEVEL_LOW_SVS
+			RPMH_REGULATOR_LEVEL_LOW_SVS
+			19200000
+			/* Gen3 */
+			RPMH_REGULATOR_LEVEL_LOW_SVS
+			RPMH_REGULATOR_LEVEL_LOW_SVS
+			100000000
+			/* Gen4 */
+			RPMH_REGULATOR_LEVEL_NOM
+			RPMH_REGULATOR_LEVEL_NOM
+			100000000>;
+
+	qcom,pcie-phy-ver = <105>;
+	qcom,phy-sequence = <0x1240 0x03 0x0
+			0x101c 0x31 0x0
+			0x1020 0x01 0x0
+			0x1024 0xde 0x0
+			0x1028 0x07 0x0
+			0x1030 0x97 0x0
+			0x1034 0x0c 0x0
+			0x1044 0x14 0x0
+			0x1048 0x90 0x0
+			0x1058 0x0f 0x0
+			0x1074 0x06 0x0
+			0x1078 0x06 0x0
+			0x107c 0x16 0x0
+			0x1080 0x16 0x0
+			0x1084 0x36 0x0
+			0x1088 0x36 0x0
+			0x1094 0x08 0x0
+			0x10a4 0x46 0x0
+			0x10a8 0x04 0x0
+			0x10ac 0x0a 0x0
+			0x10b0 0x1a 0x0
+			0x10b4 0x14 0x0
+			0x10b8 0x34 0x0
+			0x10bc 0x82 0x0
+			0x10c4 0xd0 0x0
+			0x10cc 0x55 0x0
+			0x10d0 0x55 0x0
+			0x10d4 0x03 0x0
+			0x10d8 0x55 0x0
+			0x10dc 0x55 0x0
+			0x10e0 0x05 0x0
+			0x110c 0x02 0x0
+			0x1154 0x34 0x0
+			0x1158 0x12 0x0
+			0x115c 0x00 0x0
+			0x1168 0x0a 0x0
+			0x116c 0x04 0x0
+			0x119c 0x88 0x0
+			0x1174 0x20 0x0
+			0x117c 0x06 0x0
+			0x11a0 0x14 0x0
+			0x11a8 0x0f 0x0
+			0x0220 0x16 0x0
+			0x03c0 0x38 0x0
+			0x0a20 0x16 0x0
+			0x0bc0 0x38 0x0
+			0x0364 0xcc 0x0
+			0x0368 0x12 0x0
+			0x036c 0xcc 0x0
+			0x0374 0x4a 0x0
+			0x0378 0x29 0x0
+			0x037c 0xc5 0x0
+			0x0380 0xad 0x0
+			0x0384 0xb6 0x0
+			0x0388 0xc0 0x0
+			0x038c 0x1f 0x0
+			0x0390 0xfb 0x0
+			0x0394 0x0f 0x0
+			0x0398 0xc7 0x0
+			0x039c 0xef 0x0
+			0x03a0 0xbf 0x0
+			0x03a4 0xa0 0x0
+			0x03a8 0x81 0x0
+			0x03ac 0xde 0x0
+			0x03b0 0x7f 0x0
+			0x0b64 0xcc 0x0
+			0x0b68 0x12 0x0
+			0x0b6c 0xcc 0x0
+			0x0b74 0x4a 0x0
+			0x0b78 0x29 0x0
+			0x0b7c 0xc5 0x0
+			0x0b80 0xad 0x0
+			0x0b84 0xb6 0x0
+			0x0b88 0xc0 0x0
+			0x0b8c 0x1f 0x0
+			0x0b90 0xfb 0x0
+			0x0b94 0x0f 0x0
+			0x0b98 0xc7 0x0
+			0x0b9c 0xef 0x0
+			0x0ba0 0xbf 0x0
+			0x0ba4 0xa0 0x0
+			0x0ba8 0x81 0x0
+			0x0bac 0xde 0x0
+			0x0bb0 0x7f 0x0
+			0x03b4 0x20 0x0
+			0x022c 0x3f 0x0
+			0x0230 0x37 0x0
+			0x0bb4 0x20 0x0
+			0x0a2c 0x3f 0x0
+			0x0a30 0x37 0x0
+			0x0078 0x05 0x0
+			0x007c 0xf6 0x0
+			0x0878 0x05 0x0
+			0x087c 0xf6 0x0
+			0x0290 0x05 0x0
+			0x0a90 0x05 0x0
+			0x03f8 0x1f 0x0
+			0x0400 0x1f 0x0
+			0x0408 0x1f 0x0
+			0x0410 0x1f 0x0
+			0x0418 0x1f 0x0
+			0x0420 0x1f 0x0
+			0x03f4 0x1f 0x0
+			0x03fc 0x1f 0x0
+			0x0404 0x1f 0x0
+			0x0bf8 0x1f 0x0
+			0x0c00 0x1f 0x0
+			0x0c08 0x1f 0x0
+			0x0c10 0x1f 0x0
+			0x0c18 0x1f 0x0
+			0x0c20 0x1f 0x0
+			0x0bf4 0x1f 0x0
+			0x0bfc 0x1f 0x0
+			0x0c04 0x1f 0x0
+			0x0208 0x0c 0x0
+			0x0a08 0x0c 0x0
+			0x020c 0x0a 0x0
+			0x0a0c 0x0a 0x0
+			0x02dc 0x0a 0x0
+			0x0adc 0x0a 0x0
+			0x0308 0x0b 0x0
+			0x0b08 0x0b 0x0
+			0x027c 0x10 0x0
+			0x0a7c 0x10 0x0
+			0x02b4 0x00 0x0
+			0x0ab4 0x00 0x0
+			0x02ec 0x0f 0x0
+			0x0aec 0x0f 0x0
+			0x02c4 0x00 0x0
+			0x02c8 0x1f 0x0
+			0x0ac4 0x00 0x0
+			0x0ac8 0x1f 0x0
+			0x0030 0x1a 0x0
+			0x0034 0x0c 0x0
+			0x0830 0x1a 0x0
+			0x0834 0x0c 0x0
+			0x141c 0xc1 0x0
+			0x1490 0x00 0x0
+			0x13e0 0x16 0x0
+			0x13e4 0x22 0x0
+			0x1508 0x02 0x0
+			0x14a0 0x16 0x0
+			0x1584 0x28 0x0
+			0x1370 0x2e 0x0
+			0x155c 0x2e 0x0
+			0x1388 0x99 0x0
+			0x1e24 0x01 0x0
+			0x1e28 0x01 0x0
+			0x1828 0x50 0x0
+			0x1c28 0x50 0x0
+			0x1200 0x00 0x0
+			0x1244 0x03 0x0>;
+};
+
+&soc {
+	qcom,ipa-mpm {
+		compatible = "qcom,ipa-mpm";
+		qcom,iova-mapping = <0x10000000 0x0FFFFFFF>;
+	};
+
+	qcom,qbt_handler {
+		status = "disabled";
+	};
+};
+
+&ipa_hw {
+	status = "ok";
+	qcom,platform-type = <2>; /* APQ platform */
+	qcom,entire-ipa-block-size = <0x100000>;
+	qcom,register-collection-on-crash;
+	qcom,testbus-collection-on-crash;
+	qcom,non-tn-collection-on-crash;
+	qcom,ram-collection-on-crash;
+	qcom,secure-debug-check-action = <0>;
+};
+
+&tlmm {
+	qcom,gpios-reserved = <28 29 30 31>;
+};
+
+&pcie1_rp {
+	#address-cells = <5>;
+	#size-cells = <0>;
+
+	mhi0: qcom,mhi@0 {
+		reg = <0 0 0 0 0 >;
+
+		esoc-names = "mdm";
+		esoc-0 = <&mdm0>;
+
+		interconnects = <&pcie_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
+		interconnect-names = "pcie_to_ddr";
+
+		qcom,mhi-bus-bw-cfg =
+		<0 0>, /* no vote */
+		<250000 0>, /* avg bw / AB: 2 GBps, peak bw / IB: no vote */
+		<500000 0>, /* avg bw / AB: 4 GBps, peak bw / IB: no vote */
+		<1000000 0>, /* avg bw / AB: 8 GBps, peak bw / IB: no vote */
+		<2000000 0>; /* avg bw / AB: 16 GBps, peak bw / IB: no vote */
+
+		qcom,iommu-group = <&mhi0_iommu_group>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mhi0_iommu_group: mhi0_iommu_group {
+			qcom,iommu-msi-size = <0x1000>;
+			qcom,iommu-dma-addr-pool = <0x20000000 0x0fffffff>;
+			qcom,iommu-dma = "fastmap";
+			qcom,iommu-pagetable = "coherent";
+		};
+	};
+};
diff --git a/qcom/waipio-mtp-pm8008-overlay.dts b/qcom/waipio-mtp-pm8008-overlay.dts
new file mode 100644
index 00000000..a3bbf27f
--- /dev/null
+++ b/qcom/waipio-mtp-pm8008-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "waipio-mtp.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio MTP with PM8008";
+	compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
+	qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
+	qcom,board-id = <0x10008 0>;
+};
diff --git a/qcom/waipio-mtp-pm8008.dts b/qcom/waipio-mtp-pm8008.dts
new file mode 100644
index 00000000..cc5c8e22
--- /dev/null
+++ b/qcom/waipio-mtp-pm8008.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipio.dtsi"
+#include "waipio-mtp.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio MTP with PM8008";
+	compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
+	qcom,board-id = <8 0>;
+};
diff --git a/qcom/waipio-mtp-pm8010-overlay.dts b/qcom/waipio-mtp-pm8010-overlay.dts
new file mode 100644
index 00000000..54ea4d28
--- /dev/null
+++ b/qcom/waipio-mtp-pm8010-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "waipio-mtp.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio MTP with PM8010";
+	compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
+	qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
+	qcom,board-id = <0x10008 0>;
+};
diff --git a/qcom/waipio-mtp-pm8010.dts b/qcom/waipio-mtp-pm8010.dts
new file mode 100644
index 00000000..a0dc118e
--- /dev/null
+++ b/qcom/waipio-mtp-pm8010.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipio.dtsi"
+#include "waipio-mtp.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio MTP with PM8010";
+	compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
+	qcom,board-id = <0x10008 0>;
+};
diff --git a/qcom/waipio-mtp.dtsi b/qcom/waipio-mtp.dtsi
new file mode 100644
index 00000000..8bc0bbf2
--- /dev/null
+++ b/qcom/waipio-mtp.dtsi
@@ -0,0 +1,182 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "waipio-pmic-overlay.dtsi"
+#include "waipio-thermal-overlay.dtsi"
+
+&ufsphy_mem {
+	compatible = "qcom,ufs-phy-qmp-v4-waipio";
+
+	vdda-phy-supply = <&pm8350_l5>;
+	vdda-pll-supply = <&pm8350_l6>;
+	vdda-phy-max-microamp = <173000>;
+	vdda-pll-max-microamp = <24900>;
+
+	status = "ok";
+};
+
+&ufshc_mem {
+	vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+
+	vcc-supply = <&pm8350_l7>;
+	vcc-max-microamp = <1100000>;
+
+	vccq-supply = <&pm8350_l9>;
+	vccq-max-microamp = <1200000>;
+
+	qcom,vddp-ref-clk-supply = <&pm8350_l9>;
+	qcom,vddp-ref-clk-max-microamp = <100>;
+
+	qcom,vccq-parent-supply = <&pm8350_s12>;
+	qcom,vccq-parent-max-microamp = <210000>;
+
+	status = "ok";
+};
+
+&sdhc_2 {
+	status = "ok";
+	vdd-supply = <&pm8350c_l9>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 800000>;
+
+	vdd-io-supply = <&pm8350c_l6>;
+	qcom,vdd-io-voltage-level = <1800000 2960000>;
+	qcom,vdd-io-current-level = <0 22000>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_on>;
+	pinctrl-1 = <&sdc2_off>;
+
+	cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
+};
+
+&soc {
+	gpio_keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_vol_up_default>;
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&pm8350_gpios 6 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEUP>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+			linux,can-disable;
+		};
+	};
+};
+
+&pm8350b_haptics {
+	status = "ok";
+};
+
+&pm8350c_switch0 {
+	qcom,led-mask = <9>; /* Channels 1 & 4 */
+	qcom,symmetry-en;
+};
+
+&pm8350c_switch1 {
+	qcom,led-mask = <6>; /* Channels 2 & 3 */
+	qcom,symmetry-en;
+};
+
+&pm8350c_switch2 {
+	qcom,led-mask = <15>; /* All Channels */
+	qcom,symmetry-en;
+};
+
+&pm8350c_flash {
+	status = "ok";
+};
+
+&battery_charger {
+	qcom,thermal-mitigation = <3000000 1500000 1000000 500000>;
+	qcom,wireless-fw-name = "idt9415.bin";
+};
+
+&qupv3_se9_i2c {
+	status = "ok";
+	qcom,clk-freq-out = <1000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	nq@28 {
+		compatible = "qcom,sn-nci";
+		reg = <0x28>;
+		qcom,sn-irq = <&tlmm 46 0x00>;
+		qcom,sn-ven = <&tlmm 34 0x00>;
+		qcom,sn-firm = <&tlmm 45 0x00>;
+		qcom,sn-clkreq = <&tlmm 35 0x00>;
+		qcom,sn-vdd-1p8-supply = <&S10B>;
+		qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
+		qcom,sn-vdd-1p8-current = <157000>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <46 0>;
+		interrupt-names = "nfc_irq";
+		pinctrl-names = "nfc_active", "nfc_suspend";
+		pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
+		pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
+	};
+};
+
+&qupv3_se4_i2c {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	status = "ok";
+	qcom,i2c-touch-active = "focaltech,fts_ts";
+
+	focaltech@38 {
+		compatible = "focaltech,fts_ts";
+		reg = <0x38>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <21 0x2008>;
+		focaltech,reset-gpio = <&tlmm 20 0x00>;
+		focaltech,irq-gpio = <&tlmm 21 0x2008>;
+		focaltech,max-touch-number = <5>;
+		focaltech,display-coords = <0 0 1080 2340>;
+		focaltech,touch-type = "primary";
+
+		vdd-supply = <&L3C>;
+
+		pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release";
+		pinctrl-0 = <&ts_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+		pinctrl-2 = <&ts_release>;
+		focaltech,trusted-touch-mode = "vm_mode";
+		focaltech,touch-environment = "pvm";
+		focaltech,trusted-touch-spi-irq = <754>;
+		focaltech,trusted-touch-io-bases = <0xF110000 0xF111000 0xF112000 0xF113000
+						0xF114000 0xF115000 0x990000 0x00910000>;
+		focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000
+						0x1000 0x1000 0x1000 0x4000>;
+	};
+};
+
+&usb0 {
+	usb-role-switch;
+
+	dwc3@a600000 {
+		usb-role-switch;
+		dr_mode = "otg";
+	};
+
+	port {
+		usb_port0: endpoint {
+			remote-endpoint = <&usb_port0_connector>;
+		};
+	};
+};
+
+&ucsi {
+	connector {
+		port {
+			usb_port0_connector: endpoint {
+				remote-endpoint = <&usb_port0>;
+			};
+		};
+	};
+};
diff --git a/qcom/waipio-pcie.dtsi b/qcom/waipio-pcie.dtsi
new file mode 100644
index 00000000..25277b58
--- /dev/null
+++ b/qcom/waipio-pcie.dtsi
@@ -0,0 +1,562 @@
+#include <dt-bindings/clock/qcom,gcc-waipio.h>
+
+&soc {
+	pcie0: qcom,pcie@1c00000 {
+		compatible = "qcom,pci-msm";
+
+		reg = <0x01c00000 0x3000>,
+			<0x01c06000 0x2000>,
+			<0x60000000 0xf1d>,
+			<0x60000f20 0xa8>,
+			<0x60001000 0x1000>,
+			<0x60100000 0x100000>;
+		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
+
+		cell-index = <0>;
+		linux,pci-domain = <0>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
+			<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
+
+		interrupt-parent = <&pcie0>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+
+		msi-map = <0x0 &gic_its 0x5980 0x1>, /* ITS IRQ 0x5980 */
+			<0x100 &gic_its 0x5981 0x20>; /* ITS IRQ 0x5981 - 0x59a1 */
+
+		perst-gpio = <&tlmm 94 0>;
+		wake-gpio = <&tlmm 96 0>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&pcie0_perst_default
+				&pcie0_clkreq_default
+				&pcie0_wake_default>;
+		pinctrl-1 = <&pcie0_perst_default
+				&pcie0_clkreq_sleep
+				&pcie0_wake_default>;
+
+		gdsc-vdd-supply = <&gcc_pcie_0_gdsc>;
+		vreg-1p8-supply = <&pm8350_l6>;
+		vreg-0p9-supply = <&pm8350_l5>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+		vreg-mx-supply = <&VDD_MXA_LEVEL>;
+		qcom,vreg-1p8-voltage-level = <1200000 1200000 18200>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 80900>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+		qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_NOM
+				100000000>;
+
+		interconnect-names = "icc_path";
+		interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
+
+		clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>,
+			<&clock_rpmh RPMH_CXO_CLK>,
+			<&clock_gcc GCC_PCIE_0_AUX_CLK>,
+			<&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>,
+			<&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+			<&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>,
+			<&clock_gcc GCC_PCIE_0_CLKREF_EN>,
+			<&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+			<&clock_gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+			<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+			<&clock_gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
+			<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
+			<&clock_gcc GCC_PCIE_0_PIPE_CLK_SRC>,
+			<&clock_gcc PCIE_0_PIPE_CLK>;
+		clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
+				"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
+				"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
+				"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
+				"pcie_phy_refgen_clk",
+				"pcie_ddrss_sf_tbu_clk",
+				"pcie_aggre_noc_0_axi_clk",
+				"pcie_aggre_noc_1_axi_clk", "pcie_pipe_clk_mux",
+				"pcie_pipe_clk_ext_src";
+		max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <100000000>,
+					<0>, <0>, <0>, <0>;
+
+		resets = <&clock_gcc GCC_PCIE_0_BCR>,
+			<&clock_gcc GCC_PCIE_0_PHY_BCR>;
+		reset-names = "pcie_0_core_reset",
+				"pcie_0_phy_reset";
+
+		dma-coherent;
+		qcom,smmu-sid-base = <0x1c00>;
+		iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+			<0x100 &apps_smmu 0x1c01 0x1>;
+
+		qcom,boot-option = <0x1>;
+		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
+		qcom,drv-supported;
+		qcom,drv-l1ss-timeout-us = <5000>;
+		qcom,l1-2-th-scale = <2>;
+		qcom,l1-2-th-value = <150>;
+		qcom,slv-addr-space-size = <0x4000000>;
+		qcom,ep-latency = <10>;
+		qcom,num-parf-testbus-sel = <0xb9>;
+
+		qcom,pcie-phy-ver = <104>;
+		qcom,phy-status-offset = <0x214>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0x240>;
+		qcom,phy-sequence = <0x0240 0x03 0x0
+				0x0094 0x08 0x0
+				0x0154 0x34 0x0
+				0x016c 0x08 0x0
+				0x0058 0x0f 0x0
+				0x00a4 0x42 0x0
+				0x0110 0x24 0x0
+				0x011c 0x03 0x0
+				0x0118 0xb4 0x0
+				0x010c 0x02 0x0
+				0x01bc 0x11 0x0
+				0x00bc 0x82 0x0
+				0x00d4 0x03 0x0
+				0x00d0 0x55 0x0
+				0x00cc 0x55 0x0
+				0x00b0 0x1a 0x0
+				0x00ac 0x0a 0x0
+				0x00c4 0x68 0x0
+				0x00e0 0x02 0x0
+				0x00dc 0xaa 0x0
+				0x00d8 0xab 0x0
+				0x00b8 0x34 0x0
+				0x00b4 0x14 0x0
+				0x0158 0x01 0x0
+				0x0074 0x06 0x0
+				0x007c 0x16 0x0
+				0x0084 0x36 0x0
+				0x0078 0x06 0x0
+				0x0080 0x16 0x0
+				0x0088 0x36 0x0
+				0x01b0 0x1e 0x0
+				0x01ac 0xca 0x0
+				0x01b8 0x18 0x0
+				0x01b4 0xa2 0x0
+				0x0050 0x07 0x0
+				0x0010 0x01 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x0ee4 0x20 0x0
+				0x0e84 0x75 0x0
+				0x0e90 0x3f 0x0
+				0x115c 0x7f 0x0
+				0x1160 0xff 0x0
+				0x1164 0xbf 0x0
+				0x1168 0x3f 0x0
+				0x116c 0xd8 0x0
+				0x1170 0xdc 0x0
+				0x1174 0xdc 0x0
+				0x1178 0x5c 0x0
+				0x117c 0x34 0x0
+				0x1180 0xa6 0x0
+				0x1190 0x34 0x0
+				0x1194 0x38 0x0
+				0x10d8 0x07 0x0
+				0x0e3c 0x16 0x0
+				0x0e40 0x04 0x0
+				0x10dc 0x00 0x0
+				0x104c 0x08 0x0
+				0x1050 0x08 0x0
+				0x1044 0xf0 0x0
+				0x11a4 0x38 0x0
+				0x10cc 0xf0 0x0
+				0x10f4 0x07 0x0
+				0x1008 0x09 0x0
+				0x1014 0x05 0x0
+				0x0694 0x00 0x0
+				0x0654 0x00 0x0
+				0x06a8 0x0f 0x0
+				0x0048 0x90 0x0
+				0x0620 0xc1 0x0
+				0x0388 0x77 0x0
+				0x0398 0x0b 0x0
+				0x02dc 0x05 0x0
+				0x0200 0x00 0x0
+				0x0244 0x03 0x0>;
+
+		pcie0_rp: pcie0_rp {
+			reg = <0 0 0 0 0>;
+		};
+	};
+
+	pcie0_msi: qcom,pcie0_msi@0x17110040 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0x17110040 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
+		status = "disabled";
+	};
+
+	pcie1: qcom,pcie@1c08000 {
+		compatible = "qcom,pci-msm";
+
+		reg = <0x01c08000 0x3000>,
+			<0x01c0e000 0x2000>,
+			<0x40000000 0xf1d>,
+			<0x40000f20 0xa8>,
+			<0x40001000 0x1000>,
+			<0x40100000 0x100000>;
+		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
+
+		cell-index = <1>;
+		linux,pci-domain = <1>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
+			<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
+
+		interrupt-parent = <&pcie1>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
+
+		msi-parent = <&pcie1_msi>;
+
+		perst-gpio = <&tlmm 97 0>;
+		wake-gpio = <&tlmm 99 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie1_perst_default
+				&pcie1_clkreq_default
+				&pcie1_wake_default>;
+
+		gdsc-vdd-supply = <&gcc_pcie_1_gdsc>;
+		vreg-1p8-supply = <&pm8350_l6>;
+		vreg-0p9-supply = <&pm8450_l2>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+		vreg-mx-supply = <&VDD_MXA_LEVEL>;
+		qcom,target-link-speed = <3>; /* Set max link speed to Gen3 */
+
+		qcom,vreg-1p8-voltage-level = <1200000 1200000 26100>;
+		qcom,vreg-0p9-voltage-level = <880000 912000 193000>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
+		qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				100000000>;
+
+		interconnect-names = "icc_path";
+		interconnects = <&pcie_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
+
+		clocks = <&clock_gcc GCC_PCIE_1_PIPE_CLK>,
+			<&clock_rpmh RPMH_CXO_CLK>,
+			<&clock_gcc GCC_PCIE_1_AUX_CLK>,
+			<&clock_gcc GCC_PCIE_1_CFG_AHB_CLK>,
+			<&clock_gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+			<&clock_gcc GCC_PCIE_1_SLV_AXI_CLK>,
+			<&clock_gcc GCC_PCIE_1_CLKREF_EN>,
+			<&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+			<&clock_gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
+			<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+			<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
+			<&clock_gcc GCC_PCIE_1_PIPE_CLK_SRC>,
+			<&clock_gcc PCIE_1_PIPE_CLK>,
+			<&clock_gcc GCC_PCIE_1_PHY_AUX_CLK>;
+		clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",
+				"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
+				"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
+				"pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",
+				"pcie_phy_refgen_clk",
+				"pcie_ddrss_sf_tbu_clk",
+				"pcie_aggre_noc_1_axi_clk", "pcie_pipe_clk_mux",
+				"pcie_pipe_clk_ext_src", "pcie_phy_aux_clk";
+		max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <100000000>, <0>,
+					<0>, <0>, <0>, <0>;
+
+		resets = <&clock_gcc GCC_PCIE_1_BCR>,
+			<&clock_gcc GCC_PCIE_1_PHY_BCR>;
+		reset-names = "pcie_1_core_reset",
+				"pcie_1_phy_reset";
+
+		dma-coherent;
+		qcom,smmu-sid-base = <0x1c80>;
+		iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+			<0x100 &apps_smmu 0x1c81 0x1>;
+
+		qcom,boot-option = <0x1>;
+		qcom,aux-clk-freq = <17>; /* 16.6 MHz */
+		qcom,eq-fmdc-t-min-phase23 = <1>;
+		qcom,slv-addr-space-size = <0x20000000>;
+		qcom,ep-latency = <10>;
+		qcom,num-parf-testbus-sel = <0xb9>;
+		qcom,l1-2-th-scale = <2>;
+		qcom,l1-2-th-value = <150>;
+
+		qcom,pcie-phy-ver = <105>;
+		qcom,phy-status-offset = <0x1214>;
+		qcom,phy-status-bit = <7>;
+		qcom,phy-power-down-offset = <0x1240>;
+		qcom,phy-sequence = <0x1240 0x03 0x0
+				0x101c 0x31 0x0
+				0x1020 0x01 0x0
+				0x1024 0xde 0x0
+				0x1028 0x07 0x0
+				0x1030 0x97 0x0
+				0x1034 0x0c 0x0
+				0x1044 0x14 0x0
+				0x1048 0x90 0x0
+				0x1058 0x0f 0x0
+				0x1074 0x06 0x0
+				0x1078 0x06 0x0
+				0x107c 0x16 0x0
+				0x1080 0x16 0x0
+				0x1084 0x36 0x0
+				0x1088 0x36 0x0
+				0x1094 0x08 0x0
+				0x10a4 0x46 0x0
+				0x10a8 0x04 0x0
+				0x10ac 0x0a 0x0
+				0x10b0 0x1a 0x0
+				0x10b4 0x14 0x0
+				0x10b8 0x34 0x0
+				0x10bc 0x82 0x0
+				0x10c4 0xd0 0x0
+				0x10cc 0x55 0x0
+				0x10d0 0x55 0x0
+				0x10d4 0x03 0x0
+				0x10d8 0x55 0x0
+				0x10dc 0x55 0x0
+				0x10e0 0x05 0x0
+				0x110c 0x02 0x0
+				0x1154 0x34 0x0
+				0x1158 0x12 0x0
+				0x115c 0x00 0x0
+				0x1168 0x0a 0x0
+				0x116c 0x04 0x0
+				0x119c 0x88 0x0
+				0x1174 0x20 0x0
+				0x117c 0x06 0x0
+				0x11a0 0x14 0x0
+				0x11a8 0x0f 0x0
+				0x0220 0x16 0x0
+				0x03c0 0x38 0x0
+				0x0a20 0x16 0x0
+				0x0bc0 0x38 0x0
+				0x0364 0xcc 0x0
+				0x0368 0x12 0x0
+				0x036c 0xcc 0x0
+				0x0374 0x4a 0x0
+				0x0378 0x29 0x0
+				0x037c 0xc5 0x0
+				0x0380 0xad 0x0
+				0x0384 0xb6 0x0
+				0x0388 0xc0 0x0
+				0x038c 0x1f 0x0
+				0x0390 0xfb 0x0
+				0x0394 0x0f 0x0
+				0x0398 0xc7 0x0
+				0x039c 0xef 0x0
+				0x03a0 0xbf 0x0
+				0x03a4 0xa0 0x0
+				0x03a8 0x81 0x0
+				0x03ac 0xde 0x0
+				0x03b0 0x7f 0x0
+				0x0b64 0xcc 0x0
+				0x0b68 0x12 0x0
+				0x0b6c 0xcc 0x0
+				0x0b74 0x4a 0x0
+				0x0b78 0x29 0x0
+				0x0b7c 0xc5 0x0
+				0x0b80 0xad 0x0
+				0x0b84 0xb6 0x0
+				0x0b88 0xc0 0x0
+				0x0b8c 0x1f 0x0
+				0x0b90 0xfb 0x0
+				0x0b94 0x0f 0x0
+				0x0b98 0xc7 0x0
+				0x0b9c 0xef 0x0
+				0x0ba0 0xbf 0x0
+				0x0ba4 0xa0 0x0
+				0x0ba8 0x81 0x0
+				0x0bac 0xde 0x0
+				0x0bb0 0x7f 0x0
+				0x03b4 0x20 0x0
+				0x022c 0x3f 0x0
+				0x0230 0x37 0x0
+				0x0bb4 0x20 0x0
+				0x0a2c 0x3f 0x0
+				0x0a30 0x37 0x0
+				0x0078 0x05 0x0
+				0x007c 0xf6 0x0
+				0x0878 0x05 0x0
+				0x087c 0xf6 0x0
+				0x0290 0x05 0x0
+				0x0a90 0x05 0x0
+				0x03f8 0x1f 0x0
+				0x0400 0x1f 0x0
+				0x0408 0x1f 0x0
+				0x0410 0x1f 0x0
+				0x0418 0x1f 0x0
+				0x0420 0x1f 0x0
+				0x03f4 0x1f 0x0
+				0x03fc 0x1f 0x0
+				0x0404 0x1f 0x0
+				0x0bf8 0x1f 0x0
+				0x0c00 0x1f 0x0
+				0x0c08 0x1f 0x0
+				0x0c10 0x1f 0x0
+				0x0c18 0x1f 0x0
+				0x0c20 0x1f 0x0
+				0x0bf4 0x1f 0x0
+				0x0bfc 0x1f 0x0
+				0x0c04 0x1f 0x0
+				0x0208 0x0c 0x0
+				0x0a08 0x0c 0x0
+				0x020c 0x0a 0x0
+				0x0a0c 0x0a 0x0
+				0x02dc 0x0a 0x0
+				0x0adc 0x0a 0x0
+				0x0308 0x0b 0x0
+				0x0b08 0x0b 0x0
+				0x027c 0x10 0x0
+				0x0a7c 0x10 0x0
+				0x02b4 0x00 0x0
+				0x0ab4 0x00 0x0
+				0x02ec 0x0f 0x0
+				0x0aec 0x0f 0x0
+				0x02c4 0x00 0x0
+				0x02c8 0x1f 0x0
+				0x0ac4 0x00 0x0
+				0x0ac8 0x1f 0x0
+				0x0030 0x1a 0x0
+				0x0034 0x0c 0x0
+				0x0830 0x1a 0x0
+				0x0834 0x0c 0x0
+				0x141c 0xc1 0x0
+				0x1490 0x00 0x0
+				0x13e0 0x16 0x0
+				0x13e4 0x22 0x0
+				0x1508 0x02 0x0
+				0x14a0 0x16 0x0
+				0x1584 0x28 0x0
+				0x1370 0x2e 0x0
+				0x155c 0x2e 0x0
+				0x1388 0x99 0x0
+				0x1200 0x00 0x0
+				0x1244 0x03 0x0>;
+
+		pcie1_rp: pcie1_rp {
+			reg = <0 0 0 0 0>;
+		};
+	};
+
+	pcie1_msi: qcom,pcie1_msi@17110040 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0x17110040 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 800 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 801 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 802 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 803 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 804 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 805 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 806 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 807 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 808 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 809 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 810 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 811 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 812 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 813 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 814 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 815 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 816 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 817 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 818 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 819 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 820 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 821 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 822 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 823 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 824 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 825 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 826 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 827 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 828 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 829 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 830 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 831 IRQ_TYPE_EDGE_RISING>;
+	};
+};
diff --git a/qcom/waipio-pinctrl.dtsi b/qcom/waipio-pinctrl.dtsi
new file mode 100644
index 00000000..df6b62b8
--- /dev/null
+++ b/qcom/waipio-pinctrl.dtsi
@@ -0,0 +1,2897 @@
+&tlmm {
+	bt_en_sleep: bt_en_sleep {
+		mux {
+			pins = "gpio81";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio81";
+			drive-strength = <2>;
+			output-low;
+			bias-pull-down;
+		};
+	};
+
+	qupv3_se7_2uart_pins: qupv3_se7_2uart_pins {
+		qupv3_se7_2uart_active: qupv3_se7_2uart_active {
+			mux {
+				pins = "gpio26", "gpio27";
+				function = "qup7";
+			};
+
+			config {
+				pins = "gpio26", "gpio27";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se7_2uart_sleep: qupv3_se7_2uart_sleep {
+			mux {
+				pins = "gpio26", "gpio27";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio26", "gpio27";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+	};
+
+	sdc2_on: sdc2_on {
+		clk {
+			pins = "sdc2_clk";
+			bias-disable;
+			drive-strength = <16>;
+		};
+
+		cmd {
+			pins = "sdc2_cmd";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		data {
+			pins = "sdc2_data";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		sd-cd {
+			pins = "gpio92";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+	};
+
+	sdc2_off: sdc2_off {
+		clk {
+			pins = "sdc2_clk";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+		cmd {
+			pins = "sdc2_cmd";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		data {
+			pins = "sdc2_data";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		sd-cd {
+			pins = "gpio92";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+	};
+
+	qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
+		qupv3_se0_i2c_active: qupv3_se0_i2c_active {
+			mux {
+				pins = "gpio0", "gpio1";
+				function = "qup0";
+			};
+
+			config {
+				pins = "gpio0", "gpio1";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
+			mux {
+				pins = "gpio0", "gpio1";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio0", "gpio1";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se0_spi_pins: qupv3_se0_spi_pins {
+		qupv3_se0_spi_active: qupv3_se0_spi_active {
+			mux {
+				pins = "gpio0", "gpio1",
+						"gpio2", "gpio3";
+				function = "qup0";
+			};
+
+			config {
+				pins = "gpio0", "gpio1",
+						"gpio2", "gpio3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
+			mux {
+				pins = "gpio0", "gpio1",
+						"gpio2", "gpio3";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio0", "gpio1",
+						"gpio2", "gpio3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
+		qupv3_se1_i2c_active: qupv3_se1_i2c_active {
+			mux {
+				pins = "gpio4", "gpio5";
+				function = "qup1";
+			};
+
+			config {
+				pins = "gpio4", "gpio5";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
+			mux {
+				pins = "gpio4", "gpio5";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio4", "gpio5";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se1_spi_pins: qupv3_se1_spi_pins {
+		qupv3_se1_spi_active: qupv3_se1_spi_active {
+			mux {
+				pins = "gpio4", "gpio5",
+						"gpio6", "gpio7";
+				function = "qup1";
+			};
+
+			config {
+				pins = "gpio4", "gpio5",
+						"gpio6", "gpio7";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
+			mux {
+				pins = "gpio4", "gpio5",
+						"gpio6", "gpio7";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio4", "gpio5",
+						"gpio6", "gpio7";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
+		qupv3_se2_i2c_active: qupv3_se2_i2c_active {
+			mux {
+				pins = "gpio8", "gpio9";
+				function = "qup2";
+			};
+
+			config {
+				pins = "gpio8", "gpio9";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
+			mux {
+				pins = "gpio8", "gpio9";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio8", "gpio9";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se2_spi_pins: qupv3_se2_spi_pins {
+		qupv3_se2_spi_active: qupv3_se2_spi_active {
+			mux {
+				pins = "gpio8", "gpio9",
+						"gpio10", "gpio11";
+				function = "qup2";
+			};
+
+			config {
+				pins = "gpio8", "gpio9",
+						"gpio10", "gpio11";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
+			mux {
+				pins = "gpio8", "gpio9",
+						"gpio10", "gpio11";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio8", "gpio9",
+						"gpio10", "gpio11";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
+		qupv3_se3_i2c_active: qupv3_se3_i2c_active {
+			mux {
+				pins = "gpio12", "gpio13";
+				function = "qup3";
+			};
+
+			config {
+				pins = "gpio12", "gpio13";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
+			mux {
+				pins = "gpio12", "gpio13";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio12", "gpio13";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se3_spi_pins: qupv3_se3_spi_pins {
+		qupv3_se3_spi_active: qupv3_se3_spi_active {
+			mux {
+				pins = "gpio12", "gpio13",
+						"gpio14", "gpio15";
+				function = "qup3";
+			};
+
+			config {
+				pins = "gpio12", "gpio13",
+						"gpio14", "gpio15";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
+			mux {
+				pins = "gpio12", "gpio13",
+						"gpio14", "gpio15";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio12", "gpio13",
+						"gpio14", "gpio15";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
+		qupv3_se4_i2c_active: qupv3_se4_i2c_active {
+			mux {
+				pins = "gpio16", "gpio17";
+				function = "qup4";
+			};
+
+			config {
+				pins = "gpio16", "gpio17";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
+			mux {
+				pins = "gpio16", "gpio17";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio16", "gpio17";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se4_spi_pins: qupv3_se4_spi_pins {
+		qupv3_se4_spi_active: qupv3_se4_spi_active {
+			mux {
+				pins = "gpio16", "gpio17",
+						"gpio18", "gpio19";
+				function = "qup4";
+			};
+
+			config {
+				pins = "gpio16", "gpio17",
+						"gpio18", "gpio19";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
+			mux {
+				pins = "gpio16", "gpio17",
+						"gpio18", "gpio19";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio16", "gpio17",
+						"gpio18", "gpio19";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
+		qupv3_se5_i2c_active: qupv3_se5_i2c_active {
+			mux {
+				pins = "gpio206", "gpio207";
+				function = "qup5";
+			};
+
+			config {
+				pins = "gpio206", "gpio207";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
+			mux {
+				pins = "gpio206", "gpio207";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio206", "gpio207";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se5_spi_pins: qupv3_se5_spi_pins {
+		qupv3_se5_spi_active: qupv3_se5_spi_active {
+			mux {
+				pins = "gpio206", "gpio207",
+						"gpio84", "gpio85";
+				function = "qup5";
+			};
+
+			config {
+				pins = "gpio206", "gpio207",
+						"gpio84", "gpio85";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
+			mux {
+				pins = "gpio206", "gpio207",
+						"gpio84", "gpio85";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio206", "gpio207",
+						"gpio84", "gpio85";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
+		qupv3_se6_i2c_active: qupv3_se6_i2c_active {
+			mux {
+				pins = "gpio20", "gpio21";
+				function = "qup6";
+			};
+
+			config {
+				pins = "gpio20", "gpio21";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
+			mux {
+				pins = "gpio20", "gpio21";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio20", "gpio21";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se6_spi_pins: qupv3_se6_spi_pins {
+		qupv3_se6_spi_active: qupv3_se6_spi_active {
+			mux {
+				pins = "gpio20", "gpio21",
+						"gpio22", "gpio23";
+				function = "qup6";
+			};
+
+			config {
+				pins = "gpio20", "gpio21",
+						"gpio22", "gpio23";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
+			mux {
+				pins = "gpio20", "gpio21",
+						"gpio22", "gpio23";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio20", "gpio21",
+						"gpio22", "gpio23";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
+		qupv3_se8_i2c_active: qupv3_se8_i2c_active {
+			mux {
+				pins = "gpio28", "gpio29";
+				function = "qup8";
+			};
+
+			config {
+				pins = "gpio28", "gpio29";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
+			mux {
+				pins = "gpio28", "gpio29";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio28", "gpio29";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se8_spi_pins: qupv3_se8_spi_pins {
+		qupv3_se8_spi_active: qupv3_se8_spi_active {
+			mux {
+				pins = "gpio28", "gpio29",
+						"gpio30", "gpio31";
+				function = "qup8";
+			};
+
+			config {
+				pins = "gpio28", "gpio29",
+						"gpio30", "gpio31";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
+			mux {
+				pins = "gpio28", "gpio29",
+						"gpio30", "gpio31";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio28", "gpio29",
+						"gpio30", "gpio31";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
+		qupv3_se9_i2c_active: qupv3_se9_i2c_active {
+			mux {
+				pins = "gpio32", "gpio33";
+				function = "qup9";
+			};
+
+			config {
+				pins = "gpio32", "gpio33";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
+			mux {
+				pins = "gpio32", "gpio33";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio32", "gpio33";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se9_spi_pins: qupv3_se9_spi_pins {
+		qupv3_se9_spi_active: qupv3_se9_spi_active {
+			mux {
+				pins = "gpio32", "gpio33",
+						"gpio34", "gpio35";
+				function = "qup9";
+			};
+
+			config {
+				pins = "gpio32", "gpio33",
+						"gpio34", "gpio35";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
+			mux {
+				pins = "gpio32", "gpio33",
+						"gpio34", "gpio35";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio32", "gpio33",
+						"gpio34", "gpio35";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
+		qupv3_se10_i2c_active: qupv3_se10_i2c_active {
+			mux {
+				pins = "gpio36", "gpio37";
+				function = "qup10";
+			};
+
+			config {
+				pins = "gpio36", "gpio37";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
+			mux {
+				pins = "gpio36", "gpio37";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio36", "gpio37";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se10_spi_pins: qupv3_se10_spi_pins {
+		qupv3_se10_spi_active: qupv3_se10_spi_active {
+			mux {
+				pins = "gpio36", "gpio37",
+						"gpio38", "gpio39";
+				function = "qup10";
+			};
+
+			config {
+				pins = "gpio36", "gpio37",
+						"gpio38", "gpio39";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
+			mux {
+				pins = "gpio36", "gpio37",
+						"gpio38", "gpio39";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio36", "gpio37",
+						"gpio38", "gpio39";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
+		qupv3_se11_i2c_active: qupv3_se11_i2c_active {
+			mux {
+				pins = "gpio40", "gpio41";
+				function = "qup11";
+			};
+
+			config {
+				pins = "gpio40", "gpio41";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
+			mux {
+				pins = "gpio40", "gpio41";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio40", "gpio41";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se11_spi_pins: qupv3_se11_spi_pins {
+		qupv3_se11_spi_active: qupv3_se11_spi_active {
+			mux {
+				pins = "gpio40", "gpio41",
+						"gpio42", "gpio43";
+				function = "qup11";
+			};
+
+			config {
+				pins = "gpio40", "gpio41",
+						"gpio42", "gpio43";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se11_spi_sleep: qupv3_se11_spi_sleep {
+			mux {
+				pins = "gpio40", "gpio41",
+						"gpio42", "gpio43";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio40", "gpio41",
+						"gpio42", "gpio43";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se12_i2c_pins: qupv3_se12_i2c_pins {
+		qupv3_se12_i2c_active: qupv3_se12_i2c_active {
+			mux {
+				pins = "gpio44", "gpio45";
+				function = "qup12";
+			};
+
+			config {
+				pins = "gpio44", "gpio45";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep {
+			mux {
+				pins = "gpio44", "gpio45";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio44", "gpio45";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se12_spi_pins: qupv3_se12_spi_pins {
+		qupv3_se12_spi_active: qupv3_se12_spi_active {
+			mux {
+				pins = "gpio44", "gpio45",
+						"gpio46", "gpio47";
+				function = "qup12";
+			};
+
+			config {
+				pins = "gpio44", "gpio45",
+						"gpio46", "gpio47";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se12_spi_sleep: qupv3_se12_spi_sleep {
+			mux {
+				pins = "gpio44", "gpio45",
+						"gpio46", "gpio47";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio44", "gpio45",
+						"gpio46", "gpio47";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se13_i2c_pins: qupv3_se13_i2c_pins {
+		qupv3_se13_i2c_active: qupv3_se13_i2c_active {
+			mux {
+				pins = "gpio48", "gpio49";
+				function = "qup13";
+			};
+
+			config {
+				pins = "gpio48", "gpio49";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep {
+			mux {
+				pins = "gpio48", "gpio49";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio48", "gpio49";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se13_spi_pins: qupv3_se13_spi_pins {
+		qupv3_se13_spi_active: qupv3_se13_spi_active {
+			mux {
+				pins = "gpio48", "gpio49",
+						"gpio50", "gpio51";
+				function = "qup13";
+			};
+
+			config {
+				pins = "gpio48", "gpio49",
+						"gpio50", "gpio51";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se13_spi_sleep: qupv3_se13_spi_sleep {
+			mux {
+				pins = "gpio48", "gpio49",
+						"gpio50", "gpio51";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio48", "gpio49",
+						"gpio50", "gpio51";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se14_i2c_pins: qupv3_se14_i2c_pins {
+		qupv3_se14_i2c_active: qupv3_se14_i2c_active {
+			mux {
+				pins = "gpio52", "gpio53";
+				function = "qup14";
+			};
+
+			config {
+				pins = "gpio52", "gpio53";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep {
+			mux {
+				pins = "gpio52", "gpio53";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio52", "gpio53";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se14_spi_pins: qupv3_se14_spi_pins {
+		qupv3_se14_spi_active: qupv3_se14_spi_active {
+			mux {
+				pins = "gpio52", "gpio53",
+						"gpio54", "gpio55";
+				function = "qup14";
+			};
+
+			config {
+				pins = "gpio52", "gpio53",
+						"gpio54", "gpio55";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se14_spi_sleep: qupv3_se14_spi_sleep {
+			mux {
+				pins = "gpio52", "gpio53",
+						"gpio54", "gpio55";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio52", "gpio53",
+						"gpio54", "gpio55";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se15_i2c_pins: qupv3_se15_i2c_pins {
+		qupv3_se15_i2c_active: qupv3_se15_i2c_active {
+			mux {
+				pins = "gpio56", "gpio57";
+				function = "qup15";
+			};
+
+			config {
+				pins = "gpio56", "gpio57";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep {
+			mux {
+				pins = "gpio56", "gpio57";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio56", "gpio57";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se15_spi_pins: qupv3_se15_spi_pins {
+		qupv3_se15_spi_active: qupv3_se15_spi_active {
+			mux {
+				pins = "gpio56", "gpio57",
+						"gpio58", "gpio59";
+				function = "qup15";
+			};
+
+			config {
+				pins = "gpio56", "gpio57",
+						"gpio58", "gpio59";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se15_spi_sleep: qupv3_se15_spi_sleep {
+			mux {
+				pins = "gpio56", "gpio57",
+						"gpio58", "gpio59";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio56", "gpio57",
+						"gpio58", "gpio59";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se15_i3c_pins: qupv3_se15_i3c_pins {
+		qupv3_se15_i3c_active: qupv3_se15_i3c_active {
+			mux {
+				pins = "gpio56", "gpio57";
+				function = "ibi_i3c";
+			};
+
+			config {
+				pins = "gpio56", "gpio57";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se15_i3c_sleep: qupv3_se15_i3c_sleep {
+			mux {
+				pins = "gpio56", "gpio57";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio56", "gpio57";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se15_i3c_disable: qupv3_se15_i3c_disable {
+			mux {
+				pins = "gpio56", "gpio57";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio56", "gpio57";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se16_i2c_pins: qupv3_se16_i2c_pins {
+		qupv3_se16_i2c_active: qupv3_se16_i2c_active {
+			mux {
+				pins = "gpio60", "gpio61";
+				function = "qup16";
+			};
+
+			config {
+				pins = "gpio60", "gpio61";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se16_i2c_sleep: qupv3_se16_i2c_sleep {
+			mux {
+				pins = "gpio60", "gpio61";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio60", "gpio61";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se16_spi_pins: qupv3_se16_spi_pins {
+		qupv3_se16_spi_active: qupv3_se16_spi_active {
+			mux {
+				pins = "gpio60", "gpio61",
+						"gpio62", "gpio63";
+				function = "qup16";
+			};
+
+			config {
+				pins = "gpio60", "gpio61",
+						"gpio62", "gpio63";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se16_spi_sleep: qupv3_se16_spi_sleep {
+			mux {
+				pins = "gpio60", "gpio61",
+						"gpio62", "gpio63";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio60", "gpio61",
+						"gpio62", "gpio63";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se17_i2c_pins: qupv3_se17_i2c_pins {
+		qupv3_se17_i2c_active: qupv3_se17_i2c_active {
+			mux {
+				pins = "gpio64", "gpio65";
+				function = "qup17";
+			};
+
+			config {
+				pins = "gpio64", "gpio65";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se17_i2c_sleep: qupv3_se17_i2c_sleep {
+			mux {
+				pins = "gpio64", "gpio65";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio64", "gpio65";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se17_spi_pins: qupv3_se17_spi_pins {
+		qupv3_se17_spi_active: qupv3_se17_spi_active {
+			mux {
+				pins = "gpio64", "gpio65",
+						"gpio66", "gpio67";
+				function = "qup17";
+			};
+
+			config {
+				pins = "gpio64", "gpio65",
+						"gpio66", "gpio67";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se17_spi_sleep: qupv3_se17_spi_sleep {
+			mux {
+				pins = "gpio64", "gpio65",
+						"gpio66", "gpio67";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio64", "gpio65",
+						"gpio66", "gpio67";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se18_i2c_pins: qupv3_se18_i2c_pins {
+		qupv3_se18_i2c_active: qupv3_se18_i2c_active {
+			mux {
+				pins = "gpio68", "gpio69";
+				function = "qup18";
+			};
+
+			config {
+				pins = "gpio68", "gpio69";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se18_i2c_sleep: qupv3_se18_i2c_sleep {
+			mux {
+				pins = "gpio68", "gpio69";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio68", "gpio69";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se18_spi_pins: qupv3_se18_spi_pins {
+		qupv3_se18_spi_active: qupv3_se18_spi_active {
+			mux {
+				pins = "gpio68", "gpio69",
+						"gpio70", "gpio71";
+				function = "qup18";
+			};
+
+			config {
+				pins = "gpio68", "gpio69",
+						"gpio70", "gpio71";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se18_spi_sleep: qupv3_se18_spi_sleep {
+			mux {
+				pins = "gpio68", "gpio69",
+						"gpio70", "gpio71";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio68", "gpio69",
+						"gpio70", "gpio71";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se19_i2c_pins: qupv3_se19_i2c_pins {
+		qupv3_se19_i2c_active: qupv3_se19_i2c_active {
+			mux {
+				pins = "gpio72", "gpio73";
+				function = "qup19";
+			};
+
+			config {
+				pins = "gpio72", "gpio73";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se19_i2c_sleep: qupv3_se19_i2c_sleep {
+			mux {
+				pins = "gpio72", "gpio73";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio72", "gpio73";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se19_spi_pins: qupv3_se19_spi_pins {
+		qupv3_se19_spi_active: qupv3_se19_spi_active {
+			mux {
+				pins = "gpio72", "gpio73",
+						"gpio74", "gpio75";
+				function = "qup19";
+			};
+
+			config {
+				pins = "gpio72", "gpio73",
+						"gpio74", "gpio75";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se19_spi_sleep: qupv3_se19_spi_sleep {
+			mux {
+				pins = "gpio72", "gpio73",
+						"gpio74", "gpio75";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio72", "gpio73",
+						"gpio74", "gpio75";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se20_i2c_pins: qupv3_se20_i2c_pins {
+		qupv3_se20_i2c_active: qupv3_se20_i2c_active {
+			mux {
+				pins = "gpio76", "gpio77";
+				function = "qup20";
+			};
+
+			config {
+				pins = "gpio76", "gpio77";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se20_i2c_sleep: qupv3_se20_i2c_sleep {
+			mux {
+				pins = "gpio76", "gpio77";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio76", "gpio77";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se20_spi_pins: qupv3_se20_spi_pins {
+		qupv3_se20_spi_active: qupv3_se20_spi_active {
+			mux {
+				pins = "gpio76", "gpio77",
+						"gpio78", "gpio79";
+				function = "qup20";
+			};
+
+			config {
+				pins = "gpio76", "gpio77",
+						"gpio78", "gpio79";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se20_spi_sleep: qupv3_se20_spi_sleep {
+			mux {
+				pins = "gpio76", "gpio77",
+						"gpio78", "gpio79";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio76", "gpio77",
+						"gpio78", "gpio79";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se21_i2c_pins: qupv3_se21_i2c_pins {
+		qupv3_se21_i2c_active: qupv3_se21_i2c_active {
+			mux {
+				pins = "gpio80", "gpio81";
+				function = "qup21";
+			};
+
+			config {
+				pins = "gpio80", "gpio81";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se21_i2c_sleep: qupv3_se21_i2c_sleep {
+			mux {
+				pins = "gpio80", "gpio81";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio80", "gpio81";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se21_spi_pins: qupv3_se21_spi_pins {
+		qupv3_se21_spi_active: qupv3_se21_spi_active {
+			mux {
+				pins = "gpio80", "gpio81",
+						"gpio82", "gpio83";
+				function = "qup21";
+			};
+
+			config {
+				pins = "gpio80", "gpio81",
+						"gpio82", "gpio83";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se21_spi_sleep: qupv3_se21_spi_sleep {
+			mux {
+				pins = "gpio80", "gpio81",
+						"gpio82", "gpio83";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio80", "gpio81",
+						"gpio82", "gpio83";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se20_4uart_pins: qupv3_se20_4uart_pins {
+		qupv3_se20_default_cts:
+				qupv3_se20_default_cts {
+			mux {
+				pins = "gpio76";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio76";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se20_default_rtsrx:
+			qupv3_se20_default_rtsrx {
+			mux {
+				pins = "gpio77", "gpio79";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio77", "gpio79";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se20_default_tx:
+			qupv3_se20_default_tx {
+			mux {
+				pins = "gpio78";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio78";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se20_cts: qupv3_se20_cts {
+			mux {
+				pins = "gpio76";
+				function = "qup20";
+			};
+
+			config {
+				pins = "gpio76";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se20_rts: qupv3_se20_rts {
+			mux {
+				pins = "gpio77";
+				function = "qup20";
+			};
+
+			config {
+				pins = "gpio77";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se20_tx: qupv3_se20_tx {
+			mux {
+				pins = "gpio78";
+				function = "qup20";
+			};
+
+			config {
+				pins = "gpio78";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		/* RX to be in gpio mode for sleep config */
+		qupv3_se20_rx_wake: qupv3_se20_rx_wake {
+			mux {
+				pins = "gpio79";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio79";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se20_rx_active: qupv3_se20_rx_active {
+			mux {
+				pins = "gpio79";
+				function = "qup20";
+			};
+
+			config {
+				pins = "gpio79";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	nfc {
+		nfc_int_active: nfc_int_active {
+			/* active state */
+			mux {
+				/* NFC Read Interrupt */
+				pins = "gpio46";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio46";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-down;
+			};
+		};
+
+		nfc_int_suspend: nfc_int_suspend {
+			/* sleep state */
+			mux {
+				/* NFC Read Interrupt */
+				pins = "gpio46";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio46";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-down;
+			};
+		};
+
+		nfc_enable_active: nfc_enable_active {
+			mux {
+				/* Enable, Firmware and Clock request gpios */
+				pins = "gpio34", "gpio45", "gpio35";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio34", "gpio45", "gpio35";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+
+		nfc_enable_suspend: nfc_enable_suspend {
+			mux {
+				pins = "gpio34", "gpio45", "gpio35";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio34", "gpio45", "gpio35";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+	};
+
+	pri_aux_pcm_clk {
+		pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep {
+			mux {
+				pins = "gpio126";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio126";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		pri_aux_pcm_clk_active: pri_aux_pcm_clk_active {
+			mux {
+				pins = "gpio126";
+				function = "mi2s0_sck";
+			};
+
+			config {
+				pins = "gpio126";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	pri_aux_pcm_sync {
+		pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep {
+			mux {
+				pins = "gpio129";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio129";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		pri_aux_pcm_sync_active: pri_aux_pcm_sync_active {
+			mux {
+				pins = "gpio129";
+				function = "mi2s0_ws";
+			};
+
+			config {
+				pins = "gpio129";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	pri_aux_pcm_din {
+		pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep {
+			mux {
+				pins = "gpio127";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio127";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		pri_aux_pcm_din_active: pri_aux_pcm_din_active {
+			mux {
+				pins = "gpio127";
+				function = "mi2s0_data0";
+			};
+
+			config {
+				pins = "gpio127";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	pri_aux_pcm_dout {
+		pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep {
+			mux {
+				pins = "gpio128";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio128";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		pri_aux_pcm_dout_active: pri_aux_pcm_dout_active {
+			mux {
+				pins = "gpio128";
+				function = "mi2s0_data1";
+			};
+
+			config {
+				pins = "gpio128";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	tert_aux_pcm {
+		tert_aux_pcm_clk_sleep: tert_aux_pcm_clk_sleep {
+			mux {
+				pins = "gpio121";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio121";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_aux_pcm_clk_active: tert_aux_pcm_clk_active {
+			mux {
+				pins = "gpio121";
+				function = "mi2s2_sck";
+			};
+
+			config {
+				pins = "gpio121";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+
+		tert_aux_pcm_ws_sleep: tert_aux_pcm_ws_sleep {
+			mux {
+				pins = "gpio123";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio123";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_aux_pcm_ws_active: tert_aux_pcm_ws_active {
+			mux {
+				pins = "gpio123";
+				function = "mi2s2_ws";
+			};
+
+			config {
+				pins = "gpio123";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	tert_aux_pcm_din {
+		tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep {
+			mux {
+				pins = "gpio122";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio122";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_aux_pcm_din_active: tert_aux_pcm_din_active {
+			mux {
+				pins = "gpio122";
+				function = "mi2s2_data0";
+			};
+
+			config {
+				pins = "gpio122";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	tert_aux_pcm_dout {
+		tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep {
+			mux {
+				pins = "gpio124";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio124";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_aux_pcm_dout_active: tert_aux_pcm_dout_active {
+			mux {
+				pins = "gpio124";
+				function = "mi2s2_data1";
+			};
+
+			config {
+				pins = "gpio124";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	pri_tdm_clk {
+		pri_tdm_clk_sleep: pri_tdm_clk_sleep {
+			mux {
+				pins = "gpio126";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio126";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		pri_tdm_clk_active: pri_tdm_clk_active {
+			mux {
+				pins = "gpio126";
+				function = "mi2s0_sck";
+			};
+
+			config {
+				pins = "gpio126";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	pri_tdm_sync {
+		pri_tdm_sync_sleep: pri_tdm_sync_sleep {
+			mux {
+				pins = "gpio129";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio129";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		pri_tdm_sync_active: pri_tdm_sync_active {
+			mux {
+				pins = "gpio129";
+				function = "mi2s0_ws";
+			};
+
+			config {
+				pins = "gpio129";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	pri_tdm_din {
+		pri_tdm_din_sleep: pri_tdm_din_sleep {
+			mux {
+				pins = "gpio127";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio127";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		pri_tdm_din_active: pri_tdm_din_active {
+			mux {
+				pins = "gpio127";
+				function = "mi2s0_data0";
+			};
+
+			config {
+				pins = "gpio127";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	pri_tdm_dout {
+		pri_tdm_dout_sleep: pri_tdm_dout_sleep {
+			mux {
+				pins = "gpio128";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio128";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		pri_tdm_dout_active: pri_tdm_dout_active {
+			mux {
+				pins = "gpio128";
+				function = "mi2s0_data1";
+			};
+
+			config {
+				pins = "gpio128";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	tert_tdm {
+		tert_tdm_clk_sleep: tert_tdm_clk_sleep {
+			mux {
+				pins = "gpio121";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio121";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_tdm_clk_active: tert_tdm_clk_active {
+			mux {
+				pins = "gpio121";
+				function = "mi2s2_sck";
+			};
+
+			config {
+				pins = "gpio121";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+
+		tert_tdm_ws_sleep: tert_tdm_ws_sleep {
+			mux {
+				pins = "gpio123";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio123";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_tdm_ws_active: tert_tdm_ws_active {
+			mux {
+				pins = "gpio123";
+				function = "mi2s2_ws";
+			};
+
+			config {
+				pins = "gpio123";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	tert_tdm_din {
+		tert_tdm_din_sleep: tert_tdm_din_sleep {
+			mux {
+				pins = "gpio122";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio122";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_tdm_din_active: tert_tdm_din_active {
+			mux {
+				pins = "gpio122";
+				function = "mi2s2_data0";
+			};
+
+			config {
+				pins = "gpio122";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	tert_tdm_dout {
+		tert_tdm_dout_sleep: tert_tdm_dout_sleep {
+			mux {
+				pins = "gpio124";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio124";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_tdm_dout_active: tert_tdm_dout_active {
+			mux {
+				pins = "gpio124";
+				function = "mi2s2_data1";
+			};
+
+			config {
+				pins = "gpio124";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	pri_mi2s_mclk {
+		pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep {
+			mux {
+				pins = "gpio125";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio125";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		pri_mi2s_mclk_active: pri_mi2s_mclk_active {
+			mux {
+				pins = "gpio125";
+				function = "pri_mi2s";
+			};
+
+			config {
+				pins = "gpio125";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	pri_mi2s_sck {
+		pri_mi2s_sck_sleep: pri_mi2s_sck_sleep {
+			mux {
+				pins = "gpio126";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio126";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		pri_mi2s_sck_active: pri_mi2s_sck_active {
+			mux {
+				pins = "gpio126";
+				function = "mi2s0_sck";
+			};
+
+			config {
+				pins = "gpio126";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	pri_mi2s_ws {
+		pri_mi2s_ws_sleep: pri_mi2s_ws_sleep {
+			mux {
+				pins = "gpio129";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio129";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		pri_mi2s_ws_active: pri_mi2s_ws_active {
+			mux {
+				pins = "gpio129";
+				function = "mi2s0_ws";
+			};
+
+			config {
+				pins = "gpio129";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	pri_mi2s_sd0 {
+		pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep {
+			mux {
+				pins = "gpio127";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio127";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		pri_mi2s_sd0_active: pri_mi2s_sd0_active {
+			mux {
+				pins = "gpio127";
+				function = "mi2s0_data0";
+			};
+
+			config {
+				pins = "gpio127";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	pri_mi2s_sd1 {
+		pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep {
+			mux {
+				pins = "gpio128";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio128";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		pri_mi2s_sd1_active: pri_mi2s_sd1_active {
+			mux {
+				pins = "gpio128";
+				function = "mi2s0_data1";
+			};
+
+			config {
+				pins = "gpio128";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	sec_mi2s_mclk {
+		sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep {
+			mux {
+				pins = "gpio124";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio124";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		sec_mi2s_mclk_active: sec_mi2s_mclk_active {
+			mux {
+				pins = "gpio124";
+				function = "sec_mi2s";
+			};
+
+			config {
+				pins = "gpio124";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	tert_mi2s_sck {
+		tert_mi2s_sck_sleep: tert_mi2s_sck_sleep {
+			mux {
+				pins = "gpio121";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio121";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_mi2s_sck_active: tert_mi2s_sck_active {
+			mux {
+				pins = "gpio121";
+				function = "mi2s2_sck";
+			};
+
+			config {
+				pins = "gpio121";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	tert_mi2s_ws {
+		tert_mi2s_ws_sleep: tert_mi2s_ws_sleep {
+			mux {
+				pins = "gpio123";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio123";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_mi2s_ws_active: tert_mi2s_ws_active {
+			mux {
+				pins = "gpio123";
+				function = "mi2s2_ws";
+			};
+
+			config {
+				pins = "gpio123";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	tert_mi2s_sd0 {
+		tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep {
+			mux {
+				pins = "gpio122";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio122";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_mi2s_sd0_active: tert_mi2s_sd0_active {
+			mux {
+				pins = "gpio122";
+				function = "mi2s2_data0";
+			};
+
+			config {
+				pins = "gpio122";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	tert_mi2s_sd1 {
+		tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep {
+			mux {
+				pins = "gpio124";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio124";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_mi2s_sd1_active: tert_mi2s_sd1_active {
+			mux {
+				pins = "gpio124";
+				function = "mi2s2_data1";
+			};
+
+			config {
+				pins = "gpio124";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	pm8008i_active: pm8008i_active {
+		mux {
+			pins = "gpio7";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio7";
+			bias-disable;
+			output-high;
+			drive-strength = <2>;
+		};
+	};
+
+	pm8008j_active: pm8008j_active {
+		mux {
+			pins = "gpio11";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio11";
+			bias-disable;
+			output-high;
+			drive-strength = <2>;
+		};
+	};
+
+	/* WSA speaker reset pins */
+	spkr_1_sd_n {
+		spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
+			mux {
+				pins = "gpio1";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio1";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;
+				input-enable;
+			};
+		};
+
+		spkr_1_sd_n_active: spkr_1_sd_n_active {
+			mux {
+				pins = "gpio1";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio1";
+				drive-strength = <16>;   /* 16 mA */
+				bias-disable;
+				output-high;
+			};
+		};
+	};
+
+	spkr_2_sd_n {
+		spkr_2_sd_n_sleep: spkr_2_sd_n_sleep {
+			mux {
+				pins = "gpio89";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio89";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;
+				input-enable;
+			};
+		};
+
+		spkr_2_sd_n_active: spkr_2_sd_n_active {
+			mux {
+				pins = "gpio89";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio89";
+				drive-strength = <16>;   /* 16 mA */
+				bias-disable;
+				output-high;
+			};
+		};
+	};
+
+	spkr2_1_sd_n {
+		spkr2_1_sd_n_sleep: spkr2_1_sd_n_sleep {
+			mux {
+				pins = "gpio71";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio71";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;
+				input-enable;
+			};
+		};
+
+		spkr2_1_sd_n_active: spkr2_1_sd_n_active {
+			mux {
+				pins = "gpio71";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio71";
+				drive-strength = <16>;   /* 16 mA */
+				bias-disable;
+				output-high;
+			};
+		};
+	};
+
+	spkr2_2_sd_n {
+		spkr2_2_sd_n_sleep: spkr2_2_sd_n_sleep {
+			mux {
+				pins = "gpio3";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio3";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;
+				input-enable;
+			};
+		};
+
+		spkr2_2_sd_n_active: spkr2_2_sd_n_active {
+			mux {
+				pins = "gpio3";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio3";
+				drive-strength = <16>;   /* 16 mA */
+				bias-disable;
+				output-high;
+			};
+		};
+	};
+
+	/* WCD reset pin */
+	wcd938x_reset_active: wcd938x_reset_active {
+		mux {
+			pins = "gpio43";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio43";
+			drive-strength = <16>;
+			output-high;
+		};
+	};
+
+	wcd938x_reset_sleep: wcd938x_reset_sleep {
+		mux {
+			pins = "gpio43";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio43";
+			drive-strength = <16>;
+			bias-disable;
+			output-low;
+		};
+	};
+
+	usb_phy_ps: usb_phy_ps {
+		usb3phy_portselect_default: usb3phy_portselect_default {
+			mux {
+				pins = "gpio91";
+				function = "usb_phy";
+			};
+
+			config {
+				pins = "gpio91";
+				bias-disable;
+				drive-strength = <2>;
+			};
+		};
+
+		usb3phy_portselect_gpio: usb3phy_portselect_gpio {
+			mux {
+				pins = "gpio91";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio91";
+				drive-strength = <2>;
+				bias-disable;
+				input-enable;
+			};
+		};
+	};
+
+	cnss_pins {
+		cnss_wlan_en_active: cnss_wlan_en_active {
+			mux {
+				pins = "gpio80";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio80";
+				drive-strength = <16>;
+				output-high;
+				bias-pull-up;
+			};
+		};
+
+		cnss_wlan_en_sleep: cnss_wlan_en_sleep {
+			mux {
+				pins = "gpio80";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio80";
+				drive-strength = <2>;
+				output-low;
+				bias-pull-down;
+			};
+		};
+	};
+
+	pcie0 {
+		pcie0_perst_default: pcie0_perst_default {
+			mux {
+				pins = "gpio94";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio94";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		pcie0_clkreq_default: pcie0_clkreq_default {
+			mux {
+				pins = "gpio95";
+				function = "pcie0_clkreqn";
+			};
+
+			config {
+				pins = "gpio95";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie0_wake_default: pcie0_wake_default {
+			mux {
+				pins = "gpio96";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio96";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie0_clkreq_sleep: pcie0_clkreq_sleep {
+			mux {
+				pins = "gpio95";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio95";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+	};
+
+	pcie1 {
+		pcie1_perst_default: pcie1_perst_default {
+			mux {
+				pins = "gpio97";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio97";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		pcie1_clkreq_default: pcie1_clkreq_default {
+			mux {
+				pins = "gpio98";
+				function = "pcie1_clkreqn";
+			};
+
+			config {
+				pins = "gpio98";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie1_wake_default: pcie1_wake_default {
+			mux {
+				pins = "gpio99";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio99";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+	};
+
+	pmx_sde: pmx_sde {
+		sde_dsi_active: sde_dsi_active {
+			mux {
+				pins = "gpio0";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio0";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable = <0>;   /* no pull */
+			};
+		};
+
+		sde_dsi_suspend: sde_dsi_suspend {
+			mux {
+				pins = "gpio0";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio0";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+			};
+		};
+
+		sde_dsi1_active: sde_dsi1_active {
+			mux {
+				pins = "gpio4";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio4";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable = <0>;   /* no pull */
+			};
+		};
+
+		sde_dsi1_suspend: sde_dsi1_suspend {
+			mux {
+				pins = "gpio4";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio4";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+			};
+		};
+	};
+
+	pmx_sde_te: pmx_sde_te {
+		sde_te_active: sde_te_active {
+			mux {
+				pins = "gpio86";
+				function = "mdp_vsync";
+			};
+
+			config {
+				pins = "gpio86";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+			};
+		};
+
+		sde_te_suspend: sde_te_suspend {
+			mux {
+				pins = "gpio86";
+				function = "mdp_vsync";
+			};
+
+			config {
+				pins = "gpio86";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+			};
+		};
+
+		sde_te1_active: sde_te1_active {
+			mux {
+				pins = "gpio87";
+				function = "mdp_vsync";
+			};
+
+			config {
+				pins = "gpio87";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+			};
+		};
+
+		sde_te1_suspend: sde_te1_suspend {
+			mux {
+				pins = "gpio87";
+				function = "mdp_vsync";
+			};
+
+			config {
+				pins = "gpio87";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+			};
+		};
+	};
+
+	/* touchscreen pins */
+	pmx_ts_active {
+		ts_active: ts_active {
+			mux {
+				pins = "gpio20", "gpio21";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio20", "gpio21";
+				drive-strength = <8>;
+				bias-pull-up;
+			};
+		};
+	};
+
+	pmx_ts_reset_suspend {
+		ts_reset_suspend: ts_reset_suspend {
+			mux {
+				pins = "gpio20";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio20";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+	};
+
+	pmx_ts_int_suspend {
+		ts_int_suspend: ts_int_suspend {
+			mux {
+				pins = "gpio21";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio21";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+	};
+
+	pmx_ts_release {
+		ts_release: ts_release {
+			mux {
+				pins = "gpio20", "gpio21";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio20", "gpio21";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	ap2mdm {
+		ap2mdm_active: ap2mdm_active {
+			mux {
+				/* ap2mdm-status
+				 * ap2mdm-errfatal
+				 */
+				pins = "gpio41", "gpio37";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio41", "gpio37";
+				drive-strength = <16>;
+				bias-disable;
+			};
+		};
+
+		ap2mdm_sleep: ap2mdm_sleep {
+			mux {
+				/* ap2mdm-status
+				 * ap2mdm-errfatal
+				 */
+				pins = "gpio41", "gpio37";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio41", "gpio37";
+				drive-strength = <8>;
+				bias-disable;
+			};
+		};
+	};
+
+	mdm2ap {
+		mdm2ap_active: mdm2ap_active {
+			mux {
+				/* mdm2ap-status
+				 * mdm2ap-errfatal
+				 */
+				pins = "gpio40", "gpio36";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio40", "gpio36";
+				drive-strength = <16>;
+				bias-disable;
+			};
+		};
+
+		mdm2ap_sleep: mdm2ap_sleep {
+			mux {
+				/* mdm2ap-status
+				 * mdm2ap-errfatal
+				 */
+				pins = "gpio40", "gpio36";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio40", "gpio36";
+				drive-strength = <8>;
+				bias-disable;
+			};
+		};
+	};
+};
diff --git a/qcom/waipio-pm8008.dtsi b/qcom/waipio-pm8008.dtsi
new file mode 100644
index 00000000..2d5acc9e
--- /dev/null
+++ b/qcom/waipio-pm8008.dtsi
@@ -0,0 +1,224 @@
+/* Waipio configurations for PM8008I and PM8008J connected via I2C */
+
+/ {
+	qcom,pmic-id = <0x2f 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
+	qcom,pmic-id-size = <8>;
+};
+
+/*
+ * Each QUP device that's a parent to PMIC must be listed as a critical device
+ * to GCC.
+ */
+&clock_gcc {
+	qcom,critical-devices = <&qupv3_se5_i2c>;
+};
+
+&qupv3_se5_i2c {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "ok";
+
+	pm8008i@8 {
+		compatible = "qcom,i2c-pmic";
+		reg = <0x8>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pm8008i_active>;
+
+		pm8008-chip@900 {
+			compatible = "qcom,pm8008-chip";
+			reg = <0x900>;
+
+			PM8008I_EN: qcom,pm8008-chip-en {
+				regulator-name = "pm8008i-chip-en";
+			};
+		};
+
+		qcom,revid@100 {
+			compatible = "qcom,qpnp-revid";
+			reg = <0x100>;
+		};
+	};
+
+	pm8008i@9 {
+		compatible = "qcom,i2c-pmic";
+		reg = <0x9>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,pm8008i-regulator {
+			compatible = "qcom,pm8008-regulator";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pm8008_en-supply = <&PM8008I_EN>;
+			vdd_l1_l2-supply = <&S12B>;
+			vdd_l3_l4-supply = <&BOB>;
+			vdd_l5-supply = <&S1C>;
+			vdd_l6-supply = <&BOB>;
+			vdd_l7-supply = <&BOB>;
+
+			L1I: pm8008i_l1: regulator@4000 {
+				reg = <0x4000>;
+				regulator-name = "pm8008i_l1";
+				regulator-min-microvolt = <480000>;
+				regulator-max-microvolt = <1104000>;
+				qcom,min-dropout-voltage = <24000>;
+				qcom,hpm-min-load = <30000>;
+			};
+
+			L2I: pm8008i_l2: regulator@4100 {
+				reg = <0x4100>;
+				regulator-name = "pm8008i_l2";
+				regulator-min-microvolt = <1056000>;
+				regulator-max-microvolt = <1056000>;
+				qcom,min-dropout-voltage = <56000>;
+				qcom,hpm-min-load = <30000>;
+			};
+
+			L3I: pm8008i_l3: regulator@4200 {
+				reg = <0x4200>;
+				regulator-name = "pm8008i_l3";
+				regulator-min-microvolt = <2784000>;
+				regulator-max-microvolt = <2904000>;
+				qcom,min-dropout-voltage = <224000>;
+			};
+
+			L4I: pm8008i_l4: regulator@4300 {
+				reg = <0x4300>;
+				regulator-name = "pm8008i_l4";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				qcom,min-dropout-voltage = <152000>;
+			};
+
+			L5I: pm8008i_l5: regulator@4400 {
+				reg = <0x4400>;
+				regulator-name = "pm8008i_l5";
+				regulator-min-microvolt = <1776000>;
+				regulator-max-microvolt = <1800000>;
+				qcom,min-dropout-voltage = <24000>;
+			};
+
+			L6I: pm8008i_l6: regulator@4500 {
+				reg = <0x4500>;
+				regulator-name = "pm8008i_l6";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				qcom,min-dropout-voltage = <208000>;
+			};
+
+			L7I: pm8008i_l7: regulator@4600 {
+				reg = <0x4600>;
+				regulator-name = "pm8008i_l7";
+				regulator-min-microvolt = <2712000>;
+				regulator-max-microvolt = <2960000>;
+				qcom,min-dropout-voltage = <296000>;
+			};
+		};
+	};
+
+	pm8008j@c {
+		compatible = "qcom,i2c-pmic";
+		reg = <0xc>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pm8008j_active>;
+
+		pm8008-chip@900 {
+			compatible = "qcom,pm8008-chip";
+			reg = <0x900>;
+
+			PM8008J_EN: qcom,pm8008-chip-en {
+				regulator-name = "pm8008j-chip-en";
+			};
+		};
+
+		qcom,revid@100 {
+			compatible = "qcom,qpnp-revid";
+			reg = <0x100>;
+		};
+	};
+
+	pm8008j@d {
+		compatible = "qcom,i2c-pmic";
+		reg = <0xd>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,pm8008j-regulator {
+			compatible = "qcom,pm8008-regulator";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pm8008_en-supply = <&PM8008J_EN>;
+			vdd_l1_l2-supply = <&S12B>;
+			vdd_l3_l4-supply = <&S1C>;
+			vdd_l5-supply = <&BOB>;
+			vdd_l6-supply = <&BOB>;
+			vdd_l7-supply = <&BOB>;
+
+			L1J: pm8008j_l1: regulator@4000 {
+				reg = <0x4000>;
+				regulator-name = "pm8008j_l1";
+				regulator-min-microvolt = <1104000>;
+				regulator-max-microvolt = <1104000>;
+				qcom,min-dropout-voltage = <64000>;
+				qcom,hpm-min-load = <30000>;
+			};
+
+			L2J: pm8008j_l2: regulator@4100 {
+				reg = <0x4100>;
+				regulator-name = "pm8008j_l2";
+				regulator-min-microvolt = <1056000>;
+				regulator-max-microvolt = <1056000>;
+				qcom,min-dropout-voltage = <24000>;
+				qcom,hpm-min-load = <30000>;
+			};
+
+			L3J: pm8008j_l3: regulator@4200 {
+				reg = <0x4200>;
+				regulator-name = "pm8008j_l3";
+				regulator-min-microvolt = <1576000>;
+				regulator-max-microvolt = <1800000>;
+				qcom,min-dropout-voltage = <224000>;
+			};
+
+			L4J: pm8008j_l4: regulator@4300 {
+				reg = <0x4300>;
+				regulator-name = "pm8008j_l4";
+				regulator-min-microvolt = <1608000>;
+				regulator-max-microvolt = <1800000>;
+				qcom,min-dropout-voltage = <192000>;
+			};
+
+			L5J: pm8008j_l5: regulator@4400 {
+				reg = <0x4400>;
+				regulator-name = "pm8008j_l5";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				qcom,min-dropout-voltage = <56000>;
+			};
+
+			L6J: pm8008j_l6: regulator@4500 {
+				reg = <0x4500>;
+				regulator-name = "pm8008j_l6";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				qcom,min-dropout-voltage = <120000>;
+			};
+
+			L7J: pm8008j_l7: regulator@4600 {
+				reg = <0x4600>;
+				regulator-name = "pm8008j_l7";
+				regulator-min-microvolt = <2912000>;
+				regulator-max-microvolt = <3304000>;
+				qcom,min-dropout-voltage = <96000>;
+			};
+		};
+	};
+};
diff --git a/qcom/waipio-pm8010-i2c.dtsi b/qcom/waipio-pm8010-i2c.dtsi
new file mode 100644
index 00000000..7015ae75
--- /dev/null
+++ b/qcom/waipio-pm8010-i2c.dtsi
@@ -0,0 +1,224 @@
+/* Waipio configurations for PM8010I and PM8010J connected via I2C */
+
+/ {
+	qcom,pmic-id = <0x2f 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
+	qcom,pmic-id-size = <8>;
+};
+
+/*
+ * Each QUP device that's a parent to PMIC must be listed as a critical device
+ * to GCC.
+ */
+&clock_gcc {
+	qcom,critical-devices = <&qupv3_se5_i2c>;
+};
+
+&qupv3_se5_i2c {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "ok";
+
+	pm8010i@8 {
+		compatible = "qcom,i2c-pmic";
+		reg = <0x8>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pm8008i_active>;
+
+		pm8010-chip@900 {
+			compatible = "qcom,pm8008-chip";
+			reg = <0x900>;
+
+			PM8010I_EN: qcom,pm8008-chip-en {
+				regulator-name = "pm8010i-chip-en";
+			};
+		};
+
+		qcom,revid@100 {
+			compatible = "qcom,qpnp-revid";
+			reg = <0x100>;
+		};
+	};
+
+	pm8010i@9 {
+		compatible = "qcom,i2c-pmic";
+		reg = <0x9>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,pm8010i-regulator {
+			compatible = "qcom,pm8010-regulator";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pm8008_en-supply = <&PM8010I_EN>;
+			vdd_l1_l2-supply = <&S12B>;
+			vdd_l3_l4-supply = <&BOB>;
+			vdd_l5-supply = <&S1C>;
+			vdd_l6-supply = <&BOB>;
+			vdd_l7-supply = <&BOB>;
+
+			L1I: pm8010i_l1: regulator@4000 {
+				reg = <0x4000>;
+				regulator-name = "pm8010i_l1";
+				regulator-min-microvolt = <480000>;
+				regulator-max-microvolt = <1104000>;
+				qcom,min-dropout-voltage = <24000>;
+				qcom,hpm-min-load = <30000>;
+			};
+
+			L2I: pm8010i_l2: regulator@4100 {
+				reg = <0x4100>;
+				regulator-name = "pm8010i_l2";
+				regulator-min-microvolt = <1056000>;
+				regulator-max-microvolt = <1056000>;
+				qcom,min-dropout-voltage = <56000>;
+				qcom,hpm-min-load = <30000>;
+			};
+
+			L3I: pm8010i_l3: regulator@4200 {
+				reg = <0x4200>;
+				regulator-name = "pm8010i_l3";
+				regulator-min-microvolt = <2784000>;
+				regulator-max-microvolt = <2904000>;
+				qcom,min-dropout-voltage = <224000>;
+			};
+
+			L4I: pm8010i_l4: regulator@4300 {
+				reg = <0x4300>;
+				regulator-name = "pm8010i_l4";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				qcom,min-dropout-voltage = <152000>;
+			};
+
+			L5I: pm8010i_l5: regulator@4400 {
+				reg = <0x4400>;
+				regulator-name = "pm8010i_l5";
+				regulator-min-microvolt = <1776000>;
+				regulator-max-microvolt = <1800000>;
+				qcom,min-dropout-voltage = <24000>;
+			};
+
+			L6I: pm8010i_l6: regulator@4500 {
+				reg = <0x4500>;
+				regulator-name = "pm8010i_l6";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				qcom,min-dropout-voltage = <208000>;
+			};
+
+			L7I: pm8010i_l7: regulator@4600 {
+				reg = <0x4600>;
+				regulator-name = "pm8010i_l7";
+				regulator-min-microvolt = <2712000>;
+				regulator-max-microvolt = <2960000>;
+				qcom,min-dropout-voltage = <296000>;
+			};
+		};
+	};
+
+	pm8010j@c {
+		compatible = "qcom,i2c-pmic";
+		reg = <0xc>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pm8008j_active>;
+
+		pm8010-chip@900 {
+			compatible = "qcom,pm8008-chip";
+			reg = <0x900>;
+
+			PM8010J_EN: qcom,pm8008-chip-en {
+				regulator-name = "pm8010j-chip-en";
+			};
+		};
+
+		qcom,revid@100 {
+			compatible = "qcom,qpnp-revid";
+			reg = <0x100>;
+		};
+	};
+
+	pm8010j@d {
+		compatible = "qcom,i2c-pmic";
+		reg = <0xd>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,pm8010j-regulator {
+			compatible = "qcom,pm8010-regulator";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pm8008_en-supply = <&PM8010J_EN>;
+			vdd_l1_l2-supply = <&S12B>;
+			vdd_l3_l4-supply = <&S1C>;
+			vdd_l5-supply = <&BOB>;
+			vdd_l6-supply = <&BOB>;
+			vdd_l7-supply = <&BOB>;
+
+			L1J: pm8010j_l1: regulator@4000 {
+				reg = <0x4000>;
+				regulator-name = "pm8010j_l1";
+				regulator-min-microvolt = <1104000>;
+				regulator-max-microvolt = <1104000>;
+				qcom,min-dropout-voltage = <64000>;
+				qcom,hpm-min-load = <30000>;
+			};
+
+			L2J: pm8010j_l2: regulator@4100 {
+				reg = <0x4100>;
+				regulator-name = "pm8010j_l2";
+				regulator-min-microvolt = <1056000>;
+				regulator-max-microvolt = <1056000>;
+				qcom,min-dropout-voltage = <24000>;
+				qcom,hpm-min-load = <30000>;
+			};
+
+			L3J: pm8010j_l3: regulator@4200 {
+				reg = <0x4200>;
+				regulator-name = "pm8010j_l3";
+				regulator-min-microvolt = <1576000>;
+				regulator-max-microvolt = <1800000>;
+				qcom,min-dropout-voltage = <224000>;
+			};
+
+			L4J: pm8010j_l4: regulator@4300 {
+				reg = <0x4300>;
+				regulator-name = "pm8010j_l4";
+				regulator-min-microvolt = <1608000>;
+				regulator-max-microvolt = <1800000>;
+				qcom,min-dropout-voltage = <192000>;
+			};
+
+			L5J: pm8010j_l5: regulator@4400 {
+				reg = <0x4400>;
+				regulator-name = "pm8010j_l5";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				qcom,min-dropout-voltage = <56000>;
+			};
+
+			L6J: pm8010j_l6: regulator@4500 {
+				reg = <0x4500>;
+				regulator-name = "pm8010j_l6";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				qcom,min-dropout-voltage = <120000>;
+			};
+
+			L7J: pm8010j_l7: regulator@4600 {
+				reg = <0x4600>;
+				regulator-name = "pm8010j_l7";
+				regulator-min-microvolt = <2912000>;
+				regulator-max-microvolt = <3304000>;
+				qcom,min-dropout-voltage = <96000>;
+			};
+		};
+	};
+};
diff --git a/qcom/waipio-pm8010-spmi.dtsi b/qcom/waipio-pm8010-spmi.dtsi
new file mode 100644
index 00000000..1cbfe0d4
--- /dev/null
+++ b/qcom/waipio-pm8010-spmi.dtsi
@@ -0,0 +1,319 @@
+/* Waipio configurations for PM8010I and PM8010J connected via SPMI */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+	qcom,pmic-id = <0x2f 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x41 0x41>;
+	qcom,pmic-id-size = <10>;
+};
+
+&apps_rsc {
+	rpmh-regulator-ldoi2 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoi2";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L2I: pm8010i_l2: regulator-pm8010i-l2 {
+			regulator-name = "pm8010i_l2";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1056000>;
+			regulator-max-microvolt = <1056000>;
+			qcom,init-voltage = <1056000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoi3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoi3";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L3I: pm8010i_l3: regulator-pm8010i-l3 {
+			regulator-name = "pm8010i_l3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2904000>;
+			regulator-max-microvolt = <2904000>;
+			qcom,init-voltage = <2904000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoi4 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoi4";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L4I: pm8010i_l4: regulator-pm8010i-l4 {
+			regulator-name = "pm8010i_l4";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			qcom,init-voltage = <2800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoi6 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoi6";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L6I: pm8010i_l6: regulator-pm8010i-l6 {
+			regulator-name = "pm8010i_l6";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			qcom,init-voltage = <2800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoi7 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoi7";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L7I: pm8010i_l7: regulator-pm8010i-l7 {
+			regulator-name = "pm8010i_l7";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <2960000>;
+			qcom,init-voltage = <2960000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoj1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoj1";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L1J: pm8010j_l1: regulator-pm8010j-l1 {
+			regulator-name = "pm8010j_l1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1104000>;
+			regulator-max-microvolt = <1104000>;
+			qcom,init-voltage = <1104000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoj2 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoj2";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L2J: pm8010j_l2: regulator-pm8010j-l2 {
+			regulator-name = "pm8010j_l2";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1056000>;
+			regulator-max-microvolt = <1056000>;
+			qcom,init-voltage = <1056000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoj3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoj3";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L3J: pm8010j_l3: regulator-pm8010j-l3 {
+			regulator-name = "pm8010j_l3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoj4 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoj4";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L4J: pm8010j_l4: regulator-pm8010j-l4 {
+			regulator-name = "pm8010j_l4";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoj5 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoj5";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L5J: pm8010j_l5: regulator-pm8010j-l5 {
+			regulator-name = "pm8010j_l5";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			qcom,init-voltage = <2800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoj6 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoj6";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L6J: pm8010j_l6: regulator-pm8010j-l6 {
+			regulator-name = "pm8010j_l6";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			qcom,init-voltage = <2800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoj7 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoj7";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L7J: pm8010j_l7: regulator-pm8010j-l7 {
+			regulator-name = "pm8010j_l7";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <3304000>;
+			regulator-max-microvolt = <3304000>;
+			qcom,init-voltage = <3304000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&spmi_bus {
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pm8010@8 {
+		compatible = "qcom,spmi-pmic";
+		reg = <8 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8010i_tz: qcom,temp-alarm@2400 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0x2400>;
+			interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+	};
+
+	qcom,pm8010@9 {
+		compatible = "qcom,spmi-pmic";
+		reg = <9 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8010j_tz: qcom,temp-alarm@2400 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0x2400>;
+			interrupts = <0x9 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+	};
+};
+
+&thermal_zones {
+	pm8010i_tz {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8010i_tz>;
+
+		trips {
+			trip0 {
+				temperature = <95000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			trip1 {
+				temperature = <115000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+
+			trip2 {
+				temperature = <145000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+		};
+	};
+
+	pm8010j_tz {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8010j_tz>;
+
+		trips {
+			trip0 {
+				temperature = <95000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			trip1 {
+				temperature = <115000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+
+			trip2 {
+				temperature = <145000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+		};
+	};
+};
diff --git a/qcom/waipio-pmic-overlay.dtsi b/qcom/waipio-pmic-overlay.dtsi
new file mode 100644
index 00000000..35dc575d
--- /dev/null
+++ b/qcom/waipio-pmic-overlay.dtsi
@@ -0,0 +1,467 @@
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-smb139x.h>
+
+#include "pmk8350.dtsi"
+#include "pm8350.dtsi"
+#include "pm8350c.dtsi"
+#include "pm8350b.dtsi"
+#include "pmr735a.dtsi"
+#include "pmr735b.dtsi"
+#include "pm8450.dtsi"
+
+&pmk8350 {
+	/delete-node/ pon_pbs@800;
+	/delete-node/ pon_hlos@1300;
+
+	pon_hlos@1300 {
+		compatible = "qcom,pm8998-pon";
+		reg = <0x1300>, <0x800>;
+		reg-names = "pon_hlos", "pon_pbs";
+
+		pwrkey {
+			compatible = "qcom,pmk8350-pwrkey";
+			interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
+			linux,code = <KEY_POWER>;
+		};
+
+		resin {
+			compatible = "qcom,pmk8350-resin";
+			interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
+			linux,code = <KEY_VOLUMEDOWN>;
+		};
+	};
+};
+
+&pm8350_gpios {
+	pm8350_rear_tof_therm {
+		pm8350_rear_tof_therm_default: pm8350_rear_tof_therm_default {
+			pins = "gpio1";
+			bias-high-impedance;
+		};
+	};
+
+	key_vol_up {
+		key_vol_up_default: key_vol_up_default {
+			pins = "gpio6";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+			power-source = <1>;
+		};
+	};
+};
+
+&pm8350c_gpios {
+	lcd_backlight_ctrl {
+		lcd_backlight_ctrl_default: lcd_backlight_ctrl_default {
+			pins = "gpio8";
+			function = "func1";
+			input-disable;
+			output-enable;
+			bias-disable;
+			power-source = <1>;       /* 1.8V */
+			qcom,drive-strength = <2>;
+		};
+	};
+};
+
+&pmk8350_sdam_2 {
+	hap_cl_brake: cl_brake@7c {
+		reg = <0x7c 0x1>;
+		bits = <0 8>;
+	};
+};
+
+&pm8350b_haptics {
+	nvmem-cell-names = "hap_cl_brake";
+	nvmem-cells = <&hap_cl_brake>;
+	nvmem-names = "hap_cfg_sdam";
+	nvmem = <&pmk8350_sdam_46>;
+	qcom,pbs-client = <&pm8350b_pbs2>;
+};
+
+&soc {
+	reboot_reason {
+		compatible = "qcom,reboot-reason";
+		nvmem-cells = <&restart_reason>;
+		nvmem-cell-names = "restart_reason";
+	};
+
+	pmic-pon-log {
+		compatible = "qcom,pmic-pon-log";
+		nvmem = <&pmk8350_sdam_5>;
+		nvmem-names = "pon_log";
+	};
+};
+
+&pmk8350_vadc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pm8350_rear_tof_therm_default>;
+
+	pm8350_msm_therm {
+		reg = <PM8350_ADC7_AMUX_THM1_100K_PU>;
+		label = "pm8350_msm_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm8350_cam_flash_therm {
+		reg = <PM8350_ADC7_AMUX_THM2_100K_PU>;
+		label = "pm8350_cam_flash_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm8350_hot_pocket_therm {
+		reg = <PM8350_ADC7_AMUX_THM3_100K_PU>;
+		label = "pm8350_hot_pocket_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm8350_wide_rfc_therm {
+		reg = <PM8350_ADC7_AMUX_THM4_100K_PU>;
+		label = "pm8350_wide_rfc_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm8350_rear_tof_therm {
+		reg = <PM8350_ADC7_AMUX_THM5_100K_PU>;
+		label = "pm8350_rear_tof_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm8350b_usb_conn_therm {
+		reg = <PM8350B_ADC7_AMUX_THM4_100K_PU>;
+		label = "pm8350b_usb_conn_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm8350b_wl_chg_therm {
+		reg = <PM8350B_ADC7_GPIO2_100K_PU>;
+		label = "pm8350b_wl_chg_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm8350b_chg_temp {
+		reg = <PM8350B_ADC7_CHG_TEMP>;
+		label = "pm8350b_chg_temp";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm8350b_iin_fb {
+		reg = <PM8350B_ADC7_IIN_FB>;
+		label = "pm8350b_iin_fb";
+		qcom,pre-scaling = <32 100>;
+	};
+
+	pm8350b_ichg_fb {
+		reg = <PM8350B_ADC7_ICHG_FB>;
+		label = "pm8350b_ichg_fb";
+		qcom,pre-scaling = <1000 305185>;
+	};
+
+	pm8350b_usb_in_v_div_16 {
+		reg = <PM8350B_ADC7_USB_IN_V_16>;
+		label = "pm8350b_usb_in_v_div_16";
+		qcom,pre-scaling = <1 16>;
+	};
+
+	smb139x_1_smb_temp {
+		reg = <SMB1394_1_ADC7_SMB_TEMP>;
+		label = "smb139x_1_smb_temp";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	smb139x_1_ichg_smb {
+		reg = <SMB1394_1_ADC7_ICHG_SMB>;
+		label = "smb139x_1_ichg_smb";
+		qcom,pre-scaling = <16 100>;
+	};
+
+	smb139x_1_iin_smb {
+		reg = <SMB1394_1_ADC7_IIN_SMB>;
+		label = "smb139x_1_iin_smb";
+		qcom,pre-scaling = <32 100>;
+	};
+
+	smb139x_2_smb_temp {
+		reg = <SMB1394_2_ADC7_SMB_TEMP>;
+		label = "smb139x_2_smb_temp";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	smb139x_2_ichg_smb {
+		reg = <SMB1394_2_ADC7_ICHG_SMB>;
+		label = "smb139x_2_ichg_smb";
+		qcom,pre-scaling = <16 100>;
+	};
+
+	smb139x_2_iin_smb {
+		reg = <SMB1394_2_ADC7_IIN_SMB>;
+		label = "smb139x_2_iin_smb";
+		qcom,pre-scaling = <32 100>;
+	};
+};
+
+&pm8350_tz {
+	io-channels = <&pmk8350_vadc PM8350_ADC7_DIE_TEMP>;
+	io-channel-names = "thermal";
+};
+
+&pm8350b_tz {
+	io-channels = <&pmk8350_vadc PM8350B_ADC7_DIE_TEMP>;
+	io-channel-names = "thermal";
+};
+
+&pmr735a_tz {
+	io-channels = <&pmk8350_vadc PMR735A_ADC7_DIE_TEMP>;
+	io-channel-names = "thermal";
+};
+
+&pmr735b_tz {
+	io-channels = <&pmk8350_vadc PMR735B_ADC7_DIE_TEMP>;
+	io-channel-names = "thermal";
+};
+
+&pmk8350_adc_tm {
+	io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM1_100K_PU>,
+			<&pmk8350_vadc PM8350_ADC7_AMUX_THM2_100K_PU>,
+			<&pmk8350_vadc PM8350_ADC7_AMUX_THM3_100K_PU>,
+			<&pmk8350_vadc PM8350_ADC7_AMUX_THM4_100K_PU>,
+			<&pmk8350_vadc PM8350_ADC7_AMUX_THM5_100K_PU>,
+			<&pmk8350_vadc PM8350B_ADC7_AMUX_THM4_100K_PU>,
+			<&pmk8350_vadc PM8350B_ADC7_GPIO2_100K_PU>,
+			<&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
+
+	pm8350_msm_therm {
+		reg = <PM8350_ADC7_AMUX_THM1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	pm8350_cam_flash_therm {
+		reg = <PM8350_ADC7_AMUX_THM2_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	pm8350_hot_pocket_therm {
+		reg = <PM8350_ADC7_AMUX_THM3_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	pm8350_wide_rfc_therm {
+		reg = <PM8350_ADC7_AMUX_THM4_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	pm8350_rear_tof_therm {
+		reg = <PM8350_ADC7_AMUX_THM5_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	pm8350b_usb_conn_therm {
+		reg = <PM8350B_ADC7_AMUX_THM4_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	pm8350b_wl_chg_therm {
+		reg = <PM8350B_ADC7_GPIO2_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	pmk8350_xo_therm {
+		reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&thermal_zones {
+	skin-msm-therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmk8350_adc_tm PM8350_ADC7_AMUX_THM1_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	camera-therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmk8350_adc_tm PM8350_ADC7_AMUX_THM2_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	hot-pock-therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmk8350_adc_tm PM8350_ADC7_AMUX_THM3_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	rear-cam-therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmk8350_adc_tm PM8350_ADC7_AMUX_THM4_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	tof-therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmk8350_adc_tm PM8350_ADC7_AMUX_THM5_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	conn-therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmk8350_adc_tm PM8350B_ADC7_AMUX_THM4_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	wlc-therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmk8350_adc_tm PM8350B_ADC7_GPIO2_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	xo-therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			xo_config0: xo-config0 {
+				temperature = <78000>;
+				hysteresis = <8000>;
+				type = "passive";
+			};
+
+			xo_config1: xo-config1 {
+				temperature = <80000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			xo_config2: xo-config2 {
+				temperature = <90000>;
+				hysteresis = <10000>;
+				type = "critical";
+			};
+		};
+	};
+};
diff --git a/qcom/waipio-qrd-2s.dtsi b/qcom/waipio-qrd-2s.dtsi
new file mode 100644
index 00000000..2a98fb4e
--- /dev/null
+++ b/qcom/waipio-qrd-2s.dtsi
@@ -0,0 +1,8 @@
+#include "waipio-qrd.dtsi"
+
+&battery_charger {
+	qcom,thermal-mitigation = <10000000 9500000 9000000 8500000 8000000
+				7500000 7000000 6500000 6000000 5500000
+				5000000 4500000 4000000 3500000 3000000
+				2500000 2000000 1500000 1000000 500000>;
+};
diff --git a/qcom/waipio-qrd-pm8008-overlay.dts b/qcom/waipio-qrd-pm8008-overlay.dts
new file mode 100644
index 00000000..7bca0e8e
--- /dev/null
+++ b/qcom/waipio-qrd-pm8008-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "waipio-qrd.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio QRD with PM8008";
+	compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
+	qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
+	qcom,board-id = <0x1000B 0>;
+};
diff --git a/qcom/waipio-qrd-pm8008.dts b/qcom/waipio-qrd-pm8008.dts
new file mode 100644
index 00000000..2364b024
--- /dev/null
+++ b/qcom/waipio-qrd-pm8008.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipio.dtsi"
+#include "waipio-qrd.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio QRD with PM8008";
+	compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
+	qcom,board-id = <11 0>;
+};
diff --git a/qcom/waipio-qrd-pm8010-2s-overlay.dts b/qcom/waipio-qrd-pm8010-2s-overlay.dts
new file mode 100644
index 00000000..2863608c
--- /dev/null
+++ b/qcom/waipio-qrd-pm8010-2s-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "waipio-qrd-2s.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio QRD with PM8010 + 2S";
+	compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
+	qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
+	qcom,board-id = <0x2000b 0>;
+};
diff --git a/qcom/waipio-qrd-pm8010-2s.dts b/qcom/waipio-qrd-pm8010-2s.dts
new file mode 100644
index 00000000..c0bac69d
--- /dev/null
+++ b/qcom/waipio-qrd-pm8010-2s.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipio.dtsi"
+#include "waipio-qrd-2s.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio QRD with PM8010 + 2S";
+	compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
+	qcom,board-id = <0x2000b 0>;
+};
diff --git a/qcom/waipio-qrd-pm8010-overlay.dts b/qcom/waipio-qrd-pm8010-overlay.dts
new file mode 100644
index 00000000..ec7fe36f
--- /dev/null
+++ b/qcom/waipio-qrd-pm8010-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "waipio-qrd.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio QRD with PM8010";
+	compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
+	qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
+	qcom,board-id = <0x1000b 0>;
+};
diff --git a/qcom/waipio-qrd-pm8010.dts b/qcom/waipio-qrd-pm8010.dts
new file mode 100644
index 00000000..ae26154e
--- /dev/null
+++ b/qcom/waipio-qrd-pm8010.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipio.dtsi"
+#include "waipio-qrd.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio QRD with PM8010";
+	compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
+	qcom,board-id = <0x1000b 0>;
+};
diff --git a/qcom/waipio-qrd.dtsi b/qcom/waipio-qrd.dtsi
new file mode 100644
index 00000000..6f5f120d
--- /dev/null
+++ b/qcom/waipio-qrd.dtsi
@@ -0,0 +1,277 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "waipio-pmic-overlay.dtsi"
+#include "waipio-thermal-overlay.dtsi"
+
+&ufsphy_mem {
+	compatible = "qcom,ufs-phy-qmp-v4-waipio";
+
+	vdda-phy-supply = <&pm8350_l5>;
+	vdda-pll-supply = <&pm8350_l6>;
+	vdda-phy-max-microamp = <173000>;
+	vdda-pll-max-microamp = <24900>;
+
+	status = "ok";
+};
+
+&ufshc_mem {
+	vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+
+	vcc-supply = <&pm8350_l7>;
+	vcc-max-microamp = <1100000>;
+
+	vccq-supply = <&pm8350_l9>;
+	vccq-max-microamp = <1200000>;
+
+	qcom,vddp-ref-clk-supply = <&pm8350_l9>;
+	qcom,vddp-ref-clk-max-microamp = <100>;
+
+	qcom,vccq-parent-supply = <&pm8350_s12>;
+	qcom,vccq-parent-max-microamp = <210000>;
+
+	status = "ok";
+};
+
+&sdhc_2 {
+	vdd-supply = <&pm8350c_l9>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 800000>;
+
+	vdd-io-supply = <&pm8350c_l6>;
+	qcom,vdd-io-voltage-level = <1800000 2960000>;
+	qcom,vdd-io-current-level = <0 22000>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_on>;
+	pinctrl-1 = <&sdc2_off>;
+
+	cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
+
+	status = "ok";
+};
+
+&qupv3_se5_i2c {
+	status = "ok";
+};
+
+&soc {
+	gpio_keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_vol_up_default>;
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&pm8350_gpios 6 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEUP>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+			linux,can-disable;
+		};
+	};
+};
+
+&pm8350b_haptics {
+	qcom,vmax-mv = <1300>;
+	qcom,lra-period-us = <5880>;
+	status = "ok";
+
+	effect_0 {
+		/* CLICK */
+		qcom,wf-vmax-mv = <1800>;
+		qcom,wf-pattern-period-us = <5880>;
+	};
+
+	effect_1 {
+		/* DOUBLE_CLICK */
+		qcom,wf-vmax-mv = <1800>;
+		qcom,wf-pattern-period-us = <5880>;
+	};
+
+	effect_2 {
+		/* TICK */
+		qcom,wf-vmax-mv = <1800>;
+		qcom,wf-pattern-period-us = <5880>;
+	};
+
+	effect_3 {
+		/* THUD */
+		qcom,wf-vmax-mv = <1800>;
+		qcom,wf-pattern-period-us = <5880>;
+	};
+
+	effect_4 {
+		/* POP */
+		qcom,wf-vmax-mv = <1800>;
+		qcom,wf-pattern-period-us = <5880>;
+	};
+
+	effect_5 {
+		/* HEAVY CLICK */
+		qcom,wf-vmax-mv = <1800>;
+		qcom,wf-pattern-period-us = <5880>;
+	};
+};
+
+&pm8350c_switch0 {
+	qcom,led-mask = <9>; /* Channels 1 & 4 */
+	qcom,symmetry-en;
+};
+
+&pm8350c_switch1 {
+	qcom,led-mask = <6>; /* Channels 2 & 3 */
+	qcom,symmetry-en;
+};
+
+&pm8350c_switch2 {
+	qcom,led-mask = <15>; /* All Channels */
+	qcom,symmetry-en;
+};
+
+&pm8350c_flash {
+	status = "ok";
+};
+
+&battery_charger {
+	qcom,thermal-mitigation = <11500000 11000000 10500000 10000000 9500000
+				9000000 8500000 8000000 7500000 7000000 6500000
+				6000000 5500000 5000000 4500000 4000000 3500000
+				3000000 2500000 2000000 1500000 1000000 500000>;
+	qcom,wireless-fw-name = "idt9415.bin";
+};
+
+&qupv3_se9_i2c {
+	status = "ok";
+	qcom,clk-freq-out = <1000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	nq@28 {
+		compatible = "qcom,sn-nci";
+		reg = <0x28>;
+		qcom,sn-irq = <&tlmm 46 0x00>;
+		qcom,sn-ven = <&tlmm 34 0x00>;
+		qcom,sn-firm = <&tlmm 45 0x00>;
+		qcom,sn-clkreq = <&tlmm 35 0x00>;
+		qcom,sn-vdd-1p8-supply = <&S10B>;
+		qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
+		qcom,sn-vdd-1p8-current = <157000>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <46 0>;
+		interrupt-names = "nfc_irq";
+		pinctrl-names = "nfc_active", "nfc_suspend";
+		pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
+		pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
+	};
+};
+
+&qupv3_se4_spi {
+	status = "ok";
+	qcom,spi-touch-active = "focaltech,fts_ts";
+	qcom,la-vm;
+
+	focaltech@0 {
+		compatible = "focaltech,fts_ts";
+		reg = <0x0>;
+		spi-max-frequency = <6000000>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <21 0x2008>;
+		focaltech,reset-gpio = <&tlmm 20 0x00>;
+		focaltech,irq-gpio = <&tlmm 21 0x2008>;
+		focaltech,display-coords = <0 0 1080 2340>;
+		focaltech,max-touch-number = <5>;
+		focaltech,ic-type = <0x3658D488>;
+		focaltech,touch-type = "primary";
+
+		vdd-supply = <&L3C>;
+
+		pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release";
+		pinctrl-0 = <&ts_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+		pinctrl-2 = <&ts_release>;
+
+		focaltech,trusted-touch-mode = "vm_mode";
+		focaltech,touch-environment = "pvm";
+		focaltech,trusted-touch-spi-irq = <754>;
+		focaltech,trusted-touch-io-bases = <0xF110000 0xF111000 0xF112000 0xF113000 0xF114000 0xF115000 0x990000 0x00910000>;
+		focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>;
+	};
+};
+
+&qupv3_se5_i2c {
+	status = "ok";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	redriver: redriver@1c {
+		compatible = "onnn,redriver";
+		reg = <0x1c>;
+
+		lane-channel-swap;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb3phy_portselect_gpio>;
+		gpios = <&tlmm 91 0>;
+
+		eq = /bits/ 8 <
+				/* Parameters for USB */
+				0x4 0x4 0x4 0x4
+				/* Parameters for DP */
+				0x6 0x4 0x4 0x6>;
+		flat-gain = /bits/ 8 <
+				/* Parameters for USB */
+				0x3 0x1 0x1 0x3
+				/* Parameters for DP */
+				0x2 0x1 0x1 0x2>;
+		output-comp = /bits/ 8 <
+				/* Parameters for USB */
+				0x3 0x3 0x3 0x3
+				/* Parameters for DP */
+				0x3 0x3 0x3 0x3>;
+		loss-match = /bits/ 8 <
+				/* Parameters for USB */
+				0x1 0x3 0x3 0x1
+				/* Parameters for DP */
+				0x3 0x3 0x3 0x3>;
+	};
+};
+
+&usb_qmp_dp_phy {
+	pinctrl-names = "unused";
+};
+
+&usb0 {
+	usb-role-switch;
+	ssusb_redriver = <&redriver>;
+
+	dwc3@a600000 {
+		usb-role-switch;
+		dr_mode = "otg";
+	};
+
+	port {
+		usb_port0: endpoint {
+			remote-endpoint = <&usb_port0_connector>;
+		};
+	};
+};
+
+&usb2_phy0 {
+	qcom,param-override-seq =
+		<0xe6 0x6c
+		0x0c 0x70
+		0x17 0x74>;
+};
+
+&ucsi {
+	connector {
+		port {
+			usb_port0_connector: endpoint {
+				remote-endpoint = <&usb_port0>;
+			};
+		};
+	};
+};
diff --git a/qcom/waipio-qupv3.dtsi b/qcom/waipio-qupv3.dtsi
new file mode 100644
index 00000000..b3084144
--- /dev/null
+++ b/qcom/waipio-qupv3.dtsi
@@ -0,0 +1,1114 @@
+#include <dt-bindings/interconnect/qcom,waipio.h>
+
+&soc {
+	/* QUPv3 SE Instances
+	 * Qup0 0: SE 0
+	 * Qup0 1: SE 1
+	 * Qup0 2: SE 2
+	 * Qup0 3: SE 3
+	 * Qup0 4: SE 4
+	 * Qup0 5: SE 5
+	 * Qup0 6: SE 6
+	 * Qup0 7: SE 7
+	 * Qup1 0: SE 8
+	 * Qup1 1: SE 9
+	 * Qup1 2: SE 10
+	 * Qup1 3: SE 11
+	 * Qup1 4: SE 12
+	 * Qup1 5: SE 13
+	 * Qup1 6: SE 14
+	 * Qup2 0: SE 15
+	 * Qup2 1: SE 16
+	 * Qup2 2: SE 17
+	 * Qup2 3: SE 18
+	 * Qup2 4: SE 19
+	 * Qup2 5: SE 20
+	 * Qup2 6: SE 21
+	 */
+
+	/* QUPv3_0  wrapper  instance */
+	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
+		compatible = "qcom,qupv3-geni-se";
+		reg = <0x9c0000 0x2000>;
+		qcom,msm-bus,num-paths = <3>;
+		interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
+		interconnects =
+		<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+		<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
+		<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+		iommus = <&apps_smmu 0x5a3 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		dma-coherent;
+		status = "ok";
+	};
+
+	/* GPI Instance */
+	gpi_dma0: qcom,gpi-dma@900000 {
+		compatible = "qcom,gpi-dma";
+		#dma-cells = <5>;
+		reg = <0x900000 0x60000>;
+		reg-names = "gpi-top";
+		iommus = <&apps_smmu 0x5b6 0x0>;
+		qcom,max-num-gpii = <12>;
+		interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,static-gpii-mask = <0x1>;
+		qcom,gpii-mask = <0x7e>;
+		qcom,ev-factor = <2>;
+		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+		qcom,gpi-ee-offset = <0x10000>;
+		qcom,le-vm;
+		status = "ok";
+	};
+
+	/* Debug UART Instance */
+	qupv3_se7_2uart: qcom,qup_uart@99c000 {
+		compatible = "qcom,msm-geni-console";
+		reg = <0x99c000 0x4000>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se7_2uart_active>;
+		pinctrl-1 = <&qupv3_se7_2uart_sleep>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se0_i2c: i2c@980000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x980000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se0_i2c_active>;
+		pinctrl-1 = <&qupv3_se0_i2c_sleep>;
+		dmas = <&gpi_dma0 0 0 3 64 0>,
+			<&gpi_dma0 1 0 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se0_spi: spi@980000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x980000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se0_spi_active>;
+		pinctrl-1 = <&qupv3_se0_spi_sleep>;
+		dmas = <&gpi_dma0 0 0 1 64 0>,
+			<&gpi_dma0 1 0 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se1_i2c: i2c@984000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x984000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se1_i2c_active>;
+		pinctrl-1 = <&qupv3_se1_i2c_sleep>;
+		dmas = <&gpi_dma0 0 1 3 64 0>,
+			<&gpi_dma0 1 1 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se1_spi: spi@984000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x984000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se1_spi_active>;
+		pinctrl-1 = <&qupv3_se1_spi_sleep>;
+		dmas = <&gpi_dma0 0 1 1 64 0>,
+			<&gpi_dma0 1 1 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se2_i2c: i2c@988000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x988000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se2_i2c_active>;
+		pinctrl-1 = <&qupv3_se2_i2c_sleep>;
+		dmas = <&gpi_dma0 0 2 3 64 0>,
+			<&gpi_dma0 1 2 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se2_spi: spi@988000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x988000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se2_spi_active>;
+		pinctrl-1 = <&qupv3_se2_spi_sleep>;
+		dmas = <&gpi_dma0 0 2 1 64 0>,
+			<&gpi_dma0 1 2 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se3_i2c: i2c@98c000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x98c000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se3_i2c_active>;
+		pinctrl-1 = <&qupv3_se3_i2c_sleep>;
+		dmas = <&gpi_dma0 0 3 3 64 0>,
+			<&gpi_dma0 1 3 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se3_spi: spi@98c000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x98c000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se3_spi_active>;
+		pinctrl-1 = <&qupv3_se3_spi_sleep>;
+		dmas = <&gpi_dma0 0 3 1 64 0>,
+			<&gpi_dma0 1 3 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	/* TUI over I2C */
+	qupv3_se4_i2c: i2c@990000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x990000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se4_i2c_active>;
+		pinctrl-1 = <&qupv3_se4_i2c_sleep>;
+		dmas = <&gpi_dma0 0 4 3 64 2>,
+			<&gpi_dma0 1 4 3 64 2>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se4_spi: spi@990000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x990000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se4_spi_active>;
+		pinctrl-1 = <&qupv3_se4_spi_sleep>;
+		dmas = <&gpi_dma0 0 4 1 64 2>,
+			<&gpi_dma0 1 4 1 64 2>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se5_i2c: i2c@994000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x994000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se5_i2c_active>;
+		pinctrl-1 = <&qupv3_se5_i2c_sleep>;
+		dmas = <&gpi_dma0 0 5 3 64 0>,
+			<&gpi_dma0 1 5 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_0>;
+		qcom,shared;
+		status = "disabled";
+	};
+
+	qupv3_se5_spi: spi@994000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x994000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se5_spi_active>;
+		pinctrl-1 = <&qupv3_se5_spi_sleep>;
+		dmas = <&gpi_dma0 0 5 1 64 0>,
+			<&gpi_dma0 1 5 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se6_i2c: i2c@998000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x998000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se6_i2c_active>;
+		pinctrl-1 = <&qupv3_se6_i2c_sleep>;
+		dmas = <&gpi_dma0 0 6 3 64 0>,
+			<&gpi_dma0 1 6 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se6_spi: spi@998000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x998000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se6_spi_active>;
+		pinctrl-1 = <&qupv3_se6_spi_sleep>;
+		dmas = <&gpi_dma0 0 6 1 64 0>,
+			<&gpi_dma0 1 6 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	/* QUPv3_1  wrapper  instance */
+	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
+		compatible = "qcom,qupv3-geni-se";
+		reg = <0xac0000 0x2000>;
+		qcom,msm-bus,num-paths = <3>;
+		interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
+		interconnects =
+		<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
+		<&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>,
+		<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
+		iommus = <&apps_smmu 0x43 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		dma-coherent;
+		status = "ok";
+	};
+
+	/* GPI Instance */
+	gpi_dma1: qcom,gpi-dma@a00000 {
+		compatible = "qcom,gpi-dma";
+		#dma-cells = <5>;
+		reg = <0xa00000 0x60000>;
+		reg-names = "gpi-top";
+		iommus = <&apps_smmu 0x56 0x0>;
+		qcom,max-num-gpii = <12>;
+		interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,gpii-mask = <0x3f>;
+		qcom,ev-factor = <2>;
+		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+		qcom,gpi-ee-offset = <0x10000>;
+		status = "ok";
+	};
+
+	qupv3_se8_i2c: i2c@a80000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa80000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se8_i2c_active>;
+		pinctrl-1 = <&qupv3_se8_i2c_sleep>;
+		dmas = <&gpi_dma1 0 0 3 64 0>,
+			<&gpi_dma1 1 0 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se8_spi: spi@a80000 {
+		compatible = "qcom,spi-geni";
+		reg = <0xa80000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se8_spi_active>;
+		pinctrl-1 = <&qupv3_se8_spi_sleep>;
+		dmas = <&gpi_dma1 0 0 1 64 0>,
+			<&gpi_dma1 1 0 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se9_i2c: i2c@a84000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa84000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se9_i2c_active>;
+		pinctrl-1 = <&qupv3_se9_i2c_sleep>;
+		dmas = <&gpi_dma1 0 1 3 64 0>,
+			<&gpi_dma1 1 1 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se9_spi: spi@a84000 {
+		compatible = "qcom,spi-geni";
+		reg = <0xa84000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se9_spi_active>;
+		pinctrl-1 = <&qupv3_se9_spi_sleep>;
+		dmas = <&gpi_dma1 0 1 1 64 0>,
+			<&gpi_dma1 1 1 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se10_i2c: i2c@a88000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa88000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se10_i2c_active>;
+		pinctrl-1 = <&qupv3_se10_i2c_sleep>;
+		dmas = <&gpi_dma1 0 2 3 64 0>,
+			<&gpi_dma1 1 2 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se10_spi: spi@a88000 {
+		compatible = "qcom,spi-geni";
+		reg = <0xa88000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se10_spi_active>;
+		pinctrl-1 = <&qupv3_se10_spi_sleep>;
+		dmas = <&gpi_dma1 0 2 1 64 0>,
+			<&gpi_dma1 1 2 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se11_i2c: i2c@a8c000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa8c000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se11_i2c_active>;
+		pinctrl-1 = <&qupv3_se11_i2c_sleep>;
+		dmas = <&gpi_dma1 0 3 3 64 0>,
+			<&gpi_dma1 1 3 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se11_spi: spi@a8c000 {
+		compatible = "qcom,spi-geni";
+		reg = <0xa8c000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se11_spi_active>;
+		pinctrl-1 = <&qupv3_se11_spi_sleep>;
+		dmas = <&gpi_dma1 0 3 1 64 0>,
+			<&gpi_dma1 1 3 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se12_i2c: i2c@a90000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa90000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se12_i2c_active>;
+		pinctrl-1 = <&qupv3_se12_i2c_sleep>;
+		dmas = <&gpi_dma1 0 4 3 64 0>,
+			<&gpi_dma1 1 4 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se12_spi: spi@a90000 {
+		compatible = "qcom,spi-geni";
+		reg = <0xa90000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se12_spi_active>;
+		pinctrl-1 = <&qupv3_se12_spi_sleep>;
+		dmas = <&gpi_dma1 0 4 1 64 0>,
+			<&gpi_dma1 1 4 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se13_i2c: i2c@a94000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa94000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se13_i2c_active>;
+		pinctrl-1 = <&qupv3_se13_i2c_sleep>;
+		dmas = <&gpi_dma1 0 5 3 64 0>,
+			<&gpi_dma1 1 5 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se13_spi: spi@a94000 {
+		compatible = "qcom,spi-geni";
+		reg = <0xa94000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se13_spi_active>;
+		pinctrl-1 = <&qupv3_se13_spi_sleep>;
+		dmas = <&gpi_dma1 0 5 1 64 0>,
+			<&gpi_dma1 1 5 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se14_i2c: i2c@a98000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa98000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S6_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se14_i2c_active>;
+		pinctrl-1 = <&qupv3_se14_i2c_sleep>;
+		dmas = <&gpi_dma1 0 6 3 64 0>,
+			<&gpi_dma1 1 6 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se14_spi: spi@a98000 {
+		compatible = "qcom,spi-geni";
+		reg = <0xa98000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S6_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se14_spi_active>;
+		pinctrl-1 = <&qupv3_se14_spi_sleep>;
+		dmas = <&gpi_dma1 0 6 1 64 0>,
+			<&gpi_dma1 1 6 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	/* QUPv3_2  wrapper  instance */
+	qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
+		compatible = "qcom,qupv3-geni-se";
+		reg = <0x8c0000 0x2000>;
+		qcom,msm-bus,num-paths = <3>;
+		interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
+		interconnects =
+		<&clk_virt  MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
+		<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
+		<&aggre2_noc  MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
+		iommus = <&apps_smmu 0x483 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		dma-coherent;
+		status = "ok";
+	};
+
+	/* GPI Instance */
+	gpi_dma2: qcom,gpi-dma@800000 {
+		compatible = "qcom,gpi-dma";
+		#dma-cells = <5>;
+		reg = <0x800000 0x60000>;
+		reg-names = "gpi-top";
+		iommus = <&apps_smmu 0x496 0x0>;
+		qcom,max-num-gpii = <12>;
+		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,gpii-mask = <0x3f>;
+		qcom,ev-factor = <2>;
+		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+		qcom,gpi-ee-offset = <0x10000>;
+		status = "ok";
+	};
+
+	qupv3_se15_i2c: i2c@880000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x880000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S0_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se15_i2c_active>;
+		pinctrl-1 = <&qupv3_se15_i2c_sleep>;
+		dmas = <&gpi_dma2 0 0 3 64 0>,
+			<&gpi_dma2 1 0 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se15_spi: spi@880000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x880000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S0_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se15_spi_active>;
+		pinctrl-1 = <&qupv3_se15_spi_sleep>;
+		dmas = <&gpi_dma2 0 0 1 64 0>,
+			<&gpi_dma2 1 0 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	i3c0: i3c-master@880000 {
+		compatible = "qcom,geni-i3c";
+		reg = <0x880000 0x4000>,
+			<0x0ECB0000 0x10000>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S0_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep", "disable";
+		pinctrl-0 = <&qupv3_se15_i3c_active>;
+		pinctrl-1 = <&qupv3_se15_i3c_sleep>;
+		pinctrl-2 = <&qupv3_se15_i3c_disable>;
+		interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
+				<&pdc 35 IRQ_TYPE_LEVEL_HIGH>,
+				<&pdc 34 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,ibi-support-disabled;
+
+		#address-cells = <3>;
+		#size-cells = <0>;
+		qcom,ibi-ctrl-id = <2>; //QUP2-SE0 – IBI2 - 0xECB0000
+		qcom,wrapper-core = <&qupv3_2>;
+
+		status = "disable";
+	};
+
+	qupv3_se16_i2c: i2c@884000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x884000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S1_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se16_i2c_active>;
+		pinctrl-1 = <&qupv3_se16_i2c_sleep>;
+		dmas = <&gpi_dma2 0 1 3 64 0>,
+			<&gpi_dma2 1 1 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se16_spi: spi@884000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x884000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S1_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se16_spi_active>;
+		pinctrl-1 = <&qupv3_se16_spi_sleep>;
+		dmas = <&gpi_dma2 0 1 1 64 0>,
+			<&gpi_dma2 1 1 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se17_i2c: i2c@888000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x888000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S2_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se17_i2c_active>;
+		pinctrl-1 = <&qupv3_se17_i2c_sleep>;
+		dmas = <&gpi_dma2 0 2 3 64 0>,
+			<&gpi_dma2 1 2 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se17_spi: spi@888000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x888000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S2_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se17_spi_active>;
+		pinctrl-1 = <&qupv3_se17_spi_sleep>;
+		dmas = <&gpi_dma2 0 2 1 64 0>,
+			<&gpi_dma2 1 2 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se18_i2c: i2c@88c000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x88c000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se18_i2c_active>;
+		pinctrl-1 = <&qupv3_se18_i2c_sleep>;
+		dmas = <&gpi_dma2 0 3 3 64 0>,
+			<&gpi_dma2 1 3 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se18_spi: spi@88c000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x88c000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se18_spi_active>;
+		pinctrl-1 = <&qupv3_se18_spi_sleep>;
+		dmas = <&gpi_dma2 0 3 1 64 0>,
+			<&gpi_dma2 1 3 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se19_i2c: i2c@890000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x890000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se19_i2c_active>;
+		pinctrl-1 = <&qupv3_se19_i2c_sleep>;
+		dmas = <&gpi_dma2 0 4 3 64 0>,
+			<&gpi_dma2 1 4 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se19_spi: spi@890000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x890000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se19_spi_active>;
+		pinctrl-1 = <&qupv3_se19_spi_sleep>;
+		dmas = <&gpi_dma2 0 4 1 64 0>,
+			<&gpi_dma2 1 4 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se20_i2c: i2c@894000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x894000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S5_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se20_i2c_active>;
+		pinctrl-1 = <&qupv3_se20_i2c_sleep>;
+		dmas = <&gpi_dma2 0 5 3 64 0>,
+			<&gpi_dma2 1 5 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se20_spi: spi@894000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x894000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S5_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se20_spi_active>;
+		pinctrl-1 = <&qupv3_se20_spi_sleep>;
+		dmas = <&gpi_dma2 0 5 1 64 0>,
+			<&gpi_dma2 1 5 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se21_i2c: i2c@898000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x898000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S6_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se21_i2c_active>;
+		pinctrl-1 = <&qupv3_se21_i2c_sleep>;
+		dmas = <&gpi_dma2 0 6 3 64 0>,
+			<&gpi_dma2 1 6 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se21_spi: spi@898000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x898000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S6_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se21_spi_active>;
+		pinctrl-1 = <&qupv3_se21_spi_sleep>;
+		dmas = <&gpi_dma2 0 6 1 64 0>,
+			<&gpi_dma2 1 6 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	/* HS UART Instance */
+	qupv3_se20_4uart: qcom,qup_uart@894000 {
+		compatible = "qcom,msm-geni-serial-hs";
+		reg = <0x894000 0x4000>;
+		reg-names = "se_phys";
+		interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>,
+				<&tlmm 79 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S5_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "active", "sleep";
+		pinctrl-0 = <&qupv3_se20_default_cts>,
+			<&qupv3_se20_default_rtsrx>, <&qupv3_se20_default_tx>;
+		pinctrl-1 = <&qupv3_se20_cts>, <&qupv3_se20_rts>,
+			<&qupv3_se20_tx>, <&qupv3_se20_rx_active>;
+		pinctrl-2 = <&qupv3_se20_cts>, <&qupv3_se20_rts>,
+			<&qupv3_se20_tx>, <&qupv3_se20_rx_wake>;
+		qcom,wakeup-byte = <0xFD>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+};
diff --git a/qcom/waipio-regulators.dtsi b/qcom/waipio-regulators.dtsi
new file mode 100644
index 00000000..01033f32
--- /dev/null
+++ b/qcom/waipio-regulators.dtsi
@@ -0,0 +1,1058 @@
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+
+&apps_rsc {
+	rpmh-regulator-gfxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "gfx.lvl";
+		VDD_GFX_LEVEL: S5B_LEVEL:
+		pm8350_s5_level: regulator-pm8350-s5-level {
+			regulator-name = "pm8350_s5_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+	};
+
+	rpmh-regulator-lcxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "lcx.lvl";
+		VDD_LPI_CX_LEVEL: L8B_LEVEL:
+		pm8350_l8_level: regulator-pm8350-l8-level {
+			regulator-name = "pm8350_l8_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+	};
+
+	rpmh-regulator-msslvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "mss.lvl";
+		VDD_MODEM_LEVEL: S4C_LEVEL:
+		pm8350c_s4_level: regulator-pm8350c-s4-level {
+			regulator-name = "pm8350c_s4_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+	};
+
+	rpmh-regulator-cxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "cx.lvl";
+		proxy-supply = <&VDD_CX_LEVEL>;
+
+		VDD_CX_LEVEL: S6C_LEVEL:
+		pm8350c_s6_level: regulator-pm8350c-s6-level {
+			regulator-name = "pm8350c_s6_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_TURBO>;
+			qcom,proxy-consumer-enable;
+			qcom,proxy-consumer-voltage =
+				<RPMH_REGULATOR_LEVEL_TURBO
+				 RPMH_REGULATOR_LEVEL_MAX>;
+		};
+
+		VDD_CX_LEVEL_AO: S6C_LEVEL_AO:
+		pm8350c_s6_level_ao: regulator-pm8350c-s6-level-ao {
+			regulator-name = "pm8350c_s6_level_ao";
+			qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+
+		VDD_CX_MMCX_SUPPLY_LEVEL: regulator-pm8350c-s6-mmcx-sup-level {
+			regulator-name = "pm8350c_s6_mmcx_sup_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_MIN_SVS>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_MIN_SVS>;
+		};
+	};
+
+	rpmh-regulator-ebilvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "ebi.lvl";
+		VDD_EBI_LEVEL: S2H_LEVEL:
+		pm8450_s2_level: regulator-pm8450-s2-level {
+			regulator-name = "pm8450_s2_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+	};
+
+	rpmh-regulator-mmcxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "mmcx.lvl";
+		proxy-supply = <&VDD_MMCX_LEVEL>;
+
+		VDD_MMCX_LEVEL: VDD_MM_LEVEL: S4H_LEVEL:
+		pm8450_s4_level: regulator-pm8450-s4-level {
+			regulator-name = "pm8450_s4_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			pm8450_s4_level-parent-supply =
+				<&VDD_CX_MMCX_SUPPLY_LEVEL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_LOW_SVS>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_TURBO>;
+			qcom,proxy-consumer-enable;
+			qcom,proxy-consumer-voltage =
+				<RPMH_REGULATOR_LEVEL_TURBO
+				 RPMH_REGULATOR_LEVEL_MAX>;
+		};
+
+		VDD_MMCX_LEVEL_AO: VDD_MM_LEVEL_AO: S4H_LEVEL_AO:
+		pm8450_s4_level_ao: regulator-pm8450-s4-level-ao {
+			regulator-name = "pm8450_s4_level_ao";
+			qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_LOW_SVS>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_LOW_SVS>;
+		};
+
+		regulator-pm8450-s4-level-so {
+			regulator-name = "pm8450_s4_level_so";
+			qcom,set = <RPMH_REGULATOR_SET_SLEEP>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_LOW_SVS>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_LOW_SVS>;
+		};
+	};
+
+	rpmh-regulator-mxclvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "mxc.lvl";
+		proxy-supply = <&VDD_MXC_LEVEL>;
+
+		VDD_MXC_LEVEL: S2C_LEVEL:
+		pm8350c_s2_level: regulator-pm8350c-s2-level {
+			regulator-name = "pm8350c_s2_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_TURBO>;
+			qcom,proxy-consumer-enable;
+			qcom,proxy-consumer-voltage =
+				<RPMH_REGULATOR_LEVEL_TURBO
+				 RPMH_REGULATOR_LEVEL_MAX>;
+		};
+
+		VDD_MXC_LEVEL_AO: S2C_LEVEL_AO:
+		pm8350c_s2_level_ao: regulator-pm8350c-s2-level-ao {
+			regulator-name = "pm8350c_s2_level_ao";
+			qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+
+		VDD_MXC_MMCX_VOTER_LEVEL: VDD_MXC_MM_VOTER_LEVEL:
+		VDD_MM_MXC_VOTER_LEVEL:
+		regulator-pm8350c-s2-mmcx-voter-level {
+			regulator-name = "pm8350c_s2_mmcx_voter_level";
+			vin-supply = <&VDD_MMCX_LEVEL>;
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_MIN_SVS>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_MIN_SVS>;
+		};
+
+		VDD_MXC_GFX_VOTER_LEVEL: VDD_GFX_MXC_VOTER_LEVEL:
+		regulator-pm8350c-s2-gfx-voter-level {
+			regulator-name = "pm8350c_s2_gfx_voter_level";
+			pm8350c_s2_gfx_voter_level-parent-supply =
+				<&VDD_GFX_LEVEL>;
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_MIN_SVS>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_MIN_SVS>;
+		};
+	};
+
+	rpmh-regulator-mxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "mx.lvl";
+		proxy-supply = <&VDD_MXA_LEVEL>;
+
+		VDD_MXA_LEVEL: S6H_LEVEL:
+		pm8450_s6_level: regulator-pm8450-s6-level {
+			regulator-name = "pm8450_s6_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_TURBO>;
+			qcom,proxy-consumer-enable;
+			qcom,proxy-consumer-voltage =
+				<RPMH_REGULATOR_LEVEL_TURBO
+				 RPMH_REGULATOR_LEVEL_MAX>;
+		};
+
+		VDD_MXA_LEVEL_AO: S6H_LEVEL_AO:
+		pm8450_s6_level_ao: regulator-pm8450-s6-level-ao {
+			regulator-name = "pm8450_s6_level_ao";
+			qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+	};
+
+	rpmh-regulator-lmxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "lmx.lvl";
+		VDD_LPI_MX_LEVEL: L1H_LEVEL:
+		pm8450_l1_level: regulator-pm8450-l1-level {
+			regulator-name = "pm8450_l1_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+	};
+
+	rpmh-regulator-smpb10 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpb10";
+		S10B: pm8350_s10: regulator-pm8350-s10 {
+			regulator-name = "pm8350_s10";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+		};
+	};
+
+	rpmh-regulator-smpb11 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpb11";
+		S11B: pm8350_s11: regulator-pm8350-s11 {
+			regulator-name = "pm8350_s11";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <848000>;
+			regulator-max-microvolt = <1104000>;
+			qcom,init-voltage = <952000>;
+		};
+	};
+
+	rpmh-regulator-smpb12 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpb12";
+		S12B: pm8350_s12: regulator-pm8350-s12 {
+			regulator-name = "pm8350_s12";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1224000>;
+			regulator-max-microvolt = <1400000>;
+			qcom,init-voltage = <1256000>;
+		};
+	};
+
+	rpmh-regulator-ldob1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob1";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L1B: pm8350_l1: regulator-pm8350-l1 {
+			regulator-name = "pm8350_l1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <920000>;
+			qcom,init-voltage = <912000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob2 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob2";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L2B: pm8350_l2: regulator-pm8350-l2 {
+			regulator-name = "pm8350_l2";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			qcom,init-voltage = <3072000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob3";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L3B: pm8350_l3: regulator-pm8350-l3 {
+			regulator-name = "pm8350_l3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <904000>;
+			regulator-max-microvolt = <904000>;
+			qcom,init-voltage = <904000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob5 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob5";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L5B: pm8350_l5: regulator-pm8350-l5 {
+			regulator-name = "pm8350_l5";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			qcom,init-voltage = <880000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		L5B_AO: pm8350_l5_ao: regulator-pm8350-l5-ao {
+			regulator-name = "pm8350_l5_ao";
+			qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			qcom,init-voltage = <880000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		regulator-pm8350-l5-so {
+			regulator-name = "pm8350_l5_so";
+			qcom,set = <RPMH_REGULATOR_SET_SLEEP>;
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			qcom,init-voltage = <880000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+			qcom,init-enable = <0>;
+		};
+	};
+
+	rpmh-regulator-ldob6 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob6";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L6B: pm8350_l6: regulator-pm8350-l6 {
+			regulator-name = "pm8350_l6";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1200000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		L6B_AO: pm8350_l6_ao: regulator-pm8350-l6-ao {
+			regulator-name = "pm8350_l6_ao";
+			qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1200000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+
+		regulator-pm8350-l6-so {
+			regulator-name = "pm8350_l6_so";
+			qcom,set = <RPMH_REGULATOR_SET_SLEEP>;
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1200000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+			qcom,init-enable = <0>;
+		};
+	};
+
+	rpmh-regulator-ldob7 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob7";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L7B: pm8350_l7: regulator-pm8350-l7 {
+			regulator-name = "pm8350_l7";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2504000>;
+			qcom,init-voltage = <2504000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob9 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob9";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L9B: pm8350_l9: regulator-pm8350-l9 {
+			regulator-name = "pm8350_l9";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1200000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-smpc1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpc1";
+		S1C: pm8350c_s1: regulator-pm8350c-s1 {
+			regulator-name = "pm8350c_s1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2024000>;
+			qcom,init-voltage = <1856000>;
+		};
+	};
+
+	rpmh-regulator-smpc10 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpc10";
+		S10C: pm8350c_s10: regulator-pm8350c-s10 {
+			regulator-name = "pm8350c_s10";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1100000>;
+			qcom,init-voltage = <1052000>;
+		};
+	};
+
+	rpmh-regulator-ldoc1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoc1";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L1C: pm8350c_l1: regulator-pm8350c-l1 {
+			regulator-name = "pm8350c_l1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc2 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoc2";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L2C: pm8350c_l2: regulator-pm8350c-l2 {
+			regulator-name = "pm8350c_l2";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoc3";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L3C: pm8350c_l3: regulator-pm8350c-l3 {
+			regulator-name = "pm8350c_l3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <3296000>;
+			regulator-max-microvolt = <3304000>;
+			qcom,init-voltage = <3296000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc4 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoc4";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L4C: pm8350c_l4: regulator-pm8350c-l4 {
+			regulator-name = "pm8350c_l4";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1704000>;
+			regulator-max-microvolt = <3000000>;
+			qcom,init-voltage = <1808000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc5 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoc5";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L5C: pm8350c_l5: regulator-pm8350c-l5 {
+			regulator-name = "pm8350c_l5";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1704000>;
+			regulator-max-microvolt = <3000000>;
+			qcom,init-voltage = <1808000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc6 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoc6";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L6C: pm8350c_l6: regulator-pm8350c-l6 {
+			regulator-name = "pm8350c_l6";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			qcom,init-voltage = <2960000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc7 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoc7";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L7C: pm8350c_l7: regulator-pm8350c-l7 {
+			regulator-name = "pm8350c_l7";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3008000>;
+			qcom,init-voltage = <3008000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc8 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoc8";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L8C: pm8350c_l8: regulator-pm8350c-l8 {
+			regulator-name = "pm8350c_l8";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc9 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoc9";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L9C: pm8350c_l9: regulator-pm8350c-l9 {
+			regulator-name = "pm8350c_l9";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <3008000>;
+			qcom,init-voltage = <2960000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc10 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoc10";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L10C: pm8350c_l10: regulator-pm8350c-l10 {
+			regulator-name = "pm8350c_l10";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1200000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc12 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoc12";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L12C: pm8350c_l12: regulator-pm8350c-l12 {
+			regulator-name = "pm8350c_l12";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1968000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoc13 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoc13";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L13C: pm8350c_l13: regulator-pm8350c-l13 {
+			regulator-name = "pm8350c_l13";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			qcom,init-voltage = <3000000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-bobc1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "bobc1";
+		qcom,regulator-type = "pmic5-bob";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_PASS
+			 RPMH_REGULATOR_MODE_AUTO>;
+		qcom,mode-threshold-currents = <0 1000000>;
+		qcom,send-defaults;
+
+		BOB: pm8350c_bob: regulator-pm8350c-bob {
+			regulator-name = "pm8350c_bob";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3960000>;
+			qcom,init-voltage = <3296000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_PASS>;
+		};
+
+		BOB_AO: pm8350c_bob_ao: regulator-pm8350c-bob-ao {
+			regulator-name = "pm8350c_bob_ao";
+			qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3960000>;
+			qcom,init-voltage = <3008000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_AUTO>;
+		};
+	};
+
+	rpmh-regulator-ldod1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldod1";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L1D: pm8350b_l1: regulator-pm8350b-l1 {
+			regulator-name = "pm8350b_l1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1296000>;
+			qcom,init-voltage = <1200000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-smpe1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpe1";
+		S1E: pmr735a_s1: regulator-pmr735a-s1 {
+			regulator-name = "pmr735a_s1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1296000>;
+			qcom,init-voltage = <1256000>;
+		};
+	};
+
+	rpmh-regulator-smpe2 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpe2";
+		S2E: pmr735a_s2: regulator-pmr735a-s2 {
+			regulator-name = "pmr735a_s2";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <500000>;
+			regulator-max-microvolt = <1040000>;
+			qcom,init-voltage = <852000>;
+		};
+	};
+
+	rpmh-regulator-smpe3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpe3";
+		S3E: pmr735a_s3: regulator-pmr735a-s3 {
+			regulator-name = "pmr735a_s3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2200000>;
+			regulator-max-microvolt = <2352000>;
+			qcom,init-voltage = <2200000>;
+		};
+	};
+
+	rpmh-regulator-ldoe1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoe1";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L1E: pmr735a_l1: regulator-pmr735a-l1 {
+			regulator-name = "pmr735a_l1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <800000>;
+			regulator-max-microvolt = <800000>;
+			qcom,init-voltage = <800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoe2 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoe2";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L2E: pmr735a_l2: regulator-pmr735a-l2 {
+			regulator-name = "pmr735a_l2";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <480000>;
+			regulator-max-microvolt = <912000>;
+			qcom,init-voltage = <800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoe3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoe3";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L3E: pmr735a_l3: regulator-pmr735a-l3 {
+			regulator-name = "pmr735a_l3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1200000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoe4 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoe4";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L4E: pmr735a_l4: regulator-pmr735a-l4 {
+			regulator-name = "pmr735a_l4";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1776000>;
+			regulator-max-microvolt = <1776000>;
+			qcom,init-voltage = <1776000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoe5 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoe5";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L5E: pmr735a_l5: regulator-pmr735a-l5 {
+			regulator-name = "pmr735a_l5";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			qcom,init-voltage = <880000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoe6 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoe6";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L6E: pmr735a_l6: regulator-pmr735a-l6 {
+			regulator-name = "pmr735a_l6";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1200000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoe7 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoe7";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L7E: pmr735a_l7: regulator-pmr735a-l7 {
+			regulator-name = "pmr735a_l7";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			qcom,init-voltage = <2800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldof1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldof1";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L1F: pmr735b_l1: regulator-pmr735b-l1 {
+			regulator-name = "pmr735b_l1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			qcom,init-voltage = <912000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldof2 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldof2";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L2F: pmr735b_l2: regulator-pmr735b-l2 {
+			regulator-name = "pmr735b_l2";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1200000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldof4 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldof4";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L4F: pmr735b_l4: regulator-pmr735b-l4 {
+			regulator-name = "pmr735b_l4";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldof5 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldof5";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L5F: pmr735b_l5: regulator-pmr735b-l5 {
+			regulator-name = "pmr735b_l5";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <800000>;
+			regulator-max-microvolt = <800000>;
+			qcom,init-voltage = <800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldof6 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldof6";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L6F: pmr735b_l6: regulator-pmr735b-l6 {
+			regulator-name = "pmr735b_l6";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <480000>;
+			regulator-max-microvolt = <904000>;
+			qcom,init-voltage = <768000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-smph3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smph3";
+		S3H: pm8450_s3: regulator-pm8450-s3 {
+			regulator-name = "pm8450_s3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <500000>;
+			regulator-max-microvolt = <600000>;
+			qcom,init-voltage = <504000>;
+		};
+	};
+
+	rpmh-regulator-ldoh2 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoh2";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L2H: pm8450_l2: regulator-pm8450-l2 {
+			regulator-name = "pm8450_l2";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			qcom,init-voltage = <880000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldoh3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoh3";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L3H: pm8450_l3: regulator-pm8450-l3 {
+			regulator-name = "pm8450_l3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			qcom,init-voltage = <912000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
diff --git a/qcom/waipio-rumi-overlay.dts b/qcom/waipio-rumi-overlay.dts
new file mode 100644
index 00000000..eedbfd56
--- /dev/null
+++ b/qcom/waipio-rumi-overlay.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "waipio-rumi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio RUMI";
+	compatible = "qcom,waipio-rumi", "qcom,waipio", "qcom,rumi";
+	qcom,msm-id = <457 0x10000>;
+	qcom,board-id = <0x1000F 0>;
+};
diff --git a/qcom/waipio-rumi.dts b/qcom/waipio-rumi.dts
new file mode 100644
index 00000000..e463c949
--- /dev/null
+++ b/qcom/waipio-rumi.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/memreserve/ 0x90000000 0x00010000;
+
+#include "waipio.dtsi"
+#include "waipio-rumi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio RUMI";
+	compatible = "qcom,waipio-rumi", "qcom,waipio", "qcom,rumi";
+	qcom,board-id = <15 0>;
+};
diff --git a/qcom/waipio-rumi.dtsi b/qcom/waipio-rumi.dtsi
new file mode 100644
index 00000000..94d1d6d6
--- /dev/null
+++ b/qcom/waipio-rumi.dtsi
@@ -0,0 +1,135 @@
+#include <dt-bindings/gpio/gpio.h>
+
+#include "waipio-pmic-overlay.dtsi"
+
+&arch_timer {
+	clock-frequency = <500000>;
+};
+
+&memtimer {
+	clock-frequency = <500000>;
+};
+
+&soc {
+	pcie0: qcom,pcie@1c00000 {
+		reg = <0x01c00000 0x3000>,
+			<0x01c06000 0x2000>,
+			<0x60000000 0xf1d>,
+			<0x60000f20 0xa8>,
+			<0x60001000 0x1000>,
+			<0x60100000 0x100000>,
+			<0x01c05000 0x1000>;
+			reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
+				"rumi";
+			qcom,target-link-speed = <0x1>;
+			qcom,link-check-max-count = <200>; /* 1 sec */
+			qcom,no-l1-supported;
+			qcom,no-l1ss-supported;
+			qcom,no-aux-clk-sync;
+
+			status = "ok";
+	};
+
+	usb_nop_phy: usb_nop_phy {
+		compatible = "usb-nop-xceiv";
+	};
+
+	usb_emuphy: phy@a784000 {
+		compatible = "qcom,usb-emu-phy";
+		reg = <0x0a784000 0x9500>;
+
+		qcom,emu-init-seq = <0xfffff 0x4
+		     0xffff0 0x4
+		     0x100000 0x20
+		     0x0 0x20
+		     0x000101F0 0x20
+		     0x00100000 0x3c
+		     0x0 0x3c
+		     0x0 0x4>;
+	};
+};
+
+&usb0 {
+	dwc3@a600000 {
+		usb-phy = <&usb_emuphy>, <&usb_nop_phy>;
+		dr_mode = "peripheral";
+		maximum-speed = "high-speed";
+	};
+};
+
+&usb2_phy0 {
+	status = "disabled";
+};
+
+&usb_qmp_dp_phy {
+	status = "disabled";
+};
+
+&sdhc_2 {
+	status = "ok";
+	vdd-supply = <&pm8350c_l9>;
+	qcom,vdd-voltage-level = <2950000 2960000>;
+	qcom,vdd-current-level = <200 800000>;
+
+	vdd-io-supply = <&pm8350c_l6>;
+	qcom,vdd-io-voltage-level = <2960000 2960000>;
+	qcom,vdd-io-current-level = <200 22000>;
+
+	cap-sd-highspeed;
+	max-frequency = <100000000>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_on>;
+	pinctrl-1 = <&sdc2_off>;
+
+	cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
+};
+
+&ufsphy_mem {
+	compatible = "qcom,ufs-phy-qrbtc-sdm845";
+
+	vdda-phy-supply = <&pm8350_l5>;
+	vdda-pll-supply = <&pm8350_l6>;
+	vdda-phy-max-microamp = <102000>;
+	vdda-pll-max-microamp = <19200>;
+
+	status = "ok";
+};
+
+&ufshc_mem {
+	limit-tx-hs-gear = <1>;
+	limit-rx-hs-gear = <1>;
+	limit-rate = <2>; /* HS Rate-B */
+
+	vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+	vdd-hba-fixed-regulator;
+
+	vcc-supply = <&pm8350_l7>;
+	vcc-max-microamp = <1100000>;
+
+	vccq-supply = <&pm8350_l9>;
+	vccq-max-microamp = <1200000>;
+
+	qcom,vddp-ref-clk-supply = <&pm8350_l9>;
+	qcom,vddp-ref-clk-max-microamp = <100>;
+
+	qcom,disable-lpm;
+	rpm-level = <0>;
+	spm-level = <0>;
+
+	qcom,iommu-dma = "bypass";
+
+	status = "ok";
+};
+
+&qupv3_se5_i2c {
+	status = "disabled";
+};
+
+&tsens0 {
+	status = "disabled";
+};
+
+&tsens1 {
+	status = "disabled";
+};
diff --git a/qcom/waipio-smp2p.dtsi b/qcom/waipio-smp2p.dtsi
new file mode 100644
index 00000000..93786b65
--- /dev/null
+++ b/qcom/waipio-smp2p.dtsi
@@ -0,0 +1,140 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,ipcc.h>
+
+&soc {
+	qcom,smp2p-adsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
+			      IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
+			  IPCC_MPROC_SIGNAL_SMP2P>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		adsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		adsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
+			qcom,entry-name = "rdbg";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
+			qcom,entry-name = "rdbg";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+	};
+
+	qcom,smp2p-dsps {
+		compatible = "qcom,smp2p";
+		qcom,smem = <481>, <430>;
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P
+			      IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <3>;
+
+		dsps_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		dsps_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		sleepstate_smp2p_out: sleepstate-out {
+			qcom,entry-name = "sleepstate";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		sleepstate_smp2p_in: qcom,sleepstate-in {
+			qcom,entry-name = "sleepstate_see";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	qcom,smp2p-cdsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <94>, <432>;
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
+			      IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <5>;
+
+		cdsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		cdsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
+			qcom,entry-name = "rdbg";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
+			qcom,entry-name = "rdbg";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+	};
+
+	qcom,smp2p-modem {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
+			      IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		modem_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		modem_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
+			qcom,entry-name = "ipa";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		/* ipa - inbound entry from mss */
+		smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
+			qcom,entry-name = "ipa";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
diff --git a/qcom/waipio-thermal-modem.dtsi b/qcom/waipio-thermal-modem.dtsi
new file mode 100644
index 00000000..c1d7da1d
--- /dev/null
+++ b/qcom/waipio-thermal-modem.dtsi
@@ -0,0 +1,632 @@
+#include <dt-bindings/thermal/thermal_qti.h>
+
+&soc {
+	qmi-tmd-devices {
+		compatible = "qcom,qmi-cooling-devices";
+
+		modem {
+			qcom,instance-id = <QMI_MODEM_INST_ID>;
+
+			modem_lte_dsc: mmodem_lte_dsc {
+				qcom,qmi-dev-name = "modem_lte_dsc";
+				#cooling-cells = <2>;
+			};
+
+			modem_nr_dsc: modem_nr_dsc {
+				qcom,qmi-dev-name = "modem_nr_dsc";
+				#cooling-cells = <2>;
+			};
+
+			modem_nr_scg_dsc: modem_nr_scg_dsc {
+				qcom,qmi-dev-name = "modem_nr_scg_dsc";
+				#cooling-cells = <2>;
+			};
+
+			sdr0_lte_dsc: sdr0_lte_dsc {
+				qcom,qmi-dev-name = "sdr0_lte_dsc";
+				#cooling-cells = <2>;
+			};
+
+			sdr1_lte_dsc: sdr1_lte_dsc {
+				qcom,qmi-dev-name = "sdr1_lte_dsc";
+				#cooling-cells = <2>;
+			};
+
+			sdr0_nr_dsc: sdr0_nr_dsc {
+				qcom,qmi-dev-name = "sdr0_nr_dsc";
+				#cooling-cells = <2>;
+			};
+
+			sdr1_nr_dsc: sdr1_nr_dsc {
+				qcom,qmi-dev-name = "sdr1_nr_dsc";
+				#cooling-cells = <2>;
+			};
+
+			pa_sdr0_dsc: pa_sdr0_dsc {
+				qcom,qmi-dev-name = "pa_sdr0_dsc";
+				#cooling-cells = <2>;
+			};
+
+			pa_sdr1_dsc: pa_sdr1_dsc {
+				qcom,qmi-dev-name = "pa_sdr1_dsc";
+				#cooling-cells = <2>;
+			};
+
+			pa_fr1_sdr0_dsc: pa_fr1_sdr0_dsc {
+				qcom,qmi-dev-name = "pa_fr1_sdr0_dsc";
+				#cooling-cells = <2>;
+			};
+
+			pa_fr1_sdr1_dsc: pa_fr1_sdr1_dsc {
+				qcom,qmi-dev-name = "pa_fr1_sdr1_dsc";
+				#cooling-cells = <2>;
+			};
+
+			pa_fr1_sdr0_scg_dsc: pa_fr1_sdr0_scg_dsc {
+				qcom,qmi-dev-name = "pa_fr1_sdr0_scg_dsc";
+				#cooling-cells = <2>;
+			};
+
+			pa_fr1_sdr1_scg_dsc: pa_fr1_sdr1_scg_dsc {
+				qcom,qmi-dev-name = "pa_fr1_sdr1_scg_dsc";
+				#cooling-cells = <2>;
+			};
+
+			mmw0_dsc: mmw0_dsc {
+				qcom,qmi-dev-name = "mmw0_dsc";
+				#cooling-cells = <2>;
+			};
+
+			mmw1_dsc: mmw1_dsc {
+				qcom,qmi-dev-name = "mmw1_dsc";
+				#cooling-cells = <2>;
+			};
+
+			mmw2_dsc: mmw2_dsc {
+				qcom,qmi-dev-name = "mmw2_dsc";
+				#cooling-cells = <2>;
+			};
+
+			mmw3_dsc: mmw3_dsc {
+				qcom,qmi-dev-name = "mmw3_dsc";
+				#cooling-cells = <2>;
+			};
+
+			mmw_ul_throttle_dsc: mmw_ul_throttling_dsc {
+				qcom,qmi-dev-name = "mmw_ul_throttling_dsc";
+				#cooling-cells = <2>;
+			};
+
+			mmw_ific_dsc: mmw_ific_dsc {
+				qcom,qmi-dev-name = "mmw_ific_dsc";
+				#cooling-cells = <2>;
+			};
+
+			qmi_wlan: wlan {
+				qcom,qmi-dev-name = "wlan";
+				#cooling-cells = <2>;
+			};
+
+			wlan_bw: wlan_bw {
+				qcom,qmi-dev-name = "wlan_bw";
+				#cooling-cells = <2>;
+			};
+
+			modem_vdd: modem_vdd {
+				qcom,qmi-dev-name = "cpuv_restriction_cold";
+				#cooling-cells = <2>;
+			};
+		};
+	};
+
+	qmi_sensor: qmi-ts-sensors {
+		compatible = "qcom,qmi-sensors";
+		#thermal-sensor-cells = <1>;
+
+		modem {
+			qcom,instance-id = <QMI_MODEM_INST_ID>;
+			qcom,qmi-sensor-names = "pa",
+						"pa_1",
+						"qtm_therm",
+						"sys_therm1",
+						"sys_therm2",
+						"modem_bcl_warn",
+						"modem_tsens",
+						"modem_tsens1",
+						"sdr0_pa0",
+						"sdr0_pa1",
+						"sdr0_pa2",
+						"sdr0_pa3",
+						"sdr0_pa4",
+						"sdr0",
+						"sdr1_pa0",
+						"sdr1_pa1",
+						"sdr1_pa2",
+						"sdr1_pa3",
+						"sdr1_pa4",
+						"sdr1_pa5",
+						"sdr1",
+						"mmw0",
+						"mmw1",
+						"mmw2",
+						"mmw3",
+						"mmw_ific0";
+		};
+	};
+};
+
+&thermal_zones {
+	pa {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_PA)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	pa1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_PA_1)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	qtm-therm {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_QTM_THERM)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sys-therm1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SYS_THERM_1)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sys-therm2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SYS_THERM_2)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	bcl-warn {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_BCL_WARN)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr0-pa0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR0_PA0)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr0-pa1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR0_PA1)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr0-pa2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR0_PA2)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr0-pa3 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR0_PA3)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr0-pa4 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR0_PA4)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR0)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr1-pa0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR1_PA0)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr1-pa1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR1_PA1)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr1-pa2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR1_PA2)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr1-pa3 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR1_PA3)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr1-pa4 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR1_PA4)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr1-pa5 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR1_PA5)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR1)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	mmw0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_MMW0)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	mmw1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_MMW1)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	mmw2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_MMW2)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	mmw3 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_MMW3)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	mmw-ific0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_MMW_IFIC0)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+};
diff --git a/qcom/waipio-thermal-overlay.dtsi b/qcom/waipio-thermal-overlay.dtsi
new file mode 100644
index 00000000..0074b755
--- /dev/null
+++ b/qcom/waipio-thermal-overlay.dtsi
@@ -0,0 +1,262 @@
+#include <dt-bindings/thermal/thermal_qti.h>
+
+&thermal_zones {
+	socd {
+		cooling-maps {
+			socd_apc1 {
+				trip = <&socd_trip>;
+				cooling-device = <&APC1_pause 1 1>;
+			};
+
+			socd_cdsp1 {
+				trip = <&socd_trip>;
+				cooling-device = <&cdsp_sw 4 4>;
+			};
+
+			socd_gpu0 {
+				trip = <&socd_trip>;
+				cooling-device = <&msm_gpu 4 4>;
+			};
+		};
+	};
+
+	pm8350b-bcl-lvl0 {
+		cooling-maps {
+			vbat_cpu_5 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+
+			vbat_gpu0 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&msm_gpu 2 2>;
+			};
+
+			vbat_cdsp0 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&cdsp_sw 2 2>;
+			};
+
+			vbat_lte0 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&modem_lte_dsc 255 255>;
+			};
+
+			vbat_nr0 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&modem_nr_scg_dsc 255 255>;
+			};
+		};
+	};
+
+	pm8350b-bcl-lvl1 {
+		cooling-maps {
+			vbat_cpu_6_7 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&cpu_6_7_pause 1 1>;
+			};
+
+			vbat_gpu1 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&msm_gpu 4 4>;
+			};
+
+			vbat_cdsp1 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&cdsp_sw 4 4>;
+			};
+		};
+	};
+
+	pm8350b-bcl-lvl2 {
+		cooling-maps {
+			vbat_gpu2 {
+				trip = <&b_bcl_lvl2>;
+				cooling-device = <&msm_gpu 7 THERMAL_NO_LIMIT>;
+			};
+
+			vbat_cdsp2 {
+				trip = <&b_bcl_lvl2>;
+				cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	pm8350c-bcl-lvl0 {
+		cooling-maps {
+			vph_cpu_5 {
+				trip = <&c_bcl_lvl0>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+
+			vph_gpu0 {
+				trip = <&c_bcl_lvl0>;
+				cooling-device = <&msm_gpu 2 2>;
+			};
+
+			vph_cdsp0 {
+				trip = <&c_bcl_lvl0>;
+				cooling-device = <&cdsp_sw 2 2>;
+			};
+
+			vph_lte0 {
+				trip = <&c_bcl_lvl0>;
+				cooling-device = <&modem_lte_dsc 255 255>;
+			};
+
+			vph_nr0 {
+				trip = <&c_bcl_lvl0>;
+				cooling-device = <&modem_nr_scg_dsc 255 255>;
+			};
+		};
+	};
+
+	pm8350c-bcl-lvl1 {
+		cooling-maps {
+			vph_cpu_6_7 {
+				trip = <&c_bcl_lvl1>;
+				cooling-device = <&cpu_6_7_pause 1 1>;
+			};
+
+			vph_gpu1 {
+				trip = <&c_bcl_lvl1>;
+				cooling-device = <&msm_gpu 4 4>;
+			};
+
+			vph_cdsp1 {
+				trip = <&c_bcl_lvl1>;
+				cooling-device = <&cdsp_sw 4 4>;
+			};
+		};
+	};
+
+	pm8350c-bcl-lvl2 {
+		cooling-maps {
+			vph_gpu2 {
+				trip = <&c_bcl_lvl2>;
+				cooling-device = <&msm_gpu 7 THERMAL_NO_LIMIT>;
+			};
+
+			vph_cdsp2 {
+				trip = <&c_bcl_lvl2>;
+				cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	pm8450_tz {
+		cooling-maps {
+			pm8450_cpu4_freq {
+				trip = <&pm8450_trip0>;
+				cooling-device = <&CPU4 15 THERMAL_NO_LIMIT>;
+			};
+
+			pm8450_cpu7_freq {
+				trip = <&pm8450_trip0>;
+				cooling-device = <&CPU7 15 THERMAL_NO_LIMIT>;
+			};
+
+			pm8450_apc1 {
+				trip = <&pm8450_trip0>;
+				cooling-device = <&APC1_pause 1 1>;
+			};
+		};
+	};
+
+	pm8350_tz {
+		cooling-maps {
+			pm8350_gpu {
+				trip = <&pm8350_trip0>;
+				cooling-device = <&msm_gpu 7 THERMAL_NO_LIMIT>;
+			};
+
+			pm8350_cpu4_freq {
+				trip = <&pm8350_trip0>;
+				cooling-device = <&CPU4 15 THERMAL_NO_LIMIT>;
+			};
+
+			pm8350_cpu7_freq {
+				trip = <&pm8350_trip0>;
+				cooling-device = <&CPU7 15 THERMAL_NO_LIMIT>;
+			};
+
+			pm8350_apc1 {
+				trip = <&pm8350_trip0>;
+				cooling-device = <&APC1_pause 1 1>;
+			};
+		};
+	};
+
+	pm8350c_tz {
+		cooling-maps {
+			pm8350c_nsp {
+				trip = <&pm8350c_trip0>;
+				cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>;
+			};
+
+			pm8350c_lte {
+				trip = <&pm8350c_trip0>;
+				cooling-device = <&modem_lte_dsc 255 255>;
+			};
+
+			pm8350c_nr {
+				trip = <&pm8350c_trip0>;
+				cooling-device = <&modem_nr_scg_dsc 255 255>;
+			};
+		};
+	};
+
+	xo-therm {
+		cooling-maps {
+			cpu4_freq_cdev {
+				trip = <&xo_config0>;
+				cooling-device = <&CPU4 15 THERMAL_NO_LIMIT>;
+			};
+
+			cpu7_freq_cdev {
+				trip = <&xo_config0>;
+				cooling-device = <&CPU7 15 THERMAL_NO_LIMIT>;
+			};
+
+			apc1_cdev {
+				trip = <&xo_config0>;
+				cooling-device = <&APC1_pause 1 1>;
+			};
+
+			cdsp_cdev {
+				trip = <&xo_config0>;
+				cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>;
+			};
+
+			gpu_cdev {
+				trip = <&xo_config0>;
+				cooling-device = <&msm_gpu 7 THERMAL_NO_LIMIT>;
+			};
+
+			cpu5_hot_cdev {
+				trip = <&xo_config1>;
+				cooling-device = <&cpu5_hotplug 1 1>;
+			};
+
+			cpu6_hot_cdev {
+				trip = <&xo_config1>;
+				cooling-device = <&cpu6_hotplug 1 1>;
+			};
+
+			cpu7_hot_cdev {
+				trip = <&xo_config1>;
+				cooling-device = <&cpu7_hotplug 1 1>;
+			};
+
+			lte_cdev {
+				trip = <&xo_config1>;
+				cooling-device = <&modem_lte_dsc 255 255>;
+			};
+
+			nr_cdev {
+				trip = <&xo_config1>;
+				cooling-device = <&modem_nr_scg_dsc 255 255>;
+			};
+		};
+	};
+};
diff --git a/qcom/waipio-thermal.dtsi b/qcom/waipio-thermal.dtsi
new file mode 100644
index 00000000..1aac14c8
--- /dev/null
+++ b/qcom/waipio-thermal.dtsi
@@ -0,0 +1,1412 @@
+#include <dt-bindings/thermal/thermal_qti.h>
+
+&msm_gpu {
+	#cooling-cells = <2>;
+};
+
+&soc {
+	tsens0: thermal-sensor@c263000 {
+		compatible = "qcom,tsens-v2";
+		reg = <0x0c263000 0x1ff>, /* TM */
+			<0x0c222000 0x1ff>; /* SROT */
+		#qcom,sensors = <16>;
+		interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "uplow","critical";
+		#thermal-sensor-cells = <1>;
+	};
+
+	tsens1: thermal-sensor@c265000 {
+		compatible = "qcom,tsens-v2";
+		reg = <0x0c265000 0x1ff>, /* TM */
+			<0x0c223000 0x1ff>; /* SROT */
+		#qcom,sensors = <16>;
+		interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "uplow","critical";
+		#thermal-sensor-cells = <1>;
+	};
+
+	qcom,cpu-pause {
+		compatible = "qcom,thermal-pause";
+
+		cpu0_pause: cpu0-pause {
+			qcom,cpus = <&CPU0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu1_pause: cpu1-pause {
+			qcom,cpus = <&CPU1>;
+			#cooling-cells = <2>;
+		};
+
+		cpu2_pause: cpu2-pause {
+			qcom,cpus = <&CPU2>;
+			#cooling-cells = <2>;
+		};
+
+		cpu3_pause: cpu3-pause {
+			qcom,cpus = <&CPU3>;
+			#cooling-cells = <2>;
+		};
+
+		cpu5_pause: cpu5-pause {
+			qcom,cpus = <&CPU5>;
+			#cooling-cells = <2>;
+		};
+
+		cpu6_pause: cpu6-pause {
+			qcom,cpus = <&CPU6>;
+			#cooling-cells = <2>;
+		};
+
+		cpu7_pause: cpu7-pause {
+			qcom,cpus = <&CPU7>;
+			#cooling-cells = <2>;
+		};
+
+		APC1_pause: apc1-pause {
+			qcom,cpus = <&CPU5 &CPU6 &CPU7>;
+			#cooling-cells = <2>;
+		};
+
+		cpu_6_7_pause: cpu-6-7-pause {
+			qcom,cpus = <&CPU6 &CPU7>;
+			#cooling-cells = <2>;
+		};
+
+		/* Thermal-engine cooling devices */
+		pause-cpu0 {
+			qcom,cpus = <&CPU0>;
+			qcom,cdev-alias = "pause-cpu0";
+		};
+
+		pause-cpu1 {
+			qcom,cpus = <&CPU1>;
+			qcom,cdev-alias = "pause-cpu1";
+		};
+
+		pause-cpu2 {
+			qcom,cpus = <&CPU2>;
+			qcom,cdev-alias = "pause-cpu2";
+		};
+
+		pause-cpu3 {
+			qcom,cpus = <&CPU3>;
+			qcom,cdev-alias = "pause-cpu3";
+		};
+
+		pause-cpu5 {
+			qcom,cpus = <&CPU5>;
+			qcom,cdev-alias = "pause-cpu5";
+		};
+
+		pause-cpu6 {
+			qcom,cpus = <&CPU6>;
+			qcom,cdev-alias = "pause-cpu6";
+		};
+
+		pause-cpu7 {
+			qcom,cpus = <&CPU7>;
+			qcom,cdev-alias = "pause-cpu7";
+		};
+	};
+
+	qcom,cpu-hotplug {
+		compatible = "qcom,cpu-hotplug";
+
+		cpu0_hotplug: cpu0-hotplug {
+			qcom,cpu = <&CPU0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu1_hotplug: cpu1-hotplug {
+			qcom,cpu = <&CPU1>;
+			#cooling-cells = <2>;
+		};
+
+		cpu2_hotplug: cpu2-hotplug {
+			qcom,cpu = <&CPU2>;
+			#cooling-cells = <2>;
+		};
+
+		cpu3_hotplug: cpu3-hotplug {
+			qcom,cpu = <&CPU3>;
+			#cooling-cells = <2>;
+		};
+
+		cpu5_hotplug: cpu5-hotplug {
+			qcom,cpu = <&CPU5>;
+			#cooling-cells = <2>;
+		};
+
+		cpu6_hotplug: cpu6-hotplug {
+			qcom,cpu = <&CPU6>;
+			#cooling-cells = <2>;
+		};
+
+		cpu7_hotplug: cpu7-hotplug {
+			qcom,cpu = <&CPU7>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	qcom,cpu-voltage-cdev {
+		compatible = "qcom,cc-cooling-devices";
+		apc1_cluster: qcom,apc1-cluster {
+			qcom,cpus = <&CPU4 &CPU7>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	ddr_cdev: qcom,ddr-cdev {
+		compatible = "qcom,ddr-cooling-device";
+		#cooling-cells = <2>;
+		qcom,freq-table = <&ddr_freq_table>;
+		qcom,bus-width = <4>;
+		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
+	};
+
+	qcom,limits-dcvs {
+		compatible = "qcom,msm-hw-limits";
+		isens_vref_0p8-supply = <&pm8350_l5_ao>;
+		isens-vref-0p8-settings = <880000 880000 30000>;
+		isens_vref_1p8-supply = <&pm8350_l6_ao>;
+		isens-vref-1p8-settings = <1200000 1200000 8000>;
+	};
+
+	qmi_tmd: qmi-tmd-devices {
+		compatible = "qcom,qmi-cooling-devices";
+		cdsp {
+			qcom,instance-id = <QMI_CDSP_INST_ID>;
+
+			cdsp_sw: cdsp {
+				qcom,qmi-dev-name = "cdsp_sw";
+				#cooling-cells = <2>;
+			};
+
+			cdsp_hw: cdsp_hw {
+				qcom,qmi-dev-name = "cdsp_hw";
+				#cooling-cells = <2>;
+			};
+		};
+	};
+
+	qcom,cpufreq-cdev {
+		compatible = "qcom,cpufreq-cdev";
+		qcom,cpus = <&CPU0 &CPU4 &CPU7>;
+	};
+
+	qcom,devfreq-cdev {
+		compatible = "qcom,devfreq-cdev";
+		qcom,devfreq = <&msm_gpu>;
+	};
+};
+
+#include "waipio-thermal-modem.dtsi"
+
+&thermal_zones {
+	aoss-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 0>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpuss-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 1>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpuss-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 2>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpuss-2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 3>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpuss-3 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 4>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-1-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 5>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu4_emerg0: cpu4-emerg0-cfg {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-1-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 6>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu4_emerg1: cpu4-emerg1-cfg {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-1-2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 7>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu5_emerg0: cpu5-emerg0-cfg {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu12_cdev {
+				trip = <&cpu5_emerg0>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-1-3 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 8>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu5_emerg1: cpu5-emerg1-cfg {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu13_cdev {
+				trip = <&cpu5_emerg1>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-1-4 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 9>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu6_emerg0: cpu6-emerg0-cfg {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu14_cdev {
+				trip = <&cpu6_emerg0>;
+				cooling-device = <&cpu6_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-1-5 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 10>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu6_emerg1: cpu6-emerg1-cfg {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu15_cdev {
+				trip = <&cpu6_emerg1>;
+				cooling-device = <&cpu6_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-1-6 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 11>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu7_emerg0: cpu7-emerg0-cfg {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu16_cdev {
+				trip = <&cpu7_emerg0>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-1-7 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 12>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu7_emerg1: cpu7-emerg1-cfg {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu17_cdev {
+				trip = <&cpu7_emerg1>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-1-8 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 13>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu7_emerg2: cpu7-emerg2-cfg {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu18_cdev {
+				trip = <&cpu7_emerg2>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+		};
+	};
+
+	gpuss-0 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 14>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			gpu0_tj_cfg: tj_cfg {
+				temperature = <95000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			gpu0_cdev {
+				trip = <&gpu0_tj_cfg>;
+				cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	gpuss-1 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 15>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			gpu1_tj_cfg: tj_cfg {
+				temperature = <95000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			gpu1_cdev {
+				trip = <&gpu1_tj_cfg>;
+				cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	aoss-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 0>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-0-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 1>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu0_emerg: cpu0-emerg-cfg {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu00_cdev {
+				trip = <&cpu0_emerg>;
+				cooling-device = <&cpu0_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-0-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 2>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu1_emerg: cpu1-emerg-cfg {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu01_cdev {
+				trip = <&cpu1_emerg>;
+				cooling-device = <&cpu1_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-0-2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 3>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu2_emerg: cpu2-emerg-cfg {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu02_cdev {
+				trip = <&cpu2_emerg>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+		};
+	};
+
+	cpu-0-3 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 4>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu3_emerg: cpu3-emerg-cfg {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu03_cdev {
+				trip = <&cpu3_emerg>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+		};
+	};
+
+	nspss-0 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 5>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			nspss_0_config: junction-config {
+				temperature = <95000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			nsp_cdev {
+				trip = <&nspss_0_config>;
+				cooling-device = <&cdsp_sw THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	nspss-1 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 6>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			nspss_1_config: junction-config {
+				temperature = <95000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			nsp_cdev {
+				trip = <&nspss_1_config>;
+				cooling-device = <&cdsp_sw THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	nspss-2 {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 7>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			nspss_2_config: junction-config {
+				temperature = <95000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			nsp_cdev {
+				trip = <&nspss_2_config>;
+				cooling-device = <&cdsp_sw THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	video {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 8>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	ddr {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 9>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			ddr_config0: ddr0-config {
+				temperature = <90000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			gold_cdev {
+				trip = <&ddr_config0>;
+				cooling-device = <&CPU4
+					THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			};
+
+			gold_plus_cdev {
+				trip = <&ddr_config0>;
+				cooling-device = <&CPU7
+					THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			};
+
+			ddr_cdev {
+				trip = <&ddr_config0>;
+				cooling-device = <&ddr_cdev 8 8>;
+			};
+		};
+	};
+
+	mdmss-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 10>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			mdmss0_config0: mdmss0-config0 {
+				temperature = <95000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			mdmss0_config1: mdmss0-config1 {
+				temperature = <100000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			mdmss0_config2: mdmss0-config2 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			lte_cdev0 {
+				trip = <&mdmss0_config0>;
+				cooling-device = <&modem_lte_dsc 7 7>;
+			};
+
+			nr_scg_cdev0 {
+				trip = <&mdmss0_config0>;
+				cooling-device = <&modem_nr_scg_dsc 2 2>;
+			};
+
+			nr_cdev0 {
+				trip = <&mdmss0_config0>;
+				cooling-device = <&modem_nr_dsc 4 4>;
+			};
+
+			lte_cdev1 {
+				trip = <&mdmss0_config1>;
+				cooling-device = <&modem_lte_dsc 8 8>;
+			};
+
+			nr_scg_cdev1 {
+				trip = <&mdmss0_config1>;
+				cooling-device = <&modem_nr_scg_dsc 10 10>;
+			};
+
+			nr_cdev1 {
+				trip = <&mdmss0_config1>;
+				cooling-device = <&modem_nr_dsc 6 6>;
+			};
+
+			lte_cdev2 {
+				trip = <&mdmss0_config2>;
+				cooling-device = <&modem_lte_dsc 255 255>;
+			};
+
+			nr_cdev2 {
+				trip = <&mdmss0_config2>;
+				cooling-device = <&modem_nr_dsc 255 255>;
+			};
+		};
+	};
+
+	mdmss-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 11>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			mdmss1_config0: mdmss1-config0 {
+				temperature = <95000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			mdmss1_config1: mdmss1-config1 {
+				temperature = <100000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			mdmss1_config2: mdmss1-config2 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			lte_cdev0 {
+				trip = <&mdmss1_config0>;
+				cooling-device = <&modem_lte_dsc 7 7>;
+			};
+
+			nr_scg_cdev0 {
+				trip = <&mdmss1_config0>;
+				cooling-device = <&modem_nr_scg_dsc 2 2>;
+			};
+
+			nr_cdev0 {
+				trip = <&mdmss1_config0>;
+				cooling-device = <&modem_nr_dsc 4 4>;
+			};
+
+			lte_cdev1 {
+				trip = <&mdmss1_config1>;
+				cooling-device = <&modem_lte_dsc 8 8>;
+			};
+
+			nr_scg_cdev1 {
+				trip = <&mdmss1_config1>;
+				cooling-device = <&modem_nr_scg_dsc 10 10>;
+			};
+
+			nr_cdev1 {
+				trip = <&mdmss1_config1>;
+				cooling-device = <&modem_nr_dsc 6 6>;
+			};
+
+			lte_cdev2 {
+				trip = <&mdmss1_config2>;
+				cooling-device = <&modem_lte_dsc 255 255>;
+			};
+
+			nr_cdev2 {
+				trip = <&mdmss1_config2>;
+				cooling-device = <&modem_nr_dsc 255 255>;
+			};
+		};
+	};
+
+	mdmss-2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 12>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			mdmss2_config0: mdmss2-config0 {
+				temperature = <95000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			mdmss2_config1: mdmss2-config1 {
+				temperature = <100000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			mdmss2_config2: mdmss2-config2 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			lte_cdev0 {
+				trip = <&mdmss2_config0>;
+				cooling-device = <&modem_lte_dsc 7 7>;
+			};
+
+			nr_scg_cdev0 {
+				trip = <&mdmss2_config0>;
+				cooling-device = <&modem_nr_scg_dsc 2 2>;
+			};
+
+			nr_cdev0 {
+				trip = <&mdmss2_config0>;
+				cooling-device = <&modem_nr_dsc 4 4>;
+			};
+
+			lte_cdev1 {
+				trip = <&mdmss2_config1>;
+				cooling-device = <&modem_lte_dsc 8 8>;
+			};
+
+			nr_scg_cdev1 {
+				trip = <&mdmss2_config1>;
+				cooling-device = <&modem_nr_scg_dsc 10 10>;
+			};
+
+			nr_cdev1 {
+				trip = <&mdmss2_config1>;
+				cooling-device = <&modem_nr_dsc 6 6>;
+			};
+
+			lte_cdev2 {
+				trip = <&mdmss2_config2>;
+				cooling-device = <&modem_lte_dsc 255 255>;
+			};
+
+			nr_cdev2 {
+				trip = <&mdmss2_config2>;
+				cooling-device = <&modem_nr_dsc 255 255>;
+			};
+		};
+	};
+
+	mdmss-3 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 13>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			mdmss3_config0: mdmss3-config0 {
+				temperature = <95000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			mdmss3_config1: mdmss3-config1 {
+				temperature = <100000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			mdmss3_config2: mdmss3-config2 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			lte_cdev0 {
+				trip = <&mdmss3_config0>;
+				cooling-device = <&modem_lte_dsc 7 7>;
+			};
+
+			nr_scg_cdev0 {
+				trip = <&mdmss3_config0>;
+				cooling-device = <&modem_nr_scg_dsc 2 2>;
+			};
+
+			nr_cdev0 {
+				trip = <&mdmss3_config0>;
+				cooling-device = <&modem_nr_dsc 4 4>;
+			};
+
+			lte_cdev1 {
+				trip = <&mdmss3_config1>;
+				cooling-device = <&modem_lte_dsc 8 8>;
+			};
+
+			nr_scg_cdev1 {
+				trip = <&mdmss3_config1>;
+				cooling-device = <&modem_nr_scg_dsc 10 10>;
+			};
+
+			nr_cdev1 {
+				trip = <&mdmss3_config1>;
+				cooling-device = <&modem_nr_dsc 6 6>;
+			};
+
+			lte_cdev2 {
+				trip = <&mdmss3_config2>;
+				cooling-device = <&modem_lte_dsc 255 255>;
+			};
+
+			nr_cdev2 {
+				trip = <&mdmss3_config2>;
+				cooling-device = <&modem_nr_dsc 255 255>;
+			};
+		};
+	};
+
+	camera-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 14>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	camera-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 15>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <115000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+};
diff --git a/qcom/waipio-usb.dtsi b/qcom/waipio-usb.dtsi
new file mode 100644
index 00000000..7563bfa7
--- /dev/null
+++ b/qcom/waipio-usb.dtsi
@@ -0,0 +1,335 @@
+#include <dt-bindings/clock/qcom,gcc-waipio.h>
+#include <dt-bindings/phy/qcom,usb3-5nm-qmp-combo.h>
+
+&soc {
+	usb0: ssusb@a600000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0xa600000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
+		clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>,
+			<&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+			<&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+			<&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+			<&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>,
+			<&clock_gcc GCC_USB3_0_CLKREF_EN>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+					"utmi_clk", "sleep_clk", "xo";
+
+		resets = <&clock_gcc GCC_USB30_PRIM_BCR>;
+		reset-names = "core_reset";
+
+		interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>,
+			<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+			<&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+			<&pdc 15 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+				"ss_phy_irq", "dm_hs_phy_irq";
+		qcom,use-pdc-interrupts;
+
+		qcom,core-clk-rate = <200000000>;
+		qcom,core-clk-rate-hs = <66666667>;
+		qcom,num-gsi-evt-buffs = <0x3>;
+		qcom,gsi-reg-offset =
+			<0x0fc /* GSI_GENERAL_CFG */
+			0x110 /* GSI_DBL_ADDR_L */
+			0x120 /* GSI_DBL_ADDR_H */
+			0x130 /* GSI_RING_BASE_ADDR_L */
+			0x144 /* GSI_RING_BASE_ADDR_H */
+			0x1a4>; /* GSI_IF_STS */
+		qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
+
+		interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
+		interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
+				<&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>,
+				<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
+		extcon = <&eud>;
+
+		dwc3@a600000 {
+			compatible = "snps,dwc3";
+			reg = <0xa600000 0xd93c>;
+
+			iommus = <&apps_smmu 0x0 0x0>;
+			qcom,iommu-dma = "atomic";
+			qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
+			dma-coherent;
+
+			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+			usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>;
+			snps,disable-clk-gating;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,is-utmi-l1-suspend;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,ssp-u3-u0-quirk;
+			tx-fifo-resize;
+			dr_mode = "otg";
+			maximum-speed = "super-speed-plus";
+			usb-role-switch;
+		};
+
+		qcom,usbbam@a704000 {
+			compatible = "qcom,usb-bam-msm";
+			reg = <0xa704000 0x18000>;
+			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+
+			qcom,usb-bam-fifo-baseaddr = <0x146a6000>;
+			qcom,usb-bam-num-pipes = <4>;
+			qcom,disable-clk-gating;
+			qcom,usb-bam-override-threshold = <0x4001>;
+			qcom,usb-bam-max-mbps-highspeed = <400>;
+			qcom,usb-bam-max-mbps-superspeed = <3600>;
+			qcom,reset-bam-on-connect;
+
+			qcom,pipe0 {
+				label = "ssusb-qdss-in-0";
+				qcom,usb-bam-mem-type = <2>;
+				qcom,dir = <1>;
+				qcom,pipe-num = <0>;
+				qcom,peer-bam = <0>;
+				qcom,peer-bam-physical-address = <0x10064000>;
+				qcom,src-bam-pipe-index = <0>;
+				qcom,dst-bam-pipe-index = <0>;
+				qcom,data-fifo-offset = <0x0>;
+				qcom,data-fifo-size = <0x1800>;
+				qcom,descriptor-fifo-offset = <0x1800>;
+				qcom,descriptor-fifo-size = <0x800>;
+			};
+		};
+	};
+
+	/* USB port related High Speed PHY */
+	usb2_phy0: hsphy@88e3000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x88e3000 0x114>,
+			<0x088e2000 0x4>;
+		reg-names = "hsusb_phy_base",
+			"eud_enable_reg";
+
+		vdd-supply = <&pm8350_l5>;
+		vdda18-supply = <&pm8350c_l1>;
+		vdda33-supply = <&pm8350_l2>;
+		qcom,vdd-voltage-level = <0 880000 880000>;
+
+		clocks = <&clock_rpmh RPMH_CXO_CLK>;
+		clock-names = "ref_clk_src";
+
+		resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>;
+		reset-names = "phy_reset";
+	};
+
+	/* USB port related QMP USB DP Combo PHY */
+	usb_qmp_dp_phy: ssphy@88e8000 {
+		compatible = "qcom,usb-ssphy-qmp-dp-combo";
+		reg = <0x88e8000 0x3000>;
+		reg-names = "qmp_phy_base";
+
+		vdd-supply = <&pm8350_l1>;
+		qcom,vdd-voltage-level = <0 912000 912000>;
+		qcom,vdd-max-load-uA = <47000>;
+		core-supply = <&pm8350_l6>;
+
+		clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+			<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+			<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
+			<&clock_gcc USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK>,
+			<&clock_rpmh RPMH_CXO_CLK>,
+			<&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
+				"pipe_clk_ext_src", "ref_clk_src",
+				"com_aux_clk";
+
+		resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+			<&clock_gcc GCC_USB3_PHY_PRIM_BCR>;
+		reset-names = "global_phy_reset", "phy_reset";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb3phy_portselect_default>;
+
+		qcom,qmp-phy-reg-offset =
+			<USB3_DP_PCS_PCS_STATUS1
+			 USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
+			 USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
+			 USB3_DP_PCS_POWER_DOWN_CONTROL
+			 USB3_DP_PCS_SW_RESET
+			 USB3_DP_PCS_START_CONTROL
+			 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
+			 USB3_DP_COM_POWER_DOWN_CTRL
+			 USB3_DP_COM_SW_RESET
+			 USB3_DP_COM_RESET_OVRD_CTRL
+			 USB3_DP_COM_PHY_MODE_CTRL
+			 USB3_DP_COM_TYPEC_CTRL
+			 USB3_DP_PCS_CLAMP_ENABLE>;
+
+		qcom,qmp-phy-init-seq =
+			/* <reg_offset, value, delay> */
+			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0
+			USB3_DP_QSERDES_COM_SSC_PER1 0x31 0
+			USB3_DP_QSERDES_COM_SSC_PER2 0x01 0
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
+			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0
+			USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
+			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
+			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
+			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0
+			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
+			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
+			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
+			USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0
+			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00 0
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00 0
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0E 0
+			USB3_DP_QSERDES_TXA_LANE_MODE_1 0x35 0
+			USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F 0
+			USB3_DP_QSERDES_TXA_LANE_MODE_4 0x7F 0
+			USB3_DP_QSERDES_TXA_LANE_MODE_5 0x3F 0
+			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
+			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21 0
+			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x0A 0
+			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x03 0
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0
+			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
+			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08 0
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00 0
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04 0
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F 0
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0
+			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
+			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0
+			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0
+			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xBB 0
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7B 0
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xBB 0
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3D 0
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB 0
+			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x64 0
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x24 0
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xD2 0
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x13 0
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xA9 0
+			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0
+			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0
+			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0
+			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0
+			USB3_DP_QSERDES_RXA_GM_CAL 0x00 0
+			USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00 0
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0E 0
+			USB3_DP_QSERDES_TXB_LANE_MODE_1 0x35 0
+			USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F 0
+			USB3_DP_QSERDES_TXB_LANE_MODE_4 0x7F 0
+			USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F 0
+			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
+			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x21 0
+			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x0A 0
+			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x03 0
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0
+			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
+			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08 0
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00 0
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04 0
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F 0
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0
+			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
+			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0
+			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0
+			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBB 0
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x7B 0
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBB 0
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3C 0
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB 0
+			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x64 0
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x24 0
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xD2 0
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x13 0
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xA9 0
+			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0
+			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0
+			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0
+			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0
+			USB3_DP_QSERDES_RXB_GM_CAL 0x00 0
+			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40 0
+			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00 0
+			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0
+			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
+			USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0
+			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0 0
+			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0
+			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0
+			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0
+			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0
+			USB3_DP_PCS_RX_SIGDET_LVL 0xAA 0
+			USB3_DP_PCS_CDR_RESET_TIME 0x0A 0
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0
+			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0
+			USB3_DP_PCS_EQ_CONFIG1 0x4B 0
+			USB3_DP_PCS_EQ_CONFIG5 0x10 0
+			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
+			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
+			0xffffffff 0xffffffff 0x00>;
+	};
+
+	usb_audio_qmi_dev {
+		compatible = "qcom,usb-audio-qmi-dev";
+		iommus = <&apps_smmu 0x180f 0x0>;
+		qcom,iommu-dma = "disabled";
+		qcom,usb-audio-stream-id = <0xf>;
+		qcom,usb-audio-intr-num = <2>;
+	};
+};
diff --git a/qcom/waipio-v2-atp-pm8008.dts b/qcom/waipio-v2-atp-pm8008.dts
new file mode 100644
index 00000000..31a54a2b
--- /dev/null
+++ b/qcom/waipio-v2-atp-pm8008.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipio-v2.dtsi"
+#include "waipio-atp.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio v2 ATP with PM8008";
+	compatible = "qcom,waipio-atp", "qcom,waipio", "qcom,atp";
+	qcom,board-id = <33 0>;
+};
diff --git a/qcom/waipio-v2-atp-pm8010.dts b/qcom/waipio-v2-atp-pm8010.dts
new file mode 100644
index 00000000..0f3f4bd4
--- /dev/null
+++ b/qcom/waipio-v2-atp-pm8010.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipio-v2.dtsi"
+#include "waipio-atp.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio v2 ATP with PM8010";
+	compatible = "qcom,waipio-atp", "qcom,waipio", "qcom,atp";
+	qcom,board-id = <0x10021 0>;
+};
diff --git a/qcom/waipio-v2-cdp-pm8008.dts b/qcom/waipio-v2-cdp-pm8008.dts
new file mode 100644
index 00000000..51249eb7
--- /dev/null
+++ b/qcom/waipio-v2-cdp-pm8008.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipio-v2.dtsi"
+#include "waipio-cdp.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio v2 CDP with PM8008";
+	compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
+	qcom,board-id = <1 0>;
+};
diff --git a/qcom/waipio-v2-cdp-pm8010.dts b/qcom/waipio-v2-cdp-pm8010.dts
new file mode 100644
index 00000000..e3ccf590
--- /dev/null
+++ b/qcom/waipio-v2-cdp-pm8010.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipio-v2.dtsi"
+#include "waipio-cdp.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio v2 CDP with PM8010";
+	compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
+	qcom,board-id = <0x10001 0>;
+};
diff --git a/qcom/waipio-v2-gpu.dtsi b/qcom/waipio-v2-gpu.dtsi
new file mode 100644
index 00000000..608f0576
--- /dev/null
+++ b/qcom/waipio-v2-gpu.dtsi
@@ -0,0 +1,95 @@
+&msm_gpu {
+
+	compatible = "qcom,adreno-gpu-c500v2", "qcom,kgsl-3d0";
+
+	qcom,initial-pwrlevel = <7>;
+
+	qcom,gpu-model = "Adreno730v2";
+
+	qcom,gpu-pwrlevels {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		compatible = "qcom,gpu-pwrlevels";
+
+		qcom,gpu-pwrlevel@0 {
+			reg = <0>;
+			qcom,gpu-freq = <734000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+
+			qcom,bus-freq = <10>;
+			qcom,bus-min = <9>;
+			qcom,bus-max = <10>;
+		};
+
+		qcom,gpu-pwrlevel@1 {
+			reg = <1>;
+			qcom,gpu-freq = <640000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+
+			qcom,bus-freq = <10>;
+			qcom,bus-min = <6>;
+			qcom,bus-max = <10>;
+		};
+
+		qcom,gpu-pwrlevel@2 {
+			reg = <2>;
+			qcom,gpu-freq = <599000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+
+			qcom,bus-freq = <8>;
+			qcom,bus-min = <6>;
+			qcom,bus-max = <9>;
+		};
+
+		qcom,gpu-pwrlevel@3 {
+			reg = <3>;
+			qcom,gpu-freq = <545000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+
+			qcom,bus-freq = <8>;
+			qcom,bus-min = <6>;
+			qcom,bus-max = <9>;
+		};
+
+		qcom,gpu-pwrlevel@4 {
+			reg = <4>;
+			qcom,gpu-freq = <492000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+
+			qcom,bus-freq = <6>;
+			qcom,bus-min = <6>;
+			qcom,bus-max = <8>;
+		};
+
+		qcom,gpu-pwrlevel@5 {
+			reg = <5>;
+			qcom,gpu-freq = <421000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+
+			qcom,bus-freq = <6>;
+			qcom,bus-min = <3>;
+			qcom,bus-max = <8>;
+		};
+
+		qcom,gpu-pwrlevel@6 {
+			reg = <6>;
+			qcom,gpu-freq = <350000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+
+			qcom,bus-freq = <3>;
+			qcom,bus-min = <1>;
+			qcom,bus-max = <5>;
+		};
+
+		qcom,gpu-pwrlevel@7 {
+			reg = <7>;
+			qcom,gpu-freq = <285000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+
+			qcom,bus-freq = <2>;
+			qcom,bus-min = <1>;
+			qcom,bus-max = <5>;
+		};
+	};
+};
diff --git a/qcom/waipio-v2-mtp-pm8008.dts b/qcom/waipio-v2-mtp-pm8008.dts
new file mode 100644
index 00000000..6c37dc3b
--- /dev/null
+++ b/qcom/waipio-v2-mtp-pm8008.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipio-v2.dtsi"
+#include "waipio-mtp.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio v2 MTP with PM8008";
+	compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
+	qcom,board-id = <8 0>;
+};
diff --git a/qcom/waipio-v2-mtp-pm8010.dts b/qcom/waipio-v2-mtp-pm8010.dts
new file mode 100644
index 00000000..602c6990
--- /dev/null
+++ b/qcom/waipio-v2-mtp-pm8010.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipio-v2.dtsi"
+#include "waipio-mtp.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio v2 MTP with PM8010";
+	compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
+	qcom,board-id = <0x10008 0>;
+};
diff --git a/qcom/waipio-v2-qrd-pm8008.dts b/qcom/waipio-v2-qrd-pm8008.dts
new file mode 100644
index 00000000..f593627c
--- /dev/null
+++ b/qcom/waipio-v2-qrd-pm8008.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipio-v2.dtsi"
+#include "waipio-qrd.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio v2 QRD with PM8008";
+	compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
+	qcom,board-id = <11 0>;
+};
diff --git a/qcom/waipio-v2-qrd-pm8010-2s.dts b/qcom/waipio-v2-qrd-pm8010-2s.dts
new file mode 100644
index 00000000..319e9743
--- /dev/null
+++ b/qcom/waipio-v2-qrd-pm8010-2s.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipio-v2.dtsi"
+#include "waipio-qrd-2s.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio v2 QRD with PM8010 + 2S";
+	compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
+	qcom,board-id = <0x2000b 0>;
+};
diff --git a/qcom/waipio-v2-qrd-pm8010.dts b/qcom/waipio-v2-qrd-pm8010.dts
new file mode 100644
index 00000000..7d0b91da
--- /dev/null
+++ b/qcom/waipio-v2-qrd-pm8010.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipio-v2.dtsi"
+#include "waipio-qrd.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio v2 QRD with PM8010";
+	compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
+	qcom,board-id = <0x1000b 0>;
+};
diff --git a/qcom/waipio-v2.dts b/qcom/waipio-v2.dts
new file mode 100644
index 00000000..4cd52e2d
--- /dev/null
+++ b/qcom/waipio-v2.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "waipio-v2.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio v2 SoC";
+	compatible = "qcom,waipio";
+	qcom,board-id = <0 0>;
+};
diff --git a/qcom/waipio-v2.dtsi b/qcom/waipio-v2.dtsi
new file mode 100644
index 00000000..5a4ea16f
--- /dev/null
+++ b/qcom/waipio-v2.dtsi
@@ -0,0 +1,185 @@
+#include "waipio.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio v2";
+	compatible = "qcom,waipio";
+	qcom,msm-id = <457 0x20000>;
+};
+
+&CPU4 {
+	dynamic-power-coefficient = <259>;
+};
+
+&CPU5 {
+	dynamic-power-coefficient = <259>;
+};
+
+&CPU6 {
+	dynamic-power-coefficient = <259>;
+};
+
+&CPU7 {
+	dynamic-power-coefficient = <450>;
+};
+
+&clock_camcc {
+	compatible = "qcom,waipio-camcc-v2", "syscon";
+};
+
+&clock_gpucc {
+	compatible = "qcom,waipio-gpucc-v2", "syscon";
+};
+
+&qcom_memlat {
+	ddr {
+		silver {
+			qcom,cpufreq-memfreq-tbl =
+				<  300000  200000 >,
+				<  614400  451000 >,
+				< 1171200  547000 >,
+				< 1478400  768000 >,
+				< 1785600 1555000 >;
+		};
+
+		gold {
+			qcom,cpufreq-memfreq-tbl =
+				<  300000  200000 >,
+				<  633600  451000 >,
+				<  883200  547000 >,
+				< 1113600  768000 >,
+				< 1324800 1555000 >,
+				< 1881600 2092000 >,
+				< 2630400 2736000 >,
+				< 2995200 3196000 >;
+		};
+
+		gold-compute {
+			qcom,cpufreq-memfreq-tbl =
+				< 1881600  200000 >,
+				< 2995200 1555000 >;
+		};
+
+		prime-latfloor {
+			qcom,cpufreq-memfreq-tbl =
+				< 2630400  200000 >,
+				< 2995200 3196000 >;
+		};
+	};
+
+	llcc {
+		silver {
+			qcom,cpufreq-memfreq-tbl =
+				<  300000  150000 >,
+				<  614400  300000 >,
+				< 1478400  466000 >,
+				< 1785600  600000 >;
+		};
+
+		gold {
+			qcom,cpufreq-memfreq-tbl =
+				<  300000  150000 >,
+				<  633600  300000 >,
+				< 1113600  466000 >,
+				< 1324800  600000 >,
+				< 1881600  806000 >,
+				< 2630400  933000 >,
+				< 2995200 1066000 >;
+		};
+
+		gold-compute {
+			qcom,cpufreq-memfreq-tbl =
+				< 1881600  150000 >,
+				< 2995200  600000 >;
+		};
+	};
+
+	l3 {
+		silver {
+			qcom,cpufreq-memfreq-tbl =
+				<  300000  307200 >,
+				<  403200  422400 >,
+				<  614400  537600 >,
+				<  729600  633600 >,
+				<  844800  729600 >,
+				<  960000  825600 >,
+				< 1075200  998400 >,
+				< 1267200 1094400 >,
+				< 1363200 1267200 >,
+				< 1478400 1459200 >,
+				< 1574400 1555200 >,
+				< 1785600 1651200 >;
+		};
+
+		silver-latboost {
+			qcom,cpufreq-memfreq-tbl =
+				<  300000  307200 >,
+				<  403200  729600 >,
+				<  614400  825600 >,
+				<  729600  998400 >,
+				<  844800 1094400 >,
+				<  960000 1267200 >,
+				< 1075200 1459200 >,
+				< 1267200 1555200 >,
+				< 1785600 1651200 >;
+		};
+
+		gold {
+			qcom,cpufreq-memfreq-tbl =
+				<  300000  307200 >,
+				<  633600  537600 >,
+				<  883200  633600 >,
+				< 1113600  825600 >,
+				< 1324800  998400 >,
+				< 1651200 1267200 >,
+				< 1996800 1459200 >,
+				< 2496000 1555200 >,
+				< 2995200 1651200 >;
+		};
+
+		gold-latboost {
+			qcom,cpufreq-memfreq-tbl =
+				<  300000  307200 >,
+				<  633600  998400 >,
+				<  883200 1267200 >,
+				< 1113600 1459200 >,
+				< 1324800 1555200 >,
+				< 2995200 1651200 >;
+		};
+
+		prime {
+			qcom,cpufreq-memfreq-tbl =
+				<  300000  307200 >,
+				<  633600  537600 >,
+				<  883200  633600 >,
+				< 1113600  825600 >,
+				< 1324800  998400 >,
+				< 1651200 1267200 >,
+				< 1996800 1459200 >,
+				< 2496000 1555200 >,
+				< 2995200 1651200 >;
+		};
+
+		prime-compute {
+			qcom,cpufreq-memfreq-tbl =
+				< 2054400  307200 >,
+				< 2995200 1651200 >;
+		};
+	};
+
+	ddrqos {
+		gold {
+			qcom,cpufreq-memfreq-tbl =
+				< 1881600 0 >,
+				< 2995200 1 >;
+		};
+
+		prime-latfloor {
+			qcom,cpufreq-memfreq-tbl =
+				< 2054400 0 >,
+				< 2995200 1 >;
+		};
+	};
+
+};
+
+#include "waipio-v2-gpu.dtsi"
diff --git a/qcom/waipio-vm-cdp.dts b/qcom/waipio-vm-cdp.dts
new file mode 100644
index 00000000..93711c0d
--- /dev/null
+++ b/qcom/waipio-vm-cdp.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "waipio-vm.dtsi"
+#include "waipio-vm-cdp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio SVM CDP";
+	compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
+	qcom,board-id = <0x10001 0>;
+};
diff --git a/qcom/waipio-vm-cdp.dtsi b/qcom/waipio-vm-cdp.dtsi
new file mode 100644
index 00000000..96a064fe
--- /dev/null
+++ b/qcom/waipio-vm-cdp.dtsi
@@ -0,0 +1,15 @@
+&qupv3_se4_i2c {
+	status = "ok";
+	focaltech@38 {
+		compatible = "focaltech,fts_ts";
+		reg = <0x38>;
+		focaltech,display-coords = <0 0 1080 2340>;
+		focaltech,trusted-touch-mode = "vm_mode";
+		focaltech,touch-environment = "tvm";
+		focaltech,trusted-touch-spi-irq = <754>;
+		focaltech,trusted-touch-io-bases = <0xF110000 0xF111000 0xF112000 0xF113000
+						0xF114000 0xF115000 0x990000 0x00910000>;
+		focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000
+						0x1000 0x1000 0x1000 0x4000>;
+	};
+};
diff --git a/qcom/waipio-vm-dma-heaps.dtsi b/qcom/waipio-vm-dma-heaps.dtsi
new file mode 100644
index 00000000..b5b0b73d
--- /dev/null
+++ b/qcom/waipio-vm-dma-heaps.dtsi
@@ -0,0 +1,13 @@
+#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h>
+
+&soc {
+	qcom,dma-heaps {
+		compatible = "qcom,dma-heaps";
+
+		qcom,tui {
+			qcom,dma-heap-name = "qcom,tui";
+			qcom,dma-heap-type = <HEAP_TYPE_CARVEOUT>;
+			qcom,dynamic-heap;
+		};
+	};
+};
diff --git a/qcom/waipio-vm-mtp.dts b/qcom/waipio-vm-mtp.dts
new file mode 100644
index 00000000..5f098c53
--- /dev/null
+++ b/qcom/waipio-vm-mtp.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "waipio-vm.dtsi"
+#include "waipio-vm-mtp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio SVM MTP";
+	compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
+	qcom,board-id = <0x10008 0>;
+};
diff --git a/qcom/waipio-vm-mtp.dtsi b/qcom/waipio-vm-mtp.dtsi
new file mode 100644
index 00000000..2ccc3bb0
--- /dev/null
+++ b/qcom/waipio-vm-mtp.dtsi
@@ -0,0 +1,16 @@
+
+&qupv3_se4_i2c {
+	status = "ok";
+	focaltech@38 {
+		compatible = "focaltech,fts_ts";
+		reg = <0x38>;
+		focaltech,display-coords = <0 0 1080 2340>;
+		focaltech,trusted-touch-mode = "vm_mode";
+		focaltech,touch-environment = "tvm";
+		focaltech,trusted-touch-spi-irq = <754>;
+		focaltech,trusted-touch-io-bases = <0xF110000 0xF111000 0xF112000 0xF113000
+						0xF114000 0xF115000 0x990000 0x00910000>;
+		focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000
+						0x1000 0x1000 0x1000 0x4000>;
+	};
+};
diff --git a/qcom/waipio-vm-qrd.dts b/qcom/waipio-vm-qrd.dts
new file mode 100644
index 00000000..738432d5
--- /dev/null
+++ b/qcom/waipio-vm-qrd.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "waipio-vm.dtsi"
+#include "waipio-vm-qrd.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio SVM QRD";
+	compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
+	qcom,board-id = <0x1000B 0>;
+};
diff --git a/qcom/waipio-vm-qrd.dtsi b/qcom/waipio-vm-qrd.dtsi
new file mode 100644
index 00000000..ae8b339f
--- /dev/null
+++ b/qcom/waipio-vm-qrd.dtsi
@@ -0,0 +1,26 @@
+&soc {
+};
+
+&qupv3_se4_i2c {
+	status = "disabled";
+};
+
+&qupv3_se4_spi {
+	status = "ok";
+	qcom,spi-touch-active = "focaltech,fts_ts";
+
+	focaltech@0 {
+		compatible = "focaltech,fts_ts";
+		reg = <0x0>;
+		spi-max-frequency = <6000000>;
+		focaltech,max-touch-number = <5>;
+		focaltech,display-coords = <0 0 1080 2340>;
+		focaltech,ic-type = <0x3658D488>;
+
+		focaltech,trusted-touch-mode = "vm_mode";
+		focaltech,touch-environment = "tvm";
+		focaltech,trusted-touch-spi-irq = <754>;
+		focaltech,trusted-touch-io-bases = <0xF110000 0xF111000 0xF112000 0xF113000 0xF114000 0xF115000 0x990000 0x00910000>;
+		focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>;
+	};
+};
diff --git a/qcom/waipio-vm-rumi.dts b/qcom/waipio-vm-rumi.dts
new file mode 100644
index 00000000..516f9c1c
--- /dev/null
+++ b/qcom/waipio-vm-rumi.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "waipio-vm.dtsi"
+#include "waipio-vm-rumi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio SVM RUMI";
+	compatible = "qcom,waipio-rumi", "qcom,waipio", "qcom,rumi";
+	qcom,board-id = <15 0>;
+};
diff --git a/qcom/waipio-vm-rumi.dtsi b/qcom/waipio-vm-rumi.dtsi
new file mode 100644
index 00000000..2cf87a3d
--- /dev/null
+++ b/qcom/waipio-vm-rumi.dtsi
@@ -0,0 +1,3 @@
+&arch_timer {
+	clock-frequency = <500000>;
+};
diff --git a/qcom/waipio-vm.dtsi b/qcom/waipio-vm.dtsi
new file mode 100644
index 00000000..84b9ca61
--- /dev/null
+++ b/qcom/waipio-vm.dtsi
@@ -0,0 +1,374 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-waipio.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+
+/ {
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+	qcom,msm-id = <457 0x10000>;
+	interrupt-parent = <&vgic>;
+
+	qcom,mem-buf {
+		compatible = "qcom,mem-buf";
+		qcom,mem-buf-capabilities = "consumer";
+		qcom,vmid = <45>;
+	};
+
+	qcom,mem-buf-msgq {
+		compatible = "qcom,mem-buf-msgq";
+	};
+
+	chosen {
+		bootargs = "nokaslr log_buf_len=256K root=/dev/ram rw init=/init console=hvc0 loglevel=8";
+	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		system_cma: linux,cma {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x400000>;
+			linux,cma-default;
+		};
+	};
+
+	cpus {
+		#address-cells = <0x2>;
+		#size-cells = <0x0>;
+
+		CPU0: cpu@0 {
+			compatible = "arm,armv8";
+			reg = <0x0 0x0>;
+			device_type = "cpu";
+			enable-method = "psci";
+			cpu-idle-states = <&CPU_PWR_DWN
+					   &CLUSTER_PWR_DWN>;
+		};
+
+		CPU1: cpu@100 {
+			compatible = "arm,armv8";
+			reg = <0x0 0x100>;
+			device_type = "cpu";
+			enable-method = "psci";
+			cpu-idle-states = <&CPU_PWR_DWN
+					   &CLUSTER_PWR_DWN>;
+		};
+	};
+
+	idle-states {
+		CPU_PWR_DWN: c4 {  /* Using Gold C4 latencies */
+			compatible = "arm,idle-state";
+			idle-state-name = "rail-pc";
+			entry-latency-us = <369>;
+			exit-latency-us = <1502>;
+			min-residency-us = <4488>;
+			arm,psci-suspend-param = <0x40000004>;
+			local-timer-stop;
+		};
+
+		CLUSTER_PWR_DWN: d4 { /* C4+D4 */
+			compatible = "arm,idle-state";
+			idle-state-name = "l3-pc";
+			entry-latency-us = <584>;
+			exit-latency-us = <2332>;
+			min-residency-us = <6118>;
+			arm,psci-suspend-param = <0x40000044>;
+			local-timer-stop;
+		};
+	};
+
+	qrtr-gunyah {
+		compatible = "qcom,qrtr-gunyah";
+		gunyah-label = <3>;
+	};
+
+	qcom,vm-config {
+		compatible = "qcom,vm-1.0";
+		vm-type = "aarch64-guest";
+		boot-config = "fdt,unified";
+		os-type = "linux";
+		kernel-entry-segment = "kernel";
+		kernel-entry-offset = <0x0 0x0>;
+		vendor = "Qualcomm";
+		image-name = "qcom,trustedvm";
+		qcom,pasid = <0x0 0x1c>;
+
+		iomemory-ranges = <0x0 0x92c000 0x0 0x92c000 0x0 0x4000 0x0
+				0x0 0xc400000 0x0 0xc400000 0x0 0x3000 0x1
+				0x0 0xc42d000 0x0 0xc42d000 0x0 0x4000 0x1
+				0x0 0xc440000 0x0 0xc440000 0x0 0x80000 0x1
+				0x0 0xc4c0000 0x0 0xc4c0000 0x0 0x10000 0x1
+				0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>;
+
+		gic-irq-ranges = <283 283>; /* PVM->SVM IRQ transfer */
+
+		memory {
+			#address-cells = <0x2>;
+			#size-cells = <0x0>;
+			base-address = <0x0 0xe0b00000>;
+			size-min = <0x0 0x7a00000>;    /* 122 MB */
+		};
+
+		segments {
+			ramdisk = <2>; /* 8MB */
+		};
+
+		vcpus {
+			config = "/cpus";
+			affinity = "static";
+			affinity-map = <0x5 0x6>;
+			sched-priority = <0>;       /* relative to PVM */
+			sched-timeslice = <2000>;   /* in ms */
+		};
+
+		interrupts {
+			config = &vgic;
+		};
+
+		vdevices {
+			generate = "/hypervisor";
+			rm-rpc {
+				vdevice-type = "rm-rpc";
+				generate = "/hypervisor/qcom,resource-mgr";
+				console-dev;
+				message-size = <0x000000f0>;
+				queue-depth = <0x00000008>;
+				qcom,label = <0x1>;
+			};
+
+			virtio-mmio@0 {
+				vdevice-type = "virtio-mmio";
+				generate = "/virtio-mmio";
+				peer-default;
+				vqs-num = <0x1>;
+				push-compatible = "virtio,mmio";
+				dma-coherent;
+				dma_base = <0x0 0x0>;
+				memory {
+					qcom,label = <0x11>;
+					#address-cells = <0x2>;
+					base = <0x0 0xFFEFC000>;
+				};
+			};
+
+			swiotlb-shm {
+				vdevice-type = "shm";
+				generate = "/swiotlb";
+				push-compatible = "swiotlb";
+				peer-default;
+				dma_base = <0x0 0x4000>;
+				memory {
+					qcom,label = <0x12>;
+					#address-cells = <0x2>;
+					base = <0x0 0xFFF00000>;
+				};
+			};
+
+			mem-buf-message-queue-pair {
+				vdevice-type = "message-queue-pair";
+				generate = "/hypervisor/membuf-msgq-pair";
+				message-size = <0x000000f0>;
+				queue-depth = <0x00000008>;
+				peer-default;
+				qcom,label = <0x0000001>;
+			};
+
+			display-message-queue-pair {
+				vdevice-type = "message-queue-pair";
+				generate = "/hypervisor/display-msgq-pair";
+				message-size = <0x000000f0>;
+				queue-depth = <0x00000008>;
+				peer-default;
+				qcom,label = <0x0000002>;
+			};
+
+			qrtr-shm {
+				vdevice-type = "shm-doorbell";
+				generate = "/hypervisor/qrtr-shm";
+				push-compatible = "qcom,qrtr-gunyah-gen";
+				peer-default;
+				memory {
+					qcom,label = <0x3>;
+					allocate-base;
+				};
+			};
+
+			gpiomem0 {
+				vdevice-type = "iomem";
+				patch = "/soc/tlmm-vm-mem-access";
+				push-compatible = "qcom,tlmm-vm-mem-access";
+				peer-default;
+				memory {
+					qcom,label = <0x8>;
+					qcom,mem-info-tag = <0x2>;
+					allocate-base;
+				};
+			};
+		};
+	};
+
+	firmware: firmware {
+		scm {
+			compatible = "qcom,scm";
+		};
+	};
+
+	soc: soc { };
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0 0 0 0xffffffff>;
+	compatible = "simple-bus";
+
+	spmi_bus: qcom,spmi@c42d000 {
+		compatible = "qcom,spmi-pmic-arb";
+		reg = <0xc42d000 0x4000>,
+		      <0xc400000 0x3000>,
+		      <0xc500000 0x400000>,
+		      <0xc440000 0x80000>,
+		      <0xc4c0000 0x10000>;
+		reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
+		#address-cells = <2>;
+		#size-cells = <0>;
+		cell-index = <0>;
+		qcom,channel = <0>;
+		qcom,ee = <0>;
+		qcom,bus-id = <0>;
+	};
+
+	vm_tlmm_irq: vm-tlmm-irq@0 {
+		compatible = "qcom,tlmm-vm-irq";
+		reg = <0x0 0x0>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	tlmm: pinctrl@f000000 {
+		compatible = "qcom,waipio-vm-pinctrl";
+		reg = <0x0F000000 0x1000000>;
+		interrupts-extended = <&vm_tlmm_irq 1 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		/* Valid pins */
+		gpios = /bits/ 16 <64 65 66 67 0 4 86 87>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	tlmm-vm-mem-access {
+		compatible = "qcom,tlmm-vm-mem-access";
+		tlmm-vm-gpio-list = <365 366 367 368 301 305 387 388>;
+	};
+
+	vgic: interrupt-controller@17100000 {
+		compatible = "arm,gic-v3";
+		interrupt-controller;
+		#interrupt-cells = <0x3>;
+		#redistributor-regions = <1>;
+		redistributor-stride = <0x0 0x40000>;
+		reg = <0x17100000 0x10000>,     /* GICD */
+		      <0x17180000 0x100000>;    /* GICR * 8 */
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		always-on;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <19200000>;
+	};
+
+	/*
+	 * QUPv3 Instances
+	 * North 4 : SE 4
+	 */
+
+	/* QUPv3_0 wrapper instance: North QUP */
+	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
+		compatible = "qcom,qupv3-geni-se";
+		reg = <0x9c0000 0x2000>;
+		status = "ok";
+	};
+
+	/* GPI */
+	gpi_dma0: qcom,gpi-dma@900000 {
+		compatible = "qcom,gpi-dma";
+		#dma-cells = <5>;
+		reg = <0x900000 0x60000>;
+		reg-names = "gpi-top";
+		interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,max-num-gpii = <12>;
+		qcom,gpii-mask = <0x80>;
+		qcom,ev-factor = <2>;
+		qcom,gpi-ee-offset = <0x10000>;
+		qcom,le-vm;
+		status = "ok";
+	};
+
+	/* I2C SE */
+	qupv3_se4_i2c: i2c@990000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x990000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		dmas = <&gpi_dma0 0 4 3 64 0>,
+			<&gpi_dma0 1 4 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_0>;
+		qcom,le-vm;
+		status = "disabled";
+	};
+
+	qupv3_se4_spi: spi@990000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x990000 0x4000>;
+		reg-names = "se_phys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		dmas = <&gpi_dma0 0 4 1 64 0>,
+			<&gpi_dma0 1 4 1 64 0>;
+		dma-names = "tx", "rx";
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		qcom,le-vm;
+		status = "disabled";
+	};
+
+	qcom_smcinvoke {
+		compatible = "qcom,smcinvoke";
+	};
+
+	qtee_shmbridge {
+		compatible = "qcom,tee-shared-memory-bridge";
+		qcom,custom-bridge-size = <512>;
+		qcom,support-hypervisor;
+	};
+};
+
+#include "waipio-vm-dma-heaps.dtsi"
+#include "msm-arm-smmu-waipio-vm.dtsi"
diff --git a/qcom/waipio.dts b/qcom/waipio.dts
new file mode 100644
index 00000000..6e7ae5fa
--- /dev/null
+++ b/qcom/waipio.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "waipio.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio SoC";
+	compatible = "qcom,waipio";
+	qcom,board-id = <0 0>;
+};
diff --git a/qcom/waipio.dtsi b/qcom/waipio.dtsi
new file mode 100644
index 00000000..685deaab
--- /dev/null
+++ b/qcom/waipio.dtsi
@@ -0,0 +1,3661 @@
+#include <dt-bindings/clock/qcom,aop-qmp.h>
+#include <dt-bindings/clock/qcom,camcc-waipio.h>
+#include <dt-bindings/clock/qcom,dispcc-waipio.h>
+#include <dt-bindings/clock/qcom,gcc-waipio.h>
+#include <dt-bindings/clock/qcom,gpucc-waipio.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,videocc-waipio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/interconnect/qcom,waipio.h>
+#include <dt-bindings/soc/qcom,ipcc.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/soc/qcom,ipcc.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/power/qcom-aoss-qmp.h>
+
+/ {
+	model = "Qualcomm Technologies, Inc. Waipio";
+	compatible = "qcom,waipio";
+	qcom,msm-id = <457 0x10000>;
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen: chosen {
+		bootargs = "console=ttyMSM0,115200n8 loglevel=6 kpti=0 log_buf_len=256K kernel.panic_on_rcu_stall=1 swiotlb=0 loop.max_part=7 cgroup.memory=nokmem,nosocket pcie_ports=compat service_locator.enable=1 msm_rtb.filter=0x237 allow_mismatched_32bit_el0 cpufreq.default_governor=performance pelt=8 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 irqaffinity=0-3 ftrace_dump_on_oops";
+	};
+
+	memory { device_type = "memory"; reg = <0 0 0 0>; };
+
+	ddr-regions { };
+
+	reserved_memory: reserved-memory { };
+
+	mem-offline {
+		compatible = "qcom,mem-offline";
+		offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
+				<0x1 0xc0000000 0x0 0xc0000000>,
+				<0x2 0xc0000000 0x1 0x40000000>;
+		granule = <512>;
+		mboxes = <&qmp_aop 0>;
+	};
+
+	aliases: aliases {
+		serial0 = &qupv3_se7_2uart;
+		hsuart0 = &qupv3_se20_4uart;
+		sdhc2 = &sdhc_2;
+		ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
+		pci-domain0 = &pcie0; /* PCIe0 domain */
+		pci-domain1 = &pcie1; /* PCIe1 domain */
+	};
+
+	sram: sram@17D09400 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "mmio-sram";
+		reg = <0x0 0x17D09400 0x0 0x400>;
+		ranges = <0x0 0x0 0x0 0x17D09400 0x0 0x400>;
+
+		cpu_scp_lpri: scp-shmem@0 {
+			compatible = "arm,scp-shmem";
+			reg = <0x0 0x0 0x0 0x400>;
+		};
+	};
+
+	firmware: firmware { };
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+			cpu-idle-states = <&SILVER_OFF>;
+			power-domains = <&CPU_PD0>;
+			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0 4>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			#cooling-cells = <2>;
+			L2_0: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+
+				L3_0: l3-cache {
+					compatible = "arm,arch-cache";
+					cache-level = <3>;
+				};
+			};
+		};
+
+		CPU1: cpu@100 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+			cpu-idle-states = <&SILVER_OFF>;
+			power-domains = <&CPU_PD1>;
+			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0 4>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			#cooling-cells = <2>;
+		};
+
+		CPU2: cpu@200 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			next-level-cache = <&L2_2>;
+			cpu-idle-states = <&SILVER_OFF>;
+			power-domains = <&CPU_PD2>;
+			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0 4>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			#cooling-cells = <2>;
+			L2_2: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU3: cpu@300 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			next-level-cache = <&L2_2>;
+			cpu-idle-states = <&SILVER_OFF>;
+			power-domains = <&CPU_PD3>;
+			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0 4>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			#cooling-cells = <2>;
+		};
+
+		CPU4: cpu@400 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x400>;
+			enable-method = "psci";
+			next-level-cache = <&L2_4>;
+			cpu-idle-states = <&GOLD_OFF>;
+			power-domains = <&CPU_PD4>;
+			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 1 4>;
+			capacity-dmips-mhz = <1980>;
+			dynamic-power-coefficient = <251>;
+			#cooling-cells = <2>;
+			L2_4: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+
+			};
+		};
+
+		CPU5: cpu@500 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x500>;
+			enable-method = "psci";
+			next-level-cache = <&L2_5>;
+			cpu-idle-states = <&GOLD_OFF>;
+			power-domains = <&CPU_PD5>;
+			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 1 4>;
+			capacity-dmips-mhz = <1980>;
+			dynamic-power-coefficient = <251>;
+			#cooling-cells = <2>;
+			L2_5: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU6: cpu@600 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x600>;
+			enable-method = "psci";
+			next-level-cache = <&L2_6>;
+			cpu-idle-states = <&GOLD_OFF>;
+			power-domains = <&CPU_PD6>;
+			qcom,freq-domain = <&cpufreq_hw 1 4>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1980>;
+			dynamic-power-coefficient = <251>;
+			#cooling-cells = <2>;
+			L2_6: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU7: cpu@700 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x700>;
+			enable-method = "psci";
+			next-level-cache = <&L2_7>;
+			cpu-idle-states = <&GOLD_OFF>;
+			power-domains = <&CPU_PD7>;
+			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 2 4>;
+			capacity-dmips-mhz = <2097>;
+			dynamic-power-coefficient = <396>;
+			#cooling-cells = <2>;
+			L2_7: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+
+				core3 {
+					cpu = <&CPU3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&CPU4>;
+				};
+
+				core1 {
+					cpu = <&CPU5>;
+				};
+
+				core2 {
+					cpu = <&CPU6>;
+				};
+			};
+
+			cluster2 {
+				core0 {
+					cpu = <&CPU7>;
+				};
+			};
+		};
+	};
+
+	idle-states {
+		SILVER_OFF: silver-c4 {  /* C4 */
+			compatible = "arm,idle-state";
+			idle-state-name = "rail-pc";
+			entry-latency-us = <274>;
+			exit-latency-us = <480>;
+			min-residency-us = <3934>;
+			arm,psci-suspend-param = <0x40000004>;
+			local-timer-stop;
+		};
+
+		GOLD_OFF: gold-c4 {  /* C4 */
+			compatible = "arm,idle-state";
+			idle-state-name = "rail-pc";
+			entry-latency-us = <327>;
+			exit-latency-us = <1502>;
+			min-residency-us = <4488>;
+			arm,psci-suspend-param = <0x40000004>;
+			local-timer-stop;
+		};
+
+		CLUSTER_PWR_DN: cluster-d4 { /* D4 */
+			compatible = "domain-idle-state";
+			idle-state-name = "l3-off";
+			entry-latency-us = <584>;
+			exit-latency-us = <2332>;
+			min-residency-us = <6118>;
+			arm,psci-suspend-param = <0x41000044>;
+		};
+
+		APSS_OFF: cluster-e3 { /* E3 */
+			compatible = "domain-idle-state";
+			idle-state-name = "llcc-off";
+			entry-latency-us = <2893>;
+			exit-latency-us = <4023>;
+			min-residency-us = <9987>;
+			arm,psci-suspend-param = <0x4100c344>;
+		};
+	};
+
+	soc: soc { };
+};
+
+&firmware {
+	qcom_scm {
+		compatible = "qcom,scm";
+		qcom,dload-mode = <&tcsr 0x13000>;
+	};
+
+	qtee_shmbridge {
+		compatible = "qcom,tee-shared-memory-bridge";
+	};
+
+	qcom_smcinvoke {
+		compatible = "qcom,smcinvoke";
+	};
+
+	android {
+		compatible = "android,firmware";
+		vbmeta {
+			compatible = "android,vbmeta";
+			parts = "vbmeta,boot,system,vendor,dtbo,recovery";
+		};
+
+		fstab {
+			compatible = "android,fstab";
+			vendor {
+				compatible = "android,vendor";
+				dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
+				type = "ext4";
+				mnt_flags = "ro,barrier=1,discard";
+				fsmgr_flags = "wait,slotselect,avb";
+				status = "ok";
+			};
+		};
+	};
+};
+
+&reserved_memory {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	ranges;
+
+	hyp_mem: hyp_region@80000000 {
+		no-map;
+		reg = <0x0 0x80000000 0x0 0x600000>;
+	};
+
+	xbl_dt_log_mem: xbl_dt_log@80600000 {
+		no-map;
+		reg = <0x0 0x80600000 0x0 0x40000>;
+	};
+
+	xbl_ramdump_mem: xbl_ramdump_region@80640000 {
+		no-map;
+		reg = <0x0 0x80640000 0x0 0x180000>;
+	};
+
+	xbl_sc_mem: xbl_sc_region@807c0000 {
+		no-map;
+		reg = <0x0 0x807c0000 0x0 0x40000>;
+	};
+
+	aop_image_mem: aop_image_region@80800000 {
+		no-map;
+		reg = <0x0 0x80800000 0x0 0x60000>;
+	};
+
+	aop_cmd_db_mem: aop_cmd_db_region@80860000 {
+		compatible = "qcom,cmd-db";
+		no-map;
+		reg = <0x0 0x80860000 0x0 0x20000>;
+	};
+
+	aop_config_mem: aop_config_region@80880000 {
+		no-map;
+		reg = <0x0 0x80880000 0x0 0x20000>;
+	};
+
+	tme_crash_dump_mem: tme_crash_dump_region@808a0000 {
+		no-map;
+		reg = <0x0 0x808a0000 0x0 0x40000>;
+	};
+
+	tme_log_mem: tme_log_region@808e0000 {
+		no-map;
+		reg = <0x0 0x808e0000 0x0 0x4000>;
+	};
+
+	uefi_log_mem: uefi_log_region@808e4000 {
+		no-map;
+		reg = <0x0 0x808e4000 0x0 0x10000>;
+	};
+
+	/* secdata region can be reused by apps */
+
+	smem_mem: smem_region@80900000 {
+		no-map;
+		reg = <0x0 0x80900000 0x0 0x200000>;
+	};
+
+	cpucp_fw_mem: cpucp_fw_region@80b00000 {
+		no-map;
+		reg = <0x0 0x80b00000 0x0 0x100000>;
+	};
+
+	cdsp_secure_heap: cdsp_secure_heap_region@80c00000 {
+		no-map;
+		reg = <0x0 0x80c00000 0x0 0x4600000>;
+	};
+
+	camera_mem: camera_region@85200000 {
+		no-map;
+		reg = <0x0 0x85200000 0x0 0x500000>;
+	};
+
+	video_mem: video_region@85700000 {
+		no-map;
+		reg = <0x0 0x85700000 0x0 0x700000>;
+	};
+
+	adsp_mem: adsp_region@85e00000 {
+		no-map;
+		reg = <0x0 0x85e00000 0x0 0x2100000>;
+	};
+
+	slpi_mem: slpi_region@88000000 {
+		no-map;
+		reg = <0x0 0x88000000 0x0 0x1900000>;
+	};
+
+	cdsp_mem: cdsp_region@89900000 {
+		no-map;
+		reg = <0x0 0x89900000 0x0 0x2000000>;
+	};
+
+	ipa_fw_mem: ipa_fw_region@8b900000 {
+		no-map;
+		reg = <0x0 0x8b900000 0x0 0x10000>;
+	};
+
+	ipa_gsi_mem: ipa_gsi_region@8b910000 {
+		no-map;
+		reg = <0x0 0x8b910000 0x0 0xa000>;
+	};
+
+	gpu_micro_code_mem: gpu_micro_code_region@8b91a000 {
+		no-map;
+		reg = <0x0 0x8b91a000 0x0 0x2000>;
+	};
+
+	spss_region_mem: spss_region_region@8ba00000 {
+		no-map;
+		reg = <0x0 0x8ba00000 0x0 0x180000>;
+	};
+
+	/* First part of the "SPU secure shared memory" region */
+	spu_tz_shared_mem: spu_tz_shared_mem@8bb80000 {
+		no-map;
+		reg = <0x0 0x8bb80000 0x0 0x60000>;
+	};
+
+	/* Second part of the "SPU secure shared memory" region */
+	spu_modem_shared_mem: spu_modem_shared_mem@8bbe0000 {
+		no-map;
+		reg = <0x0 0x8bbe0000 0x0 0x20000>;
+	};
+
+	mpss_mem: mpss_region@8bc00000 {
+		no-map;
+		reg = <0x0 0x8bc00000 0x0 0x13200000>;
+	};
+
+	cvp_mem: cvp_region@9ee00000 {
+		no-map;
+		reg = <0x0 0x9ee00000 0x0 0x700000>;
+	};
+
+	global_sync_mem: global_sync_region@a6f00000 {
+		no-map;
+		reg = <0x0 0xa6f00000 0x0 0x100000>;
+	};
+
+	/* uefi region can be reused by apps */
+
+	/* Linux kernel image is loaded at 0xa0000000 */
+
+	oem_vm_mem: oem_vm_region@bb000000 {
+		no-map;
+		reg = <0x0 0xbb000000 0x0 0x5000000>;
+	};
+
+	mte_mem: mte_region@c0000000 {
+		no-map;
+		reg = <0x0 0xc0000000 0x0 0x20000000>;
+	};
+
+	qheebsp_reserved_mem: qheebsp_reserved_region@e0000000 {
+		no-map;
+		reg = <0x0 0xe0000000 0x0 0x600000>;
+	};
+
+	cpusys_vm_mem: cpusys_vm_region@e0600000 {
+		no-map;
+		reg = <0x0 0xe0600000 0x0 0x400000>;
+	};
+
+	hyp_reserved_mem: hyp_reserved_region@e0a00000 {
+		no-map;
+		reg = <0x0 0xe0a00000 0x0 0x100000>;
+	};
+
+	trust_ui_vm_mem: trust_ui_vm_region@e0b00000 {
+		no-map;
+		reg = <0x0 0xe0b00000 0x0 0x4af3000>;
+	};
+
+	trust_ui_vm_qrtr: trust_ui_vm_qrtr@e55f3000 {
+		no-map;
+		reg = <0x0 0xe55f3000 0x0 0x9000>;
+	};
+
+	trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring@e55fc000 {
+		no-map;
+		reg = <0x0 0xe55fc000 0x0 0x4000>;
+		gunyah-label = <0x11>;
+	};
+
+	trust_ui_vm_swiotlb: trust_ui_vm_swiotlb@e5600000 {
+		no-map;
+		reg = <0x0 0xe5600000 0x0 0x100000>;
+		gunyah-label = <0x12>;
+	};
+
+	tz_stat_mem: tz_stat_region@e8800000 {
+		no-map;
+		reg = <0x0 0xe8800000 0x0 0x100000>;
+	};
+
+	tags_mem: tags_region@e8900000 {
+		no-map;
+		reg = <0x0 0xe8900000 0x0 0x1200000>;
+	};
+
+	qtee_mem: qtee_region@e9b00000 {
+		no-map;
+		reg = <0x0 0xe9b00000 0x0 0x500000>;
+	};
+
+	non_secure_display_memory: non_secure_display_region {
+		compatible = "shared-dma-pool";
+		reusable;
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		size = <0x0 0xa400000>;
+		alignment = <0x0 0x400000>;
+	};
+
+	va_md_mem: va_md_mem_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>;
+		reusable;
+		size = <0 0x1000000>;
+	};
+
+	sp_mem: sp_region {  /* SPSS-HLOS ION shared mem */
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1000000>;
+	};
+
+	user_contig_mem: user_contig_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1000000>;
+	};
+
+	qseecom_mem: qseecom_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1400000>;
+	};
+
+	qseecom_ta_mem: qseecom_ta_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1000000>;
+	};
+
+	cnss_wlan_mem: cnss_wlan_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1400000>;
+	};
+
+	audio_cma_mem: audio_cma_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1C00000>;
+	};
+
+	cdsp_eva_mem: cdsp_eva_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x400000>;
+	};
+
+	adsp_mem_heap: adsp_heap_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0xC00000>;
+	};
+
+	sdsp_mem: sdsp_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x800000>;
+	};
+
+	/* global autoconfigured region for contiguous allocations */
+	system_cma: linux,cma {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x2000000>;
+		linux,cma-default;
+	};
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0 0 0 0xffffffff>;
+	compatible = "simple-bus";
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+
+		CPU_PD0: cpu-pd0 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD1: cpu-pd1 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD2: cpu-pd2 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD3: cpu-pd3 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD4: cpu-pd4 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD5: cpu-pd5 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD6: cpu-pd6 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CPU_PD7: cpu-pd7 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+		};
+
+		CLUSTER_PD: cluster-pd {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&CLUSTER_PWR_DN &APSS_OFF>;
+		};
+	};
+
+	slimbam: bamdma@3304000 {
+		compatible = "qcom,bam-v1.7.0";
+		qcom,controlled-remotely;
+		reg = <0x3304000 0x20000>, <0x326b000 0x1000>;
+		reg-names = "bam", "bam_remote_mem";
+		num-channels  = <31>;
+		interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
+		#dma-cells = <1>;
+		qcom,ee = <1>;
+		qcom,num-ees = <2>;
+	};
+
+	slim_msm: slim@3340000 {
+		compatible = "qcom,slim-ngd-v1.5.0";
+		reg = <0x3340000 0x2C000>, <0x326a000 0x1000>;
+		reg-names = "ctrl", "slimbus_remote_mem";
+		interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,apps-ch-pipes = <0x0>;
+		qcom,ea-pc = <0x3c0>;
+		dmas = <&slimbam 3>, <&slimbam 4>;
+		dma-names = "rx", "tx";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "ok";
+		ngd@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			/* slimbus child nodes */
+			slimbus: btfmslim-driver {
+				compatible = "slim217,221";
+				reg = <1 0>;
+			};
+		};
+	};
+
+	intc: interrupt-controller@17100000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		ranges;
+		#redistributor-regions = <1>;
+		redistributor-stride = <0x0 0x40000>;
+		reg = <0x17100000 0x10000>,     /* GICD */
+		      <0x17180000 0x200000>;    /* GICR * 8 */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+		gic_its: msi-controller@17140000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x17140000 0x20000>;
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <19200000>;
+	};
+
+	memtimer: timer@17420000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		compatible = "arm,armv7-timer-mem";
+		reg = <0x17420000 0x1000>;
+		clock-frequency = <19200000>;
+
+		frame@17421000 {
+			frame-number = <0>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17421000 0x1000>,
+			      <0x17422000 0x1000>;
+		};
+
+		frame@17423000 {
+			frame-number = <1>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17423000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17425000 {
+			frame-number = <2>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17425000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17427000 {
+			frame-number = <3>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17427000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17429000 {
+			frame-number = <4>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x17429000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@1742b000 {
+			frame-number = <5>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x1742b000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@1742d000 {
+			frame-number = <6>;
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x1742d000 0x1000>;
+			status = "disabled";
+		};
+	};
+
+	rimps: qcom,rimps@17400000 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "qcom,rimps";
+		reg =   <0x17400000 0x10>,
+			<0x17d90000 0x2000>;
+		#mbox-cells = <1>;
+		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	scmi: qcom,scmi {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "arm,scmi";
+		mboxes = <&rimps 0>;
+		mbox-names = "tx";
+		shmem = <&cpu_scp_lpri>;
+
+		scmi_memlat: protocol@80 {
+			reg = <0x80>;
+			#clock-cells = <1>;
+		};
+
+		scmi_pmu: protocol@86 {
+			reg = <0x86>;
+			#clock-cells = <1>;
+		};
+	};
+
+	rimps_log: qcom,rimps_log@17d09c00 {
+		compatible = "qcom,rimps-log";
+		reg = <0x17d09c00 0x200>, <0x17d09e00 0x200>;
+		mboxes = <&rimps 1>;
+	};
+
+	cpu_pmu: cpu-pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	vendor_hooks: qcom,cpu-vendor-hooks {
+		compatible = "qcom,cpu-vendor-hooks";
+	};
+
+	logbuf: qcom,logbuf-vendor-hooks {
+		compatible = "qcom,logbuf-vendor-hooks";
+	};
+
+	qcom,msm-imem@146aa000 {
+		compatible = "qcom,msm-imem";
+		reg = <0x146aa000 0x1000>;
+		ranges = <0x0 0x146aa000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mem_dump_table@10 {
+			compatible = "qcom,msm-imem-mem_dump_table";
+			reg = <0x10 0x8>;
+		};
+
+		restart_reason@65c {
+			compatible = "qcom,msm-imem-restart_reason";
+			reg = <0x65c 0x4>;
+		};
+
+		dload_type@1c {
+			compatible = "qcom,msm-imem-dload-type";
+			reg = <0x1c 0x4>;
+		};
+
+		boot_stats@6b0 {
+			compatible = "qcom,msm-imem-boot_stats";
+			reg = <0x6b0 0x20>;
+		};
+
+		kaslr_offset@6d0 {
+			compatible = "qcom,msm-imem-kaslr_offset";
+			reg = <0x6d0 0xc>;
+		};
+
+		pil@94c {
+			compatible = "qcom,pil-reloc-info";
+			reg = <0x94c 0xc8>;
+		};
+
+		pil@6dc {
+			compatible = "qcom,msm-imem-pil-disable-timeout";
+			reg = <0x6dc 0x4>;
+		};
+
+		diag_dload@c8 {
+			compatible = "qcom,msm-imem-diag-dload";
+			reg = <0xc8 0xc8>;
+		};
+	};
+
+	qcom,msm-rtb {
+		compatible = "qcom,msm-rtb";
+		qcom,rtb-size = <0x100000>;
+	};
+
+	tlmm: pinctrl@f000000 {
+		compatible = "qcom,waipio-pinctrl";
+		reg = <0x0F000000 0x1000000>;
+		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		wakeup-parent = <&pdc>;
+		qcom,gpios-reserved = <28 29 30 31 36 37 38 39>;
+	};
+
+	dload_mode {
+		compatible = "qcom,dload-mode";
+	};
+
+	microdump_modem {
+		compatible = "qcom,microdump_modem";
+	};
+
+	mini_dump_mode {
+		compatible = "qcom,minidump";
+		status = "ok";
+	};
+
+	va_mini_dump {
+		compatible = "qcom,va-minidump";
+		memory-region = <&va_md_mem>;
+		status = "ok";
+	};
+
+	qcom,mpm2-sleep-counter@c221000 {
+		compatible = "qcom,mpm2-sleep-counter";
+		reg = <0xc221000 0x1000>;
+		clock-frequency = <32768>;
+	};
+
+	adsp_pas: remoteproc-adsp@03000000 {
+		compatible = "qcom,waipio-adsp-pas";
+		reg = <0x03000000 0x10000>;
+		status = "ok";
+
+		cx-supply = <&VDD_LPI_CX_LEVEL>;
+		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+		mx-supply = <&VDD_LPI_MX_LEVEL>;
+		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+		reg-names = "cx", "mx";
+
+		clocks = <&clock_rpmh RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		qcom,qmp = <&aoss_qmp>;
+
+		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+		interconnect-names = "crypto_ddr";
+
+		memory-region = <&adsp_mem>;
+
+		/* Inputs from ssc */
+		interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					<&adsp_smp2p_in 0 0>,
+					<&adsp_smp2p_in 2 0>,
+					<&adsp_smp2p_in 1 0>,
+					<&adsp_smp2p_in 3 0>;
+
+		interrupt-names = "wdog",
+				"fatal",
+				"handover",
+				"ready",
+				"stop-ack";
+
+		/* Outputs to turing */
+		qcom,smem-states = <&adsp_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		glink_edge: glink-edge {
+			qcom,remote-pid = <2>;
+			transport = "smem";
+			mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
+				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+			mbox-names = "adsp_smem";
+			interrupt-parent = <&ipcc_mproc>;
+			interrupts = <IPCC_CLIENT_LPASS
+				      IPCC_MPROC_SIGNAL_GLINK_QMP
+				      IRQ_TYPE_EDGE_RISING>;
+
+			label = "adsp";
+			qcom,glink-label = "lpass";
+
+			qcom,adsp_qrtr {
+				qcom,glink-channels = "IPCRTR";
+				qcom,intents = <0x800  5
+						0x2000 3
+						0x4400 2>;
+			};
+
+			qcom,msm_fastrpc_rpmsg {
+				compatible = "qcom,msm-fastrpc-rpmsg";
+				qcom,glink-channels = "fastrpcglink-apps-dsp";
+				qcom,intents = <0x64 64>;
+			};
+
+			qcom,pmic_glink_rpmsg {
+				qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
+			};
+
+			qcom,pmic_glink_log_rpmsg {
+				qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
+				qcom,intents = <0x800 5
+						0xc00 3
+						0x2000 1>;
+			};
+
+		};
+	};
+
+	cdsp_pas: remoteproc-cdsp@32300000 {
+		compatible = "qcom,waipio-cdsp-pas";
+		reg = <0x32300000 0x10000>;
+		status = "ok";
+
+		cx-supply = <&VDD_CX_LEVEL>;
+		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		mx-supply = <&VDD_MXC_LEVEL>;
+		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		reg-names = "cx","mx";
+
+		memory-region = <&cdsp_mem>;
+
+		clocks = <&clock_rpmh RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		qcom,qmp = <&aoss_qmp>;
+
+		interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>,
+				<&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+		interconnect-names = "rproc_ddr", "crypto_ddr";
+
+		/* Inputs from turing */
+		interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+					<&cdsp_smp2p_in 0 0>,
+					<&cdsp_smp2p_in 2 0>,
+					<&cdsp_smp2p_in 1 0>,
+					<&cdsp_smp2p_in 3 0>;
+
+		interrupt-names = "wdog",
+				"fatal",
+				"handover",
+				"ready",
+				"stop-ack";
+
+		/* Outputs to turing */
+		qcom,smem-states = <&cdsp_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		glink-edge {
+			qcom,remote-pid = <5>;
+			transport = "smem";
+			mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
+				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+			mbox-names = "cdsp_smem";
+			interrupt-parent = <&ipcc_mproc>;
+			interrupts = <IPCC_CLIENT_CDSP
+				      IPCC_MPROC_SIGNAL_GLINK_QMP
+				      IRQ_TYPE_EDGE_RISING>;
+
+			label = "cdsp";
+			qcom,glink-label = "cdsp";
+
+			qcom,cdsp_qrtr {
+				qcom,glink-channels = "IPCRTR";
+				qcom,intents = <0x800  5
+						0x2000 3
+						0x4400 2>;
+			};
+
+			qcom,msm_fastrpc_rpmsg {
+				compatible = "qcom,msm-fastrpc-rpmsg";
+				qcom,glink-channels = "fastrpcglink-apps-dsp";
+				qcom,intents = <0x64 64>;
+			};
+
+			qcom,msm_cdsprm_rpmsg {
+				compatible = "qcom,msm-cdsprm-rpmsg";
+				qcom,glink-channels = "cdsprmglink-apps-dsp";
+				qcom,intents = <0x20 12>;
+
+				msm_cdsp_rm: qcom,msm_cdsp_rm {
+					compatible = "qcom,msm-cdsp-rm";
+					qcom,qos-latency-us = <70>;
+					qcom,qos-maxhold-ms = <20>;
+				};
+			};
+		};
+	};
+
+	slpi_pas: remoteproc-slpi@02400000 {
+		compatible = "qcom,waipio-slpi-pas";
+		reg = <0x02400000 0x10000>;
+		status = "ok";
+
+		cx-supply = <&VDD_LPI_CX_LEVEL>;
+		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+		mx-supply = <&VDD_LPI_MX_LEVEL>;
+		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+		reg-names = "cx", "mx";
+
+		clocks = <&clock_rpmh RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		qcom,qmp = <&aoss_qmp>;
+
+		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+		interconnect-names = "crypto_ddr";
+
+		memory-region = <&slpi_mem>;
+
+		/* Inputs from ssc */
+		interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
+					<&dsps_smp2p_in 0 0>,
+					<&dsps_smp2p_in 2 0>,
+					<&dsps_smp2p_in 1 0>,
+					<&dsps_smp2p_in 3 0>;
+
+		interrupt-names = "wdog",
+				"fatal",
+				"handover",
+				"ready",
+				"stop-ack";
+
+		/* Outputs to turing */
+		qcom,smem-states = <&dsps_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		glink-edge {
+			qcom,remote-pid = <3>;
+			transport = "smem";
+			mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI
+				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+			mbox-names = "dsps_smem";
+			interrupt-parent = <&ipcc_mproc>;
+			interrupts = <IPCC_CLIENT_SLPI
+				      IPCC_MPROC_SIGNAL_GLINK_QMP
+				      IRQ_TYPE_EDGE_RISING>;
+
+			label = "slpi";
+			qcom,glink-label = "dsps";
+
+			qcom,slpi_qrtr {
+				qcom,glink-channels = "IPCRTR";
+				qcom,net-id = <2>;
+				qcom,low-latency;
+				qcom,intents = <0x800  5
+						0x2000 3
+						0x4400 2>;
+			};
+
+			qcom,msm_fastrpc_rpmsg {
+				compatible = "qcom,msm-fastrpc-rpmsg";
+				qcom,glink-channels = "fastrpcglink-apps-dsp";
+				qcom,intents = <0x64 64>;
+			};
+		};
+	};
+
+	qcom,guestvm_loader@e0b00000 {
+		compatible = "qcom,guestvm-loader";
+		qcom,pas-id = <28>;
+		qcom,isolate-cpus;
+		qcom,vmid = <45>;
+		qcom,firmware-name = "trustedvm";
+		qcom,reserved-cpus = <0x5>, <0x6>;
+		qcom,unisolate-timeout-ms = <8000>;
+		memory-region = <&trust_ui_vm_mem>;
+	};
+
+	qcom,guestvm_loader@e0600000 {
+		compatible = "qcom,guestvm-loader";
+		qcom,pas-id = <35>;
+		qcom,vmid = <50>;
+		qcom,firmware-name = "cpusys_vm";
+		memory-region = <&cpusys_vm_mem>;
+	};
+
+	tlmm-vm-mem-access {
+		compatible = "qcom,tlmm-vm-mem-access";
+		qcom,master;
+		tlmm-vm-gpio-list = <365 366 367 368 301 305 387 388>;
+	};
+
+	ssc_sensors: qcom,msm-ssc-sensors {
+		compatible = "qcom,msm-ssc-sensors";
+		status = "ok";
+		qcom,firmware-name = "slpi";
+		qcom,rproc-handle = <&slpi_pas>;
+	};
+
+	modem_pas: remoteproc-mss@04080000 {
+		compatible = "qcom,waipio-modem-pas";
+		reg = <0x4080000 0x10000>;
+		status = "ok";
+
+		clocks = <&clock_rpmh RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		cx-supply = <&VDD_CX_LEVEL>;
+		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		mx-supply = <&VDD_MODEM_LEVEL>;
+		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		reg-names = "cx", "mx";
+
+		qcom,qmp = <&aoss_qmp>;
+
+		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+		interconnect-names = "crypto_ddr";
+
+		memory-region = <&mpss_mem>;
+
+		/* Inputs from mss */
+		interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+					<&modem_smp2p_in 0 0>,
+					<&modem_smp2p_in 2 0>,
+					<&modem_smp2p_in 1 0>,
+					<&modem_smp2p_in 3 0>,
+					<&modem_smp2p_in 7 0>;
+
+		interrupt-names = "wdog",
+				"fatal",
+				"handover",
+				"ready",
+				"stop-ack",
+				"shutdown-ack";
+
+		/* Outputs to mss */
+		qcom,smem-states = <&modem_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		glink-edge {
+			qcom,remote-pid = <1>;
+			transport = "smem";
+			mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS
+				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+			mbox-names = "mpss_smem";
+			interrupt-parent = <&ipcc_mproc>;
+			interrupts = <IPCC_CLIENT_MPSS
+				      IPCC_MPROC_SIGNAL_GLINK_QMP
+				      IRQ_TYPE_EDGE_RISING>;
+
+			label = "modem";
+			qcom,glink-label = "mpss";
+
+			qcom,modem_qrtr {
+				qcom,glink-channels = "IPCRTR";
+				qcom,low-latency;
+				qcom,intents = <0x800  5
+						0x2000 3
+						0x4400 2>;
+			};
+
+			qcom,modem_ds {
+				qcom,glink-channels = "DS";
+				qcom,intents = <0x4000 0x2>;
+			};
+		};
+	};
+
+	/* PIL spss node - for loading Secure Processor */
+	spss_pas: remoteproc-spss@1880000 {
+		compatible = "qcom,waipio-spss-pas";
+		ranges;
+		reg = <0x188101c 0x4>,
+		      <0x1881024 0x4>,
+		      <0x1881028 0x4>,
+		      <0x188103c 0x4>,
+		      <0x1881100 0x4>,
+		      <0x1882014 0x4>;
+		reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask",
+			    "rmb_err", "rmb_general_purpose", "rmb_err_spare2";
+		interrupts = <0 352 1>;
+
+		cx-supply = <&VDD_CX_LEVEL>;
+		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+
+		clocks = <&clock_rpmh RPMH_CXO_CLK>;
+		clock-names = "xo";
+		qcom,proxy-clock-names = "xo";
+		status = "ok";
+
+		memory-region = <&spss_region_mem>;
+		qcom,spss-scsr-bits = <24 25>;
+		qcom,extra-size = <4096>;
+
+		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+		interconnect-names = "crypto_ddr";
+
+		glink-edge {
+			qcom,remote-pid = <8>;
+			mboxes = <&ipcc_mproc IPCC_CLIENT_SPSS
+				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+			mbox-names = "spss_spss";
+			interrupt-parent = <&ipcc_mproc>;
+			interrupts = <IPCC_CLIENT_SPSS
+				      IPCC_MPROC_SIGNAL_GLINK_QMP
+				      IRQ_TYPE_EDGE_RISING>;
+
+			reg = <0x1885008 0x8>,
+			      <0x1885010 0x4>;
+			reg-names = "qcom,spss-addr",
+				    "qcom,spss-size";
+
+			label = "spss";
+			qcom,glink-label = "spss";
+		};
+	};
+
+	qcom,spcom {
+		compatible = "qcom,spcom";
+
+		qcom,rproc-handle = <&spss_pas>;
+		qcom,boot-enabled;
+		/* predefined channels, remote side is server */
+		qcom,spcom-ch-names = "sp_kernel", "sp_ssr";
+		/* sp2soc rmb shared register physical address and bmsk */
+		qcom,spcom-sp2soc-rmb-reg-addr = <0x01881020>;
+		qcom,spcom-sp2soc-rmb-initdone-bit = <24>;
+		qcom,spcom-sp2soc-rmb-pbldone-bit = <25>;
+		/* soc2sp rmb shared register physical address */
+		qcom,spcom-soc2sp-rmb-reg-addr = <0x01881030>;
+		qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0>;
+		status = "ok";
+	};
+
+	spss_utils: qcom,spss_utils {
+		compatible = "qcom,spss-utils";
+		/* spss fuses physical address */
+		qcom,rproc-handle = <&spss_pas>;
+		qcom,spss-fuse1-addr = <0x221C8214>;
+		qcom,spss-fuse1-bit = <8>;
+		qcom,spss-fuse2-addr = <0x221C8214>;
+		qcom,spss-fuse2-bit = <7>;
+		qcom,spss-dev-firmware-name  = "spss1d.mdt";  /* 8 chars max */
+		qcom,spss-test-firmware-name = "spss1t.mdt";  /* 8 chars max */
+		qcom,spss-prod-firmware-name = "spss1p.mdt";  /* 8 chars max */
+		qcom,spss-debug-reg-addr = <0x01886020>;
+		qcom,spss-emul-type-reg-addr = <0x01fc8004>;
+		pil-mem = <&spss_region_mem>;
+		qcom,pil-size = <0x0F0000>; // padding to 960KB
+		status = "ok";
+	};
+
+	qcom,pmic_glink {
+		compatible = "qcom,pmic-glink";
+		qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS";
+		qcom,subsys-name = "lpass";
+		qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd";
+		depends-on-supply = <&ipcc_mproc>;
+
+		battery_charger: qcom,battery_charger {
+			compatible = "qcom,battery-charger";
+		};
+
+		ucsi: qcom,ucsi {
+			compatible = "qcom,ucsi-glink";
+		};
+
+		altmode: qcom,altmode {
+			compatible = "qcom,altmode-glink";
+			#altmode-cells = <1>;
+		};
+	};
+
+	qcom,pmic_glink_log {
+		compatible = "qcom,pmic-glink";
+		qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";
+
+		qcom,battery_debug {
+			compatible = "qcom,battery-debug";
+		};
+
+		qcom,charger_ulog_glink {
+			compatible = "qcom,charger-ulog-glink";
+		};
+
+		qcom,spmi_glink_debug {
+			compatible = "qcom,spmi-glink-debug";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			depends-on-supply = <&spmi1_bus>;
+
+			/* Primary SPMI bus */
+			spmi@0 {
+				reg = <0>;
+				#address-cells = <2>;
+				#size-cells = <0>;
+
+				qcom,pm8350b-debug@3 {
+					compatible = "qcom,spmi-pmic";
+					reg = <3 SPMI_USID>;
+					qcom,can-sleep;
+				};
+			};
+
+			/* Secondary SPMI bus */
+			spmi@1 {
+				reg = <1>;
+				#address-cells = <2>;
+				#size-cells = <0>;
+
+				smb1394_glink_debug: qcom,smb1394-debug@9 {
+					compatible = "qcom,spmi-pmic";
+					reg = <9 SPMI_USID>;
+					qcom,can-sleep;
+				};
+
+				qcom,smb1394-debug@b {
+					compatible = "qcom,spmi-pmic";
+					reg = <11 SPMI_USID>; // 0xb
+					qcom,can-sleep;
+				};
+
+				qcom,smb1396-debug@d {
+					compatible = "qcom,spmi-pmic";
+					reg = <13 SPMI_USID>; // 0xd
+					qcom,can-sleep;
+				};
+			};
+		};
+	};
+
+	cache-controller@19200000 {
+		compatible = "qcom,waipio-llcc", "qcom,llcc-v21";
+		reg = <0x19200000 0x580000> , <0x19A00000 0x80000>;
+		reg-names = "llcc_base", "llcc_broadcast_base";
+		interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+		cap-based-alloc-and-pwr-collapse;
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "qdss_clk";
+	};
+
+	hyp_core_ctl: qcom,hyp-core-ctl {
+		compatible = "qcom,hyp-core-ctl";
+		status = "ok";
+	};
+
+	eud: qcom,msm-eud@88e0000 {
+		compatible = "qcom,msm-eud";
+		interrupt-names = "eud_irq";
+		interrupt-parent = <&pdc>;
+		interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x088E0000 0x2000>,
+			<0x088E2000 0x1000>;
+		reg-names = "eud_base", "eud_mode_mgr2";
+
+		clocks = <&clock_gcc GCC_EUSB3_0_CLKREF_EN>;
+		clock-names = "eud_clkref_clk";
+
+		qcom,secure-eud-en;
+		status = "ok";
+	};
+
+	qcom,memshare {
+		compatible = "qcom,memshare";
+
+		qcom,client_1 {
+			compatible = "qcom,memshare-peripheral";
+			qcom,peripheral-size = <0x0>;
+			qcom,client-id = <0>;
+			qcom,allocate-boot-time;
+			label = "modem";
+		};
+
+		qcom,client_2 {
+			compatible = "qcom,memshare-peripheral";
+			qcom,peripheral-size = <0x0>;
+			qcom,client-id = <2>;
+			label = "modem";
+		};
+
+		qcom,client_3 {
+			compatible = "qcom,memshare-peripheral";
+			qcom,peripheral-size = <0x500000>;
+			qcom,client-id = <1>;
+			qcom,allocate-on-request;
+			label = "modem";
+		};
+	};
+
+	clocks {
+		xo_board: xo_board {
+			compatible = "fixed-clock";
+			clock-frequency = <76800000>;
+			clock-output-names = "xo_board";
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			clock-output-names = "sleep_clk";
+			#clock-cells = <0>;
+		};
+	};
+
+	ipcc_mproc: qcom,ipcc@ed18000 {
+		compatible = "qcom,ipcc";
+		reg = <0xed18000 0x1000>;
+		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#mbox-cells = <2>;
+	};
+
+	tcsr: syscon@1fc0000 {
+		compatible = "syscon";
+		reg = <0x1fc0000 0x30000>;
+	};
+
+	aoss_qmp: power-controller@c300000 {
+		compatible = "qcom,waipio-aoss-qmp";
+		reg = <0xc300000 0x400>;
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_AOP
+			      IPCC_MPROC_SIGNAL_GLINK_QMP
+			      IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
+			  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+		#power-domain-cells = <1>;
+		#clock-cells = <0>;
+	};
+
+	qmp_aop: qcom,qmp-aop {
+		compatible = "qcom,qmp-mbox";
+		qcom,qmp = <&aoss_qmp>;
+		label = "aop";
+		#mbox-cells = <1>;
+	};
+
+	qmp_tme: qcom,qmp-tme {
+		compatible = "qcom,qmp-mbox";
+		qcom,remote-pid = <14>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_TME
+			  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+		mbox-names = "tme_qmp";
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_TME
+			      IPCC_MPROC_SIGNAL_GLINK_QMP
+			      IRQ_TYPE_EDGE_RISING>;
+
+		label = "tme";
+		qcom,early-boot;
+		priority = <0>;
+		mbox-desc-offset = <0x0>;
+		#mbox-cells = <1>;
+	};
+
+	qcom,tmecom-qmp-client {
+		compatible = "qcom,tmecom-qmp-client";
+		mboxes = <&qmp_tme 0>;
+		mbox-names = "tmecom";
+		label = "tmecom";
+		depends-on-supply = <&qmp_tme>;
+	};
+
+	qcom,glinkpkt {
+		compatible = "qcom,glinkpkt";
+
+		qcom,glinkpkt-at-mdm0 {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DS";
+			qcom,glinkpkt-dev-name = "at_mdm0";
+		};
+
+		qcom,glinkpkt-apr-apps2 {
+			qcom,glinkpkt-edge = "adsp";
+			qcom,glinkpkt-ch-name = "apr_apps2";
+			qcom,glinkpkt-dev-name = "apr_apps2";
+		};
+
+		qcom,glinkpkt-data40-cntl {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DATA40_CNTL";
+			qcom,glinkpkt-dev-name = "smdcntl8";
+		};
+
+		qcom,glinkpkt-data1 {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DATA1";
+			qcom,glinkpkt-dev-name = "smd7";
+		};
+
+		qcom,glinkpkt-data4 {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DATA4";
+			qcom,glinkpkt-dev-name = "smd8";
+		};
+
+		qcom,glinkpkt-data11 {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DATA11";
+			qcom,glinkpkt-dev-name = "smd11";
+		};
+	};
+
+	qcom,qsee_ipc_irq_bridge {
+		compatible = "qcom,qsee-ipc-irq-bridge";
+
+		qcom,qsee-ipc-irq-spss {
+			qcom,dev-name = "qsee_ipc_irq_spss";
+			interrupt-parent = <&ipcc_mproc>;
+			interrupts = <IPCC_CLIENT_SPSS
+				      IPCC_MPROC_SIGNAL_TZ
+				      IRQ_TYPE_EDGE_RISING>;
+			label = "spss";
+		};
+	};
+
+	qrtr-gunyah {
+		compatible = "qcom,qrtr-gunyah";
+		qcom,master;
+		gunyah-label = <3>;
+		peer-name = <2>;
+		shared-buffer = <&trust_ui_vm_qrtr>;
+	};
+
+	/* CAM_CC GDSCs */
+	cam_cc_bps_gdsc: qcom,gdsc@adf0004 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf0004 0x4>;
+		regulator-name = "cam_cc_bps_gdsc";
+		qcom,gds-timeout = <500>;
+		clock-names = "ahb_clk";
+		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
+		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+		qcom,support-hw-trigger;
+		qcom,retain-regs;
+	};
+
+	cam_cc_ife_0_gdsc: qcom,gdsc@adf1004 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf1004 0x4>;
+		regulator-name = "cam_cc_ife_0_gdsc";
+		qcom,gds-timeout = <500>;
+		clock-names = "ahb_clk";
+		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
+		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+		qcom,retain-regs;
+	};
+
+	cam_cc_ife_1_gdsc: qcom,gdsc@adf2004 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf2004 0x4>;
+		regulator-name = "cam_cc_ife_1_gdsc";
+		qcom,gds-timeout = <500>;
+		clock-names = "ahb_clk";
+		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
+		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+		qcom,retain-regs;
+	};
+
+	cam_cc_ife_2_gdsc: qcom,gdsc@adf2050 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf2050 0x4>;
+		regulator-name = "cam_cc_ife_2_gdsc";
+		qcom,gds-timeout = <500>;
+		clock-names = "ahb_clk";
+		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
+		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+		qcom,retain-regs;
+	};
+
+	cam_cc_ipe_0_gdsc: qcom,gdsc@adf0078 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf0078 0x4>;
+		regulator-name = "cam_cc_ipe_0_gdsc";
+		qcom,gds-timeout = <500>;
+		clock-names = "ahb_clk";
+		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
+		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+		qcom,support-hw-trigger;
+		qcom,retain-regs;
+	};
+
+	cam_cc_sbi_gdsc: qcom,gdsc@adf00d0 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf00d0 0x4>;
+		regulator-name = "cam_cc_sbi_gdsc";
+		qcom,gds-timeout = <500>;
+		clock-names = "ahb_clk";
+		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
+		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+		qcom,retain-regs;
+	};
+
+	cam_cc_sfe_0_gdsc: qcom,gdsc@adf3050 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf3050 0x4>;
+		regulator-name = "cam_cc_sfe_0_gdsc";
+		qcom,gds-timeout = <500>;
+		clock-names = "ahb_clk";
+		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
+		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+		qcom,retain-regs;
+	};
+
+	cam_cc_sfe_1_gdsc: qcom,gdsc@adf3098 {
+		compatible = "qcom,gdsc";
+		reg = <0xadf3098 0x4>;
+		regulator-name = "cam_cc_sfe_1_gdsc";
+		qcom,gds-timeout = <500>;
+		clock-names = "ahb_clk";
+		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
+		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+		qcom,retain-regs;
+	};
+
+	cam_cc_titan_top_gdsc: qcom,gdsc@adf31dc {
+		compatible = "qcom,gdsc";
+		reg = <0xadf31dc 0x4>;
+		regulator-name = "cam_cc_titan_top_gdsc";
+		qcom,gds-timeout = <500>;
+		clock-names = "ahb_clk";
+		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
+		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+		qcom,retain-regs;
+	};
+
+	/* DISP_CC GDSCs */
+	disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 {
+		compatible = "qcom,gdsc";
+		reg = <0xaf09000 0x4>;
+		regulator-name = "disp_cc_mdss_core_gdsc";
+		qcom,gds-timeout = <500>;
+		clock-names = "ahb_clk";
+		clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
+		parent-supply = <&VDD_MM_LEVEL>;
+		proxy-supply = <&disp_cc_mdss_core_gdsc>;
+		qcom,proxy-consumer-enable;
+		qcom,support-hw-trigger;
+		qcom,retain-regs;
+	};
+
+	disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 {
+		compatible = "qcom,gdsc";
+		reg = <0xaf0b000 0x4>;
+		regulator-name = "disp_cc_mdss_core_int2_gdsc";
+		qcom,gds-timeout = <500>;
+		clock-names = "ahb_clk";
+		clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
+		parent-supply = <&VDD_MM_LEVEL>;
+		qcom,support-hw-trigger;
+		qcom,retain-regs;
+	};
+
+	gcc_apcs_gdsc_vote_ctrl: syscon@162128 {
+		compatible = "syscon";
+		reg = <0x162128 0x4>;
+	};
+
+	/* GCC GDSCs */
+	gcc_pcie_0_gdsc: qcom,gdsc@17b004 {
+		compatible = "qcom,gdsc";
+		reg = <0x17b004 0x4>;
+		regulator-name = "gcc_pcie_0_gdsc";
+		qcom,gds-timeout = <500>;
+		parent-supply = <&VDD_CX_LEVEL>;
+		qcom,retain-regs;
+		qcom,no-status-check-on-disable;
+		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
+	};
+
+	gcc_pcie_1_gdsc: qcom,gdsc@19d004 {
+		compatible = "qcom,gdsc";
+		reg = <0x19d004 0x4>;
+		regulator-name = "gcc_pcie_1_gdsc";
+		qcom,gds-timeout = <500>;
+		parent-supply = <&VDD_CX_LEVEL>;
+		qcom,retain-regs;
+		qcom,no-status-check-on-disable;
+		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 1>;
+	};
+
+	gcc_ufs_phy_gdsc: qcom,gdsc@187004 {
+		compatible = "qcom,gdsc";
+		reg = <0x187004 0x4>;
+		regulator-name = "gcc_ufs_phy_gdsc";
+		qcom,gds-timeout = <500>;
+		parent-supply = <&VDD_CX_LEVEL>;
+		proxy-supply = <&gcc_ufs_phy_gdsc>;
+		qcom,proxy-consumer-enable;
+		qcom,retain-regs;
+	};
+
+	gcc_usb30_prim_gdsc: qcom,gdsc@149004 {
+		compatible = "qcom,gdsc";
+		reg = <0x149004 0x4>;
+		regulator-name = "gcc_usb30_prim_gdsc";
+		qcom,gds-timeout = <500>;
+		proxy-supply = <&gcc_usb30_prim_gdsc>;
+		qcom,proxy-consumer-enable;
+		qcom,retain-regs;
+	};
+
+	/* GPU_CC GDSCs */
+	gpu_cc_cx_hw_ctrl: syscon@3d9953c {
+		compatible = "syscon";
+		reg = <0x3d9953c 0x4>;
+	};
+
+	gpu_cc_cx_gdsc: qcom,gdsc@3d99108 {
+		compatible = "qcom,gdsc";
+		reg = <0x3d99108 0x4>;
+		regulator-name = "gpu_cc_cx_gdsc";
+		hw-ctrl-addr = <&gpu_cc_cx_hw_ctrl>;
+		parent-supply = <&VDD_CX_LEVEL>;
+		qcom,no-status-check-on-disable;
+		qcom,clk-dis-wait-val = <8>;
+		qcom,gds-timeout = <500>;
+		qcom,retain-regs;
+	};
+
+	gpu_cc_gx_domain_addr: syscon@3d99504 {
+		compatible = "syscon";
+		reg = <0x3d99504 0x4>;
+	};
+
+	gpu_cc_gx_sw_reset: syscon@3d99058 {
+		compatible = "syscon";
+		reg = <0x3d99058 0x4>;
+	};
+
+	gpu_cc_gx_acd_reset: syscon@3d99358 {
+		compatible = "syscon";
+		reg = <0x3d99358 0x4>;
+	};
+
+	gpu_cc_gx_acd_iroot_reset: syscon@3d9958c {
+		compatible = "syscon";
+		reg = <0x3d9958c 0x4>;
+	};
+
+	gpu_cc_gx_gdsc: qcom,gdsc@3d9905c {
+		compatible = "qcom,gdsc";
+		reg = <0x3d9905c 0x4>;
+		regulator-name = "gpu_cc_gx_gdsc";
+		domain-addr = <&gpu_cc_gx_domain_addr>;
+		sw-reset = <&gpu_cc_gx_sw_reset>,
+			   <&gpu_cc_gx_acd_reset>,
+			   <&gpu_cc_gx_acd_iroot_reset>;
+		parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
+		qcom,reset-aon-logic;
+		qcom,retain-regs;
+		qcom,gds-timeout = <500>;
+	};
+
+	/* VIDEO_CC GDSCs */
+	video_cc_mvs0_gdsc: qcom,gdsc@aaf809c {
+		compatible = "qcom,gdsc";
+		reg = <0xaaf809C 0x4>;
+		regulator-name = "video_cc_mvs0_gdsc";
+		qcom,gds-timeout = <500>;
+		clock-names = "ahb_clk";
+		clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
+		parent-supply = <&video_cc_mvs0c_gdsc>;
+		qcom,support-hw-trigger;
+		qcom,retain-regs;
+	};
+
+	video_cc_mvs0c_gdsc: qcom,gdsc@aaf804c {
+		compatible = "qcom,gdsc";
+		reg = <0xaaf804c 0x4>;
+		regulator-name = "video_cc_mvs0c_gdsc";
+		qcom,gds-timeout = <500>;
+		clock-names = "ahb_clk";
+		clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
+		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+		qcom,retain-regs;
+	};
+
+	video_cc_mvs1_gdsc: qcom,gdsc@aaf80c0 {
+		compatible = "qcom,gdsc";
+		reg = <0xaaf80c0 0x4>;
+		regulator-name = "video_cc_mvs1_gdsc";
+		qcom,gds-timeout = <500>;
+		clock-names = "ahb_clk";
+		clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
+		parent-supply = <&video_cc_mvs1c_gdsc>;
+		qcom,support-hw-trigger;
+		qcom,retain-regs;
+	};
+
+	video_cc_mvs1c_gdsc: qcom,gdsc@aaf8074 {
+		compatible = "qcom,gdsc";
+		reg = <0xaaf8074 0x4>;
+		regulator-name = "video_cc_mvs1c_gdsc";
+		qcom,gds-timeout = <500>;
+		clock-names = "ahb_clk";
+		clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
+		parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
+		qcom,retain-regs;
+	};
+
+	clock_gcc: qcom,gcc@100000 {
+		compatible = "qcom,waipio-gcc", "syscon";
+		reg = <0x100000 0x1f4200>;
+		reg-names = "cc_base";
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		vdd_mxa-supply = <&VDD_MXA_LEVEL>;
+		clocks = <&clock_rpmh RPMH_CXO_CLK>,
+			 <&sleep_clk>;
+		clock-names = "bi_tcxo",
+			      "sleep_clk";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	clock_videocc: qcom,videocc@aaf0000 {
+		compatible = "qcom,waipio-videocc", "syscon";
+		reg = <0xaaf0000 0x10000>;
+		reg-name = "cc_base";
+		vdd_mm-supply = <&VDD_MM_LEVEL>;
+		vdd_mxc-supply = <&VDD_MXC_LEVEL>;
+		clocks = <&clock_rpmh RPMH_CXO_CLK>,
+			 <&sleep_clk>,
+			 <&clock_gcc GCC_VIDEO_AHB_CLK>;
+		clock-names = "bi_tcxo",
+			      "sleep_clk",
+			      "iface";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	clock_camcc: qcom,camcc@ade0000 {
+		compatible = "qcom,waipio-camcc", "syscon";
+		reg = <0xade0000 0x20000>;
+		reg-names = "cc_base";
+		vdd_mm-supply = <&VDD_MM_LEVEL>;
+		vdd_mxa-supply = <&VDD_MXA_LEVEL>;
+		vdd_mxc-supply = <&VDD_MXC_LEVEL>;
+		clocks = <&clock_rpmh RPMH_CXO_CLK>,
+			 <&sleep_clk>,
+			 <&clock_gcc GCC_CAMERA_AHB_CLK>;
+		clock-names = "bi_tcxo",
+			      "sleep_clk",
+			      "iface";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	clock_dispcc: qcom,dispcc@af00000 {
+		compatible = "qcom,waipio-dispcc", "syscon";
+		reg = <0xaf00000 0x20000>;
+		reg-name = "cc_base";
+		vdd_mm-supply = <&VDD_MM_LEVEL>;
+		vdd_mxa-supply = <&VDD_MXA_LEVEL>;
+		clocks = <&clock_rpmh RPMH_CXO_CLK>,
+			 <&sleep_clk>,
+			 <&clock_gcc GCC_VIDEO_AHB_CLK>;
+		clock-names = "bi_tcxo",
+			      "sleep_clk",
+			      "iface";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	clock_gpucc: qcom,gpucc@3d90000 {
+		compatible = "qcom,waipio-gpucc", "syscon";
+		clock-output-names = "gpucc_clocks";
+		reg = <0x3d90000 0xA000>;
+		reg-names = "cc_base";
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		vdd_mx-supply = <&VDD_MXA_LEVEL>;
+		vdd_mxc-supply = <&VDD_MXC_LEVEL>;
+		clocks = <&clock_rpmh RPMH_CXO_CLK>,
+			 <&clock_gcc GCC_GPU_GPLL0_CLK_SRC>,
+			 <&clock_gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+		clock-names = "bi_tcxo",
+			      "gpll0_out_main",
+			      "gpll0_out_main_div";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	clock_apsscc: syscon@17A80000 {
+		compatible = "syscon";
+		reg = <0x17A80000 0x21000>;
+	};
+
+	clock_mccc: syscon@190ba000 {
+		compatible = "syscon";
+		reg = <0x190ba000 0x54>;
+	};
+
+	clock_debugcc: qcom,cc-debug {
+		compatible = "qcom,waipio-debugcc";
+		qcom,gcc = <&clock_gcc>;
+		qcom,videocc = <&clock_videocc>;
+		qcom,dispcc = <&clock_dispcc>;
+		qcom,camcc = <&clock_camcc>;
+		qcom,gpucc = <&clock_gpucc>;
+		qcom,apsscc = <&clock_apsscc>;
+		qcom,mccc = <&clock_mccc>;
+		clock-names = "xo_clk_src";
+		clocks = <&clock_rpmh RPMH_CXO_CLK>;
+		#clock-cells = <1>;
+	};
+
+	cpufreq_hw: qcom,cpufreq-hw {
+		compatible = "qcom,cpufreq-hw-epss";
+		reg = <0x17D91000 0x1000>,
+		      <0x17D92000 0x1000>,
+		      <0x17D93000 0x1000>;
+		reg-names = "freq-domain0",
+			    "freq-domain1",
+			    "freq-domain2";
+		clocks = <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_GPLL0>;
+		clock-names = "xo", "alternate";
+		qcom,lut-row-size = <4>;
+		qcom,skip-enable-check;
+		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "dcvsh0_int",
+				  "dcvsh1_int",
+				  "dcvsh2_int";
+		#freq-domain-cells = <2>;
+	};
+
+	qcom,cpufreq-hw-debug {
+		compatible = "qcom,cpufreq-hw-epss-debug";
+		qcom,freq-hw-domain = <&cpufreq_hw 0>,
+				      <&cpufreq_hw 1>,
+				      <&cpufreq_hw 2>;
+	};
+
+	clk_virt: interconnect@0 {
+		compatible = "qcom,waipio-clk_virt";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	mc_virt: interconnect@1 {
+		compatible = "qcom,waipio-mc_virt";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos", "disp";
+		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
+	};
+
+	config_noc: interconnect@1500000 {
+		reg = <0x1500000 0x1C000>;
+		compatible = "qcom,waipio-config_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	system_noc: interconnect@1680000 {
+		reg = <0x1680000 0x1E200>;
+		compatible = "qcom,waipio-system_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	pcie_noc: interconnect@16c0000 {
+		reg = <0x16C0000 0xE280>;
+		compatible = "qcom,waipio-pcie_anoc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	aggre1_noc: interconnect@16e0000 {
+		reg = <0x16e0000 0x1C080>;
+		compatible = "qcom,waipio-aggre1_noc";
+		#interconnect-cells = <1>;
+		clocks =
+			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+			<&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	aggre2_noc: interconnect@1700000 {
+		reg = <0x1700000 0x31080>;
+		compatible = "qcom,waipio-aggre2_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+		clocks =
+			<&clock_gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
+			<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
+			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+			<&clock_rpmh RPMH_IPA_CLK>;
+	};
+
+	mmss_noc: interconnect@1740000 {
+		reg = <0x1740000 0x1f080>;
+		compatible = "qcom,waipio-mmss_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos", "disp";
+		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
+	};
+
+	gem_noc: interconnect@19100000 {
+		reg = <0x19100000 0xBB800>;
+		compatible = "qcom,waipio-gem_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos", "disp";
+		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
+	};
+
+	nsp_noc: interconnect@320C0000 {
+		reg = <0x320C0000 0x10000>;
+		compatible = "qcom,waipio-nsp_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	lpass_ag_noc: interconnect@3c40000 {
+		reg = <0x3c40000 0x17200>;
+		compatible = "qcom,waipio-lpass_ag_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	thermal_zones: thermal-zones {
+	};
+
+	tcsr_mutex_block: syscon@1f40000 {
+		compatible = "syscon";
+		reg = <0x1f40000 0x20000>;
+	};
+
+	tcsr_mutex: hwlock {
+		compatible = "qcom,tcsr-mutex";
+		syscon = <&tcsr_mutex_block 0 0x1000>;
+		#hwlock-cells = <1>;
+	};
+
+	qcom_tzlog: tz-log@146AA720 {
+		compatible = "qcom,tz-log";
+		reg = <0x146AA720 0x3000>;
+		qcom,hyplog-enabled;
+		hyplog-address-offset = <0x410>;
+		hyplog-size-offset = <0x414>;
+	};
+
+	qcom_qseecom: qseecom@c1700000 {
+		compatible = "qcom,qseecom";
+		memory-region = <&qseecom_mem>;
+		qseecom_mem = <&qseecom_mem>;
+		qseecom_ta_mem = <&qseecom_ta_mem>;
+		user_contig_mem = <&user_contig_mem>;
+		qcom,hlos-num-ce-hw-instances = <1>;
+		qcom,hlos-ce-hw-instance = <0>;
+		qcom,qsee-ce-hw-instance = <0>;
+		qcom,disk-encrypt-pipe-pair = <2>;
+		qcom,no-clock-support;
+		qcom,appsbl-qseecom-support;
+		qcom,commonlib64-loaded-by-uefi;
+		qcom,qsee-reentrancy-support = <2>;
+	};
+
+	qcom_cedev: qcedev@1de0000 {
+		compatible = "qcom,qcedev";
+		reg = <0x1de0000 0x20000>,
+			<0x1dc4000 0x24000>;
+		reg-names = "crypto-base","crypto-bam-base";
+		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,bam-pipe-pair = <2>;
+		qcom,ce-hw-instance = <0>;
+		qcom,ce-device = <0>;
+		qcom,ce-hw-shared;
+		qcom,bam-ee = <0>;
+		qcom,smmu-s1-enable;
+		qcom,no-clock-support;
+		interconnect-names = "data_path";
+		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+		iommus = <&apps_smmu 0x0584 0x0011>;
+		qcom,iommu-dma = "atomic";
+		dma-coherent;
+
+		qcom_cedev_ns_cb {
+			compatible = "qcom,qcedev,context-bank";
+			label = "ns_context";
+			iommus = <&apps_smmu 0x588 0x0>,
+				<&apps_smmu 0x59A 0x0>,
+				<&apps_smmu 0x59F 0x0>,
+				<&apps_smmu 0x598 0x5>;
+			dma-coherent;
+		};
+
+		qcom_cedev_s_cb {
+			compatible = "qcom,qcedev,context-bank";
+			label = "secure_context";
+			iommus = <&apps_smmu 0x592 0x0>,
+				 <&apps_smmu 0x597 0x0>,
+				 <&apps_smmu 0x59B 0x0>,
+				 <&apps_smmu 0x59E 0x0>;
+			qcom,iommu-vmid = <0x9>;
+			qcom,secure-context-bank;
+		};
+	};
+
+	qcom_rng: qrng@10c3000 {
+		compatible = "qcom,msm-rng";
+		reg = <0x10c3000 0x1000>;
+		qcom,no-qrng-config;
+		qcom,no-clock-support;
+	};
+
+	smem: qcom,smem {
+		compatible = "qcom,smem";
+		memory-region = <&smem_mem>;
+		hwlocks = <&tcsr_mutex 3>;
+	};
+
+	qcom,rmtfs_sharedmem@0 {
+		compatible = "qcom,sharedmem-uio";
+		reg = <0x0 0x280000>;
+		reg-names = "rmtfs";
+		qcom,client-id = <0x00000001>;
+	};
+
+	ufsphy_mem: ufsphy_mem@1d87000 {
+		reg = <0x1d87000 0xe10>;
+		reg-names = "phy_mem";
+		#phy-cells = <0>;
+
+		lanes-per-direction = <2>;
+		clock-names = "ref_clk_src",
+			"ref_aux_clk", "qref_clk",
+			"rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
+			"rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
+		clocks = <&clock_rpmh RPMH_CXO_CLK>,
+			<&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+			<&clock_gcc GCC_UFS_0_CLKREF_EN>,
+			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>,
+			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>,
+			<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>,
+			<&clock_gcc UFS_PHY_RX_SYMBOL_0_CLK>,
+			<&clock_gcc UFS_PHY_RX_SYMBOL_1_CLK>,
+			<&clock_gcc UFS_PHY_TX_SYMBOL_0_CLK>;
+		resets = <&ufshc_mem 0>;
+		status = "disabled";
+	};
+
+	ufshc_mem: ufshc@1d84000 {
+		compatible = "qcom,ufshc";
+		reg = <0x1d84000 0x3000>,
+		      <0x1d88000 0x8000>,
+		      <0x1d90000 0x9000>;
+		reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm";
+		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+		phys = <&ufsphy_mem>;
+		phy-names = "ufsphy";
+		#reset-cells = <1>;
+
+		lanes-per-direction = <2>;
+		dev-ref-clk-freq = <0>; /* 19.2 MHz */
+		clock-names =
+			"core_clk",
+			"bus_aggr_clk",
+			"iface_clk",
+			"core_clk_unipro",
+			"core_clk_ice",
+			"ref_clk",
+			"tx_lane0_sync_clk",
+			"rx_lane0_sync_clk",
+			"rx_lane1_sync_clk";
+		clocks =
+			<&clock_gcc GCC_UFS_PHY_AXI_CLK>,
+			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+			<&clock_gcc GCC_UFS_PHY_AHB_CLK>,
+			<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+			<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+			<&clock_rpmh RPMH_CXO_CLK>,
+			<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+		freq-table-hz =
+			<75000000 300000000>,
+			<0 0>,
+			<0 0>,
+			<75000000 300000000>,
+			<75000000 300000000>,
+			<0 0>,
+			<0 0>,
+			<0 0>,
+			<0 0>;
+
+		interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
+		      <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
+		interconnect-names = "ufs-ddr", "cpu-ufs";
+
+		qcom,ufs-bus-bw,name = "ufshc_mem";
+		qcom,ufs-bus-bw,num-cases = <26>;
+		qcom,ufs-bus-bw,num-paths = <2>;
+		qcom,ufs-bus-bw,vectors-KBps =
+		/*
+		 * During HS G3 UFS runs at nominal voltage corner, vote
+		 * higher bandwidth to push other buses in the data path
+		 * to run at nominal to achieve max throughput.
+		 * 4GBps pushes BIMC to run at nominal.
+		 * 200MBps pushes CNOC to run at nominal.
+		 * Vote for half of this bandwidth for HS G3 1-lane.
+		 * For max bandwidth, vote high enough to push the buses
+		 * to run in turbo voltage corner.
+		 */
+		<0 0>, <0 0>,          /* No vote */
+		<922 0>, <1000 0>,     /* PWM G1 */
+		<1844 0>, <1000 0>,    /* PWM G2 */
+		<3688 0>, <1000 0>,    /* PWM G3 */
+		<7376 0>, <1000 0>,    /* PWM G4 */
+		<1844 0>, <1000 0>,    /* PWM G1 L2 */
+		<3688 0>, <1000 0>,    /* PWM G2 L2 */
+		<7376 0>, <1000 0>,    /* PWM G3 L2 */
+		<14752 0>, <1000 0>,   /* PWM G4 L2 */
+		<127796 0>, <1000 0>,  /* HS G1 RA */
+		<255591 0>, <1000 0>,  /* HS G2 RA */
+		<1492582 0>, <102400 0>,  /* HS G3 RA */
+		<2915200 0>, <204800 0>,  /* HS G4 RA */
+		<255591 0>, <1000 0>,  /* HS G1 RA L2 */
+		<511181 0>, <1000 0>,  /* HS G2 RA L2 */
+		<1492582 0>, <204800 0>, /* HS G3 RA L2 */
+		<2915200 0>, <409600 0>, /* HS G4 RA L2 */
+		<149422 0>, <1000 0>,  /* HS G1 RB */
+		<298189 0>, <1000 0>,  /* HS G2 RB */
+		<1492582 0>, <102400 0>,  /* HS G3 RB */
+		<2915200 0>, <204800 0>,  /* HS G4 RB */
+		<298189 0>, <1000 0>,  /* HS G1 RB L2 */
+		<596378 0>, <1000 0>,  /* HS G2 RB L2 */
+		/* As UFS working in HS G3 RB L2 mode, aggregated
+		 * bandwidth (AB) should take care of providing
+		 * optimum throughput requested. However, as tested,
+		 * in order to scale up CNOC clock, instantaneous
+		 * bindwidth (IB) needs to be given a proper value too.
+		 */
+		<1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */
+		<2915200 0>, <409600 409600>, /* HS G4 RB L2 */
+		<7643136 0>, <307200 0>; /* Max. bandwidth */
+
+		qcom,bus-vector-names = "MIN",
+		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
+		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
+		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
+		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
+		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
+		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
+		"MAX";
+
+		reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+		resets = <&clock_gcc GCC_UFS_PHY_BCR>;
+		reset-names = "rst";
+
+		iommus = <&apps_smmu 0xE0 0x0>;
+		qcom,iommu-dma = "fastmap";
+		dma-coherent;
+
+		status = "disabled";
+		qos0 {
+			mask = <0xf0>;
+			vote = <44>;
+		};
+
+		qos1 {
+			mask = <0x0f>;
+			vote = <44>;
+		};
+	};
+
+	sdhc2_opp_table: sdhc2-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-peak-kBps = <160000 100000>;
+			opp-avg-kBps = <80000 50000>;
+		};
+
+		opp-202000000 {
+			opp-hz = /bits/ 64 <202000000>;
+			opp-peak-kBps = <200000 120000>;
+			opp-avg-kBps = <80000 50000>;
+		};
+	};
+
+	sdhc_2: sdhci@8804000 {
+		status = "disabled";
+
+		compatible = "qcom,sdhci-msm-v5";
+		reg = <0x08804000 0x1000>;
+		reg-names = "hc_mem";
+
+		interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hc_irq", "pwr_irq";
+
+		bus-width = <4>;
+		no-sdio;
+		no-mmc;
+		qcom,restore-after-cx-collapse;
+
+		clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,
+			<&clock_gcc GCC_SDCC2_APPS_CLK>;
+		clock-names = "iface", "core";
+
+		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+		qcom,dll-hsr-list = <0x0007642C 0xA800 0x10
+					0x2C010800 0x80040868>;
+
+		iommus = <&apps_smmu 0x4a0 0x0>;
+		dma-coherent;
+		qcom,iommu-dma = "fastmap";
+
+		interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
+			      <&gem_noc MASTER_APPSS_PROC &config_noc
+			      SLAVE_SDCC_2>;
+		interconnect-names = "sdhc-ddr","cpu-sdhc";
+		operating-points-v2 = <&sdhc2_opp_table>;
+
+		qos0 {
+			mask = <0xf0>;
+			vote = <44>;
+		};
+
+		qos1 {
+			mask = <0x0f>;
+			vote = <44>;
+		};
+	};
+
+	kryo-erp {
+		compatible = "arm,arm64-kryo-cpu-erp";
+		interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "l1-l2-faultirq","l3-scu-faultirq";
+	};
+
+	qcom,smp2p_sleepstate {
+		compatible = "qcom,smp2p-sleepstate";
+		qcom,smem-states = <&sleepstate_smp2p_out 0>;
+		interrupt-parent = <&sleepstate_smp2p_in>;
+		interrupts = <0 0>;
+		interrupt-names = "smp2p-sleepstate-in";
+	};
+
+	pdc: interrupt-controller@b220000 {
+		compatible = "qcom,pdc";
+		reg = <0xb220000 0x30000>, <0x174000f0 0x64>;
+		reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg";
+		qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
+				  <94 609 31>, <125 63 1>, <126 716 12>;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&intc>;
+		interrupt-controller;
+	};
+
+	cluster-device {
+		compatible = "qcom,lpm-cluster-dev";
+		power-domains = <&CLUSTER_PD>;
+	};
+
+	qcom,chd {
+		compatible = "qcom,core-hang-detect";
+		label = "core";
+		qcom,threshold-arr = <0x17800058 0x17810058 0x17820058 0x17830058
+			0x17840058 0x17850058 0x17860058 0x17870058>;
+		qcom,config-arr = <0x17800060 0x17810060 0x17820060 0x17830060
+			0x17840060 0x17850060 0x17860060 0x17870060>;
+	};
+
+	apps_rsc: rsc@17a00000 {
+		label = "apps_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0x17a00000 0x10000>,
+		      <0x17a10000 0x10000>,
+		      <0x17a20000 0x10000>,
+		      <0x17a30000 0x10000>;
+		reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			     /* No interrupt into GIC for DRV3 */
+		qcom,tcs-offset = <0xd00>;
+		qcom,drv-id = <2>;
+		qcom,tcs-config = <ACTIVE_TCS    3>,
+				  <SLEEP_TCS     2>,
+				  <WAKE_TCS      2>,
+				  <CONTROL_TCS   0>, /* PDC wakeup values will be written from TZ */
+				  <FAST_PATH_TCS 1>;
+		power-domains = <&CLUSTER_PD>;
+
+		apps_bcm_voter: bcm_voter {
+			compatible = "qcom,bcm-voter";
+		};
+
+		clock_rpmh: qcom,rpmhclk {
+			compatible = "qcom,waipio-rpmh-clk";
+			#clock-cells = <1>;
+		};
+
+		dcvs_fp: qcom,dcvs-fp {
+			compatible = "qcom,dcvs-fp";
+			qcom,ddr-bcm-name = "MC3";
+			qcom,llcc-bcm-name = "SH5";
+		};
+	};
+
+	disp_rsc: rsc@af20000 {
+		label = "disp_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0xaf20000 0x10000>;
+		reg-names = "drv-0";
+		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
+		qcom,tcs-offset = <0x1c00>;
+		qcom,drv-id = <0>;
+		qcom,tcs-config = <ACTIVE_TCS    0>,
+				  <SLEEP_TCS     1>,
+				  <WAKE_TCS      1>,
+				  <CONTROL_TCS   0>,
+				  <FAST_PATH_TCS 0>;
+
+		disp_bcm_voter: bcm_voter {
+			compatible = "qcom,bcm-voter";
+			qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
+		};
+	};
+
+	cpuss-sleep-stats@17800054 {
+	      compatible = "qcom,cpuss-sleep-stats";
+	      reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>,
+		    <0x17830054 0x4>, <0x17840054 0x4>, <0x17850054 0x4>,
+		    <0x17860054 0x4>, <0x17870054 0x4>, <0x178A0098 0x4>,
+		    <0x178C0000 0x10000>;
+	      reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
+			  "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
+			  "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5",
+			  "seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7",
+			  "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
+	      num-cpus = <8>;
+	};
+
+	sys-pm-vx@c320000 {
+		compatible = "qcom,sys-pm-violators", "qcom,sys-pm-waipio";
+		reg = <0xc320000 0x0400>;
+		mboxes = <&qmp_aop 0>;
+		mbox-names = "aop";
+	};
+
+	soc-sleep-stats@c3f0000 {
+		compatible = "qcom,rpmh-sleep-stats";
+		reg = <0xc3f0000 0x400>;
+		ss-name = "modem", "adsp", "adsp_island",
+			  "cdsp", "slpi", "slpi_island",
+			  "apss";
+	};
+
+	subsystem-sleep-stats {
+		compatible = "qcom,subsystem-sleep-stats";
+	};
+
+	qcom,msm-cdsp-loader {
+		compatible = "qcom,cdsp-loader";
+		qcom,proc-img-to-load = "cdsp";
+		qcom,rproc-handle = <&cdsp_pas>;
+	};
+
+	qcom,msm-adsprpc-mem {
+		compatible = "qcom,msm-adsprpc-mem-region";
+		memory-region = <&adsp_mem_heap>;
+		restrict-access;
+	};
+
+	msm_fastrpc: qcom,msm_fastrpc {
+		compatible = "qcom,msm-fastrpc-compute";
+		qcom,adsp-remoteheap-vmid = <22 37>;
+		qcom,fastrpc-adsp-audio-pdr;
+		qcom,fastrpc-adsp-sensors-pdr;
+		qcom,rpc-latency-us = <235>;
+		qcom,fastrpc-gids = <2908>;
+		qcom,qos-cores = <0 1 2 3>;
+
+		qcom,msm_fastrpc_compute_cb1 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x2161 0x0400>,
+					 <&apps_smmu 0x1021 0x1420>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb2 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x2162 0x0400>,
+					 <&apps_smmu 0x1022 0x1420>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb3 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x2163 0x0400>,
+					 <&apps_smmu 0x1023 0x1420>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb4 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x2164 0x0400>,
+					 <&apps_smmu 0x1024 0x1420>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb5 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x2165 0x0400>,
+					 <&apps_smmu 0x1025 0x1420>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb6 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x2166 0x0400>,
+					 <&apps_smmu 0x1026 0x1420>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb7 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x2167 0x0400>,
+					 <&apps_smmu 0x1027 0x1420>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb8 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x2168 0x0400>,
+					 <&apps_smmu 0x1028 0x1420>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb9 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			qcom,secure-context-bank;
+			iommus = <&apps_smmu 0x2169 0x0400>,
+					 <&apps_smmu 0x1029 0x1420>;
+			qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			qcom,iommu-vmid = <0xA>;	/* VMID_CP_PIXEL */
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb10 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x1803 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb11 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x1804 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb12 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x1805 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb13 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "sdsprpc-smd";
+			iommus = <&apps_smmu 0x0541 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb14 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "sdsprpc-smd";
+			iommus = <&apps_smmu 0x0542 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb15 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "sdsprpc-smd";
+			iommus = <&apps_smmu 0x0543 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			shared-cb = <4>;
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb16 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x102B 0x1420>,
+					 <&apps_smmu 0x216B 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb17 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x102C 0x1420>,
+					 <&apps_smmu 0x216C 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb18 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x102D 0x1420>,
+					 <&apps_smmu 0x216D 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb19 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x102E 0x1420>,
+					 <&apps_smmu 0x216E 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+	};
+
+	spmi_bus: spmi0_bus: qcom,spmi@c42d000 {
+		compatible = "qcom,spmi-pmic-arb";
+		reg = <0xc42d000 0x4000>,
+		      <0xc400000 0x3000>,
+		      <0xc500000 0x400000>,
+		      <0xc440000 0x80000>,
+		      <0xc4c0000 0x10000>;
+		reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
+		interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "periph_irq";
+		interrupt-controller;
+		#interrupt-cells = <4>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		cell-index = <0>;
+		qcom,channel = <0>;
+		qcom,ee = <0>;
+		qcom,bus-id = <0>;
+	};
+
+	spmi1_bus: qcom,spmi@c432000 {
+		compatible = "qcom,spmi-pmic-arb";
+		reg = <0xc432000 0x4000>,
+		      <0xc400000 0x3000>,
+		      <0xc500000 0x400000>,
+		      <0xc440000 0x80000>,
+		      <0xc4d0000 0x10000>;
+		reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
+		interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "periph_irq";
+		interrupt-controller;
+		#interrupt-cells = <4>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		cell-index = <0>;
+		qcom,channel = <0>;
+		qcom,ee = <0>;
+		qcom,bus-id = <1>;
+		depends-on-supply = <&spmi0_bus>;
+	};
+
+	spmi0_debug_bus: qcom,spmi-debug@10b14000 {
+		compatible = "qcom,spmi-pmic-arb-debug";
+		reg = <0x10b14000 0x60>, <0x221c8784 0x4>;
+		reg-names = "core", "fuse";
+		clocks = <&aoss_qmp>;
+		clock-names = "core_clk";
+		qcom,fuse-enable-bit = <18>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		depends-on-supply = <&spmi1_bus>;
+		depends-on2-supply = <&smb1394_glink_debug>;
+
+		qcom,pmk8350-debug@0 {
+			compatible = "qcom,spmi-pmic";
+			reg = <0 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+
+		qcom,pm8350-debug@1 {
+			compatible = "qcom,spmi-pmic";
+			reg = <1 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+
+		qcom,pm8350c-debug@2 {
+			compatible = "qcom,spmi-pmic";
+			reg = <2 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+
+		qcom,pm8350b-debug@3 {
+			compatible = "qcom,spmi-pmic";
+			reg = <3 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+
+		qcom,pmr735a-debug@4 {
+			compatible = "qcom,spmi-pmic";
+			reg = <4 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+
+		qcom,pmr735b-debug@5 {
+			compatible = "qcom,spmi-pmic";
+			reg = <5 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+
+		qcom,pm8450-debug@7 {
+			compatible = "qcom,spmi-pmic";
+			reg = <7 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+
+		qcom,pm8010-debug@8 {
+			compatible = "qcom,spmi-pmic";
+			reg = <8 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+
+		qcom,pm8010-debug@9 {
+			compatible = "qcom,spmi-pmic";
+			reg = <9 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+	};
+
+	qcom,secure-buffer {
+		compatible = "qcom,secure-buffer";
+		qcom,vmid-cp-camera-preview-ro;
+	};
+
+	qcom,mem-buf {
+		compatible = "qcom,mem-buf";
+		qcom,mem-buf-capabilities = "supplier";
+		qcom,vmid = <3>;
+	};
+
+	qcom,mem-buf-msgq {
+		compatible = "qcom,mem-buf-msgq";
+	};
+
+	qcom,sps {
+		compatible = "qcom,msm-sps-4k";
+		qcom,pipe-attr-ee;
+	};
+
+	adsp_notify: qcom,msm-adsp-notify {
+		status = "ok";
+		compatible = "qcom,adsp-notify";
+		qcom,rproc-handle = <&adsp_pas>;
+	};
+
+	bluetooth: bt_qca6490 {
+		compatible = "qcom,qca6490";
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_en_sleep>;
+		qcom,bt-reset-gpio = <&tlmm 81 0>; /* BT_EN */
+		qcom,wl-reset-gpio = <&tlmm 80 0>; /* WL_EN */
+		qcom,bt-sw-ctrl-gpio = <&tlmm 82 0>; /* SW_CTRL */
+		qcom,xo-clk-gpio = <&tlmm 204 0>; /* XO */
+		mboxes = <&qmp_aop 0>;
+		qcom,vreg_ipa="s3e";
+
+		qcom,bt-vdd-aon-supply = <&S11B>;
+		qcom,bt-vdd-dig-supply = <&S11B>;
+		qcom,bt-vdd-rfa1-supply = <&S1C>;
+		qcom,bt-vdd-rfa2-supply = <&S12B>;
+		qcom,bt-vdd-asd-supply = <&L7E>;
+
+		qcom,bt-vdd-aon-config = <966000 966000 0 1>;
+		qcom,bt-vdd-dig-config = <966000 966000 0 1>;
+		qcom,bt-vdd-rfa1-config = <1900000 2100000 0 1>;
+		qcom,bt-vdd-rfa2-config = <1350000 1350000 0 1>;
+		qcom,bt-vdd-asd-config = <2800000 2800000 0 1>;
+	};
+
+	llcc_pmu: llcc-pmu@19095000 {
+		compatible = "qcom,llcc-pmu-ver2";
+		reg = <0x19095000 0x300>;
+		reg-names = "lagg-base";
+	};
+
+	qcom_pmu: qcom,pmu {
+		compatible = "qcom,pmu";
+		qcom,long-counter;
+		qcom,pmu-events-tbl =
+			< 0x0008 0xFF 0x02 0xFF >,
+			< 0x0011 0xFF 0x01 0xFF >,
+			< 0x0017 0xFF 0xFF 0xFF >,
+			< 0x002A 0xFF 0xFF 0xFF >,
+			< 0x1000 0xFF 0xFF 0xFF >;
+	};
+
+	ddr_freq_table: ddr-freq-table {
+		qcom,freq-tbl =
+			<  200000 >,
+			<  451000 >,
+			<  547000 >,
+			<  681000 >,
+			<  768000 >,
+			< 1555000 >,
+			< 1708000 >,
+			< 2092000 >,
+			< 2736000 >,
+			< 3196000 >;
+	};
+
+	llcc_freq_table: llcc-freq-table {
+		qcom,freq-tbl =
+			<  150000 >,
+			<  300000 >,
+			<  466000 >,
+			<  600000 >,
+			<  806000 >,
+			<  933000 >,
+			< 1066000 >;
+	};
+
+	ddrqos_freq_table: ddrqos-freq-table {
+		qcom,freq-tbl =
+			< 0 >,
+			< 1 >;
+	};
+
+	qcom_dcvs: qcom,dcvs {
+		compatible = "qcom,dcvs";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		qcom_l3_dcvs_hw: l3 {
+			compatible = "qcom,dcvs-hw";
+			qcom,dcvs-hw-type = <2>;
+			qcom,bus-width = <32>;
+			reg = <0x17d90000 0x4000>, <0x17d90100 0xa0>;
+			reg-names = "l3-base", "l3tbl-base";
+
+			l3_dcvs_sp: sp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <0>;
+				qcom,shared-offset = <0x0090>;
+			};
+		};
+
+		qcom_ddr_dcvs_hw: ddr {
+			compatible = "qcom,dcvs-hw";
+			qcom,dcvs-hw-type = <0>;
+			qcom,bus-width = <4>;
+			qcom,freq-tbl = <&ddr_freq_table>;
+
+			ddr_dcvs_sp: sp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <0>;
+				interconnects = <&mc_virt MASTER_LLCC
+						 &mc_virt SLAVE_EBI1>;
+			};
+
+			ddr_dcvs_fp: fp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <1>;
+				qcom,fp-voter = <&dcvs_fp>;
+			};
+		};
+
+		qcom_llcc_dcvs_hw: llcc {
+			compatible = "qcom,dcvs-hw";
+			qcom,dcvs-hw-type = <1>;
+			qcom,bus-width = <16>;
+			qcom,freq-tbl = <&llcc_freq_table>;
+
+			llcc_dcvs_sp: sp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <0>;
+				interconnects = <&gem_noc MASTER_APPSS_PROC
+						 &gem_noc SLAVE_LLCC>;
+			};
+
+			llcc_dcvs_fp: fp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <1>;
+				qcom,fp-voter = <&dcvs_fp>;
+			};
+		};
+
+		qcom_ddrqos_dcvs_hw: ddrqos {
+			compatible = "qcom,dcvs-hw";
+			qcom,dcvs-hw-type = <3>;
+			qcom,bus-width = <1>;
+			qcom,freq-tbl = <&ddrqos_freq_table>;
+
+			ddrqos_dcvs_sp: sp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <0>;
+				interconnects = <&mc_virt MASTER_LLCC
+						 &mc_virt SLAVE_EBI1>;
+			};
+		};
+	};
+
+	qcom_memlat: qcom,memlat {
+		compatible = "qcom,memlat";
+
+		ddr {
+			compatible = "qcom,memlat-grp";
+			qcom,target-dev = <&qcom_ddr_dcvs_hw>;
+			qcom,sampling-path = <&ddr_dcvs_fp>;
+			qcom,miss-ev = <0x1000>;
+
+			silver {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+				qcom,cpufreq-memfreq-tbl =
+					<  300000  200000 >,
+					<  691200  451000 >,
+					< 1190400  547000 >,
+					< 1459200  768000 >,
+					< 1900800 1555000 >;
+				qcom,sampling-enabled;
+			};
+
+			gold {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					<  300000  200000 >,
+					<  672000  451000 >,
+					<  902400  547000 >,
+					< 1017600  768000 >,
+					< 1305600 1555000 >,
+					< 1804800 1708000 >,
+					< 2188800 2092000 >,
+					< 2400000 3196000 >;
+				qcom,sampling-enabled;
+			};
+
+			gold-compute {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					< 1804800  200000 >,
+					< 2400000 1555000 >;
+				qcom,sampling-enabled;
+				qcom,compute-mon;
+			};
+
+			prime-latfloor {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					< 2304000  200000 >,
+					< 2400000 3196000 >;
+				qcom,sampling-enabled;
+			};
+		};
+
+		llcc {
+			compatible = "qcom,memlat-grp";
+			qcom,target-dev = <&qcom_llcc_dcvs_hw>;
+			qcom,sampling-path = <&llcc_dcvs_fp>;
+			qcom,miss-ev = <0x2A>;
+
+			silver {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+				qcom,cpufreq-memfreq-tbl =
+					<  300000  150000 >,
+					<  691200  300000 >,
+					< 1459200  466000 >,
+					< 1900800  600000 >;
+				qcom,sampling-enabled;
+			};
+
+			gold {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					<  300000  150000 >,
+					<  672000  300000 >,
+					< 1017600  466000 >,
+					< 1305600  600000 >,
+					< 1804800  806000 >,
+					< 2188800  933000 >,
+					< 2400000 1066000 >;
+				qcom,sampling-enabled;
+			};
+
+			gold-compute {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					< 1804800  150000 >,
+					< 2400000  600000 >;
+				qcom,sampling-enabled;
+				qcom,compute-mon;
+			};
+		};
+
+		l3 {
+			compatible = "qcom,memlat-grp";
+			qcom,target-dev = <&qcom_l3_dcvs_hw>;
+			qcom,sampling-path = <&l3_dcvs_sp>;
+			qcom,miss-ev = <0x17>;
+
+			silver {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+				qcom,cpufreq-memfreq-tbl =
+					<  300000  300000 >,
+					<  403200  403200 >,
+					<  499200  499200 >,
+					<  691200  614400 >,
+					<  806400  710400 >,
+					<  998400  806400 >,
+					< 1190400  998400 >,
+					< 1286400 1094400 >,
+					< 1459200 1248000 >,
+					< 1728000 1344000 >,
+					< 1804800 1440000 >,
+					< 1900800 1516800 >;
+				qcom,sampling-enabled;
+			};
+
+			silver-latboost {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+				qcom,cpufreq-memfreq-tbl =
+					<  300000  300000 >,
+					<  403200  710400 >,
+					<  499200  806400 >,
+					<  691200  998400 >,
+					<  806400 1094400 >,
+					<  998400 1248000 >,
+					< 1190400 1344000 >,
+					< 1286400 1440000 >,
+					< 1459200 1516800 >;
+				qcom,sampling-enabled;
+			};
+
+			gold {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
+				qcom,cpufreq-memfreq-tbl =
+					<  300000  300000 >,
+					<  787200  614400 >,
+					< 1209600  806400 >,
+					< 1497600  998400 >,
+					< 1689600 1248000 >,
+					< 1900800 1344000 >,
+					< 2188800 1440000 >,
+					< 2400000 1516800 >;
+				qcom,sampling-enabled;
+			};
+
+			gold-latboost {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					<  300000  300000 >,
+					<  787200 1248000 >,
+					< 1209600 1344000 >,
+					< 1497600 1440000 >,
+					< 2400000 1516800 >;
+				qcom,sampling-enabled;
+			};
+
+			prime {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					<  300000  300000 >,
+					<  787200  614400 >,
+					< 1209600  806400 >,
+					< 1497600  998400 >,
+					< 1689600 1248000 >,
+					< 1900800 1344000 >,
+					< 2188800 1440000 >,
+					< 2400000 1516800 >;
+				qcom,sampling-enabled;
+			};
+
+			prime-compute {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					< 1996800  300000 >,
+					< 2400000 1516800 >;
+				qcom,sampling-enabled;
+				qcom,compute-mon;
+			};
+		};
+
+		ddrqos {
+			compatible = "qcom,memlat-grp";
+			qcom,target-dev = <&qcom_ddrqos_dcvs_hw>;
+			qcom,sampling-path = <&ddrqos_dcvs_sp>;
+			qcom,miss-ev = <0x1000>;
+
+			ddrqos_gold_lat: gold {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					<  300000 0 >,
+					< 2400000 1 >;
+				qcom,sampling-enabled;
+			};
+
+			ddrqos_prime_latfloor: prime-latfloor {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					< 1996800 0 >,
+					< 2400000 1 >;
+				qcom,sampling-enabled;
+			};
+		};
+	};
+
+	bwmon_llcc: qcom,bwmon-llcc@190b6400 {
+		compatible = "qcom,bwmon4";
+		reg = <0x190b6400 0x300>, <0x190b6300 0x200>;
+		reg-names = "base", "global_base";
+		interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,mport = <0>;
+		qcom,hw-timer-hz = <19200000>;
+		qcom,count-unit = <0x10000>;
+		qcom,target-dev = <&qcom_llcc_dcvs_hw>;
+	};
+
+	bwmon_ddr: qcom,bwmon-ddr@19091000 {
+		compatible = "qcom,bwmon5";
+		reg = <0x19091000 0x1000>;
+		reg-names = "base";
+		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,hw-timer-hz = <19200000>;
+		qcom,count-unit = <0x10000>;
+		qcom,target-dev = <&qcom_ddr_dcvs_hw>;
+	};
+
+	trust_ui_vm: qcom,trust_ui_vm@e55fc000 {
+		reg = <0xe55fc000 0x104000>;
+		vm_name = "trustedvm";
+		shared-buffers = <&trust_ui_vm_vblk0_ring &trust_ui_vm_swiotlb>;
+	};
+
+	qcom,virtio_backend@0 {
+		compatible = "qcom,virtio_backend";
+		qcom,vm = <&trust_ui_vm>;
+		qcom,label = <0x11>;
+	};
+
+	qcom,msm_gsi {
+		compatible = "qcom,msm_gsi";
+	};
+
+	qcom,rmnet-ipa {
+		compatible = "qcom,rmnet-ipa3";
+		qcom,rmnet-ipa-ssr;
+		qcom,ipa-platform-type-msm;
+		qcom,ipa-advertise-sg-support;
+		qcom,ipa-napi-enable;
+	};
+
+	qcom,ipa_fws {
+		compatible = "qcom,pil-tz-generic";
+		qcom,pas-id = <0xf>;
+		qcom,firmware-name = "ipa_fws";
+		qcom,pil-force-shutdown;
+		status = "disabled";
+	};
+
+	qcom,qbt_handler {
+		compatible = "qcom,qbt-handler";
+		qcom,ipc-gpio = <&tlmm 40 0>;
+		qcom,finger-detect-gpio = <&tlmm 41 0>;
+		qcom,intr2-gpio = <&tlmm 42 0>;
+	};
+
+	wlan: qcom,cnss-qca6490@b0000000 {
+		compatible = "qcom,cnss-qca6490";
+		reg = <0xb0000000 0x10000>;
+		reg-names = "smmu_iova_ipa";
+		wlan-en-gpio = <&tlmm 80 0>;
+		qcom,bt-en-gpio = <&tlmm 81 0>;
+		pinctrl-names = "wlan_en_active", "wlan_en_sleep";
+		pinctrl-0 = <&cnss_wlan_en_active>;
+		pinctrl-1 = <&cnss_wlan_en_sleep>;
+		qcom,wlan-rc-num = <0>;
+		qcom,wlan-ramdump-dynamic = <0x420000>;
+		qcom,wlan-cbc-enabled;
+		use-pm-domain;
+		cnss-enable-self-recovery;
+		qcom,same-dt-multi-dev;
+		mboxes = <&qmp_aop 0>;
+		qcom,vreg_ipa="s3e";
+		qcom,xo-clk-gpio = <&tlmm 204 0>;
+
+		vdd-wlan-aon-supply = <&S2E>;
+		qcom,vdd-wlan-aon-config = <1012000 1012000 0 0 1>;
+		vdd-wlan-dig-supply = <&S11B>;
+		qcom,vdd-wlan-dig-config = <966000 966000 0 0 1>;
+		vdd-wlan-io-supply = <&S10B>;
+		qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
+		vdd-wlan-rfa1-supply = <&S1C>;
+		qcom,vdd-wlan-rfa1-config = <1900000 2100000 0 0 1>;
+		vdd-wlan-rfa2-supply = <&S12B>;
+		qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>;
+		wlan-ant-switch-supply = <&L7E>;
+		qcom,wlan-ant-switch-config = <2800000 2800000 0 0 1>;
+
+		interconnects =
+		<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
+		<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
+		interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
+
+
+		qcom,icc-path-count = <2>;
+		qcom,bus-bw-cfg-count = <7>;
+		qcom,bus-bw-cfg =
+		/** ICC Path 1 **/
+		<0 0>, /* no vote */
+		/* idle: 0-18 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
+		<2250 390000>,
+		/* low: 18-60 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
+		<7500 390000>,
+		/* medium: 60-240 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */
+		<30000 790000>,
+		/* high: 240-1080 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */
+		<100000 790000>,
+		/* very high: > 1080 Mbps snoc/anoc: 403 Mhz ddr: 451.2 MHz */
+		<175000 1600000>,
+		/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz
+		 * ddr: 547.2 MHz
+		 */
+		<7500 390000>,
+
+		/** ICC Path 2 **/
+		<0 0>,
+		<2250 1804800>,
+		<7500 1804800>,
+		<30000 1804800>,
+		<100000 1804800>,
+		<175000 6220800>,
+		<7500 2188800>;
+	};
+
+	ipa_hw: qcom,ipa@3e00000 {
+		compatible = "qcom,ipa";
+		reg =
+			<0x3e00000 0x84000>,
+			<0x3e04000 0xfc000>;
+		reg-names = "ipa-base", "gsi-base";
+		pas-ids = <0xf>;
+		firmware-names = "ipa_fws";
+		memory-regions = <&ipa_gsi_mem>;
+		qcom,ipa-cfg-offset = <0x0140000>;
+		interrupts =
+			<0 654 IRQ_TYPE_LEVEL_HIGH>,
+			<0 432 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "ipa-irq", "gsi-irq";
+		qcom,ipa-hw-ver = <22>; /* IPA core version = IPAv5.1 */
+		qcom,ipa-hw-mode = <0>;
+		qcom,platform-type = <1>; /* MSM platform */
+		qcom,ee = <0>;
+		qcom,use-ipa-tethering-bridge;
+		qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */
+		qcom,modem-cfg-emb-pipe-flt;
+		qcom,ipa-wdi3-over-gsi;
+		qcom,arm-smmu;
+		qcom,smmu-fast-map;
+		qcom,use-64-bit-dma-mask;
+		qcom,ipa-endp-delay-wa-v2;
+		qcom,ipa-ulso-wa;
+		qcom,lan-rx-napi;
+		qcom,tx-napi;
+		qcom,tx-poll;
+		qcom,wan-use-skb-page;
+		qcom,rmnet-ctl-enable;
+		qcom,rmnet-ll-enable;
+		qcom,ipa-uc-holb-monitor;
+		qcom,ipa-holb-monitor-poll-period = <5>;
+		qcom,ipa-holb-monitor-max-cnt-wlan = <10>;
+		qcom,ipa-holb-monitor-max-cnt-usb = <10>;
+		qcom,ipa-holb-monitor-max-cnt-11ad = <10>;
+		qcom,tx-wrapper-cache-max-size = <400>;
+		qcom,ipa-gpi-event-rp-ddr;
+		qcom,ulso-supported;
+		qcom,ulso-ip-id-min-linux-val = <0>;
+		qcom,ulso-ip-id-max-linux-val = <0xffff>;
+		qcom,ulso-ip-id-min-windows-val = <0>;
+		qcom,ulso-ip-id-max-windows-val = <0x7fff>;
+		qcom,max_num_smmu_cb = <4>;
+		clock-names = "core_clk";
+		clocks = <&clock_rpmh RPMH_IPA_CLK>;
+		qcom,interconnect,num-cases = <5>;
+		qcom,interconnect,num-paths = <3>;
+		interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
+			<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
+		interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa";
+		/* No vote */
+		qcom,no-vote =
+		<0 0 0 0 0 0>;
+
+		/* SVS2 */
+		qcom,svs2 =
+		<600000 0 600000 1900000 0 76800>;
+
+		/* SVS */
+		qcom,svs =
+		<1200000 0 1200000 2800000 0 150000>;
+
+		/* NOMINAL */
+		qcom,nominal =
+		<2400000 0 2400000 5500000 0 400000>;
+
+		/* TURBO */
+		qcom,turbo =
+		<3600000 0 3600000 5500000 0 400000>;
+
+		qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
+			"TURBO";
+		qcom,throughput-threshold = <2000 4000 8000>;
+		qcom,scaling-exceptions = <>;
+
+		/* smp2p information */
+		qcom,smp2p_map_ipa_1_out {
+			compatible = "qcom,smp2p-map-ipa-1-out";
+			qcom,smem-states = <&smp2p_ipa_1_out 0>;
+			qcom,smem-state-names = "ipa-smp2p-out";
+		};
+
+		qcom,smp2p_map_ipa_1_in {
+			compatible = "qcom,smp2p-map-ipa-1-in";
+			interrupts-extended = <&smp2p_ipa_1_in 0 0>;
+			interrupt-names = "ipa-smp2p-in";
+		};
+
+		ipa_smmu_ap: ipa_smmu_ap {
+			compatible = "qcom,ipa-smmu-ap-cb";
+			iommus = <&apps_smmu 0x5C0 0x0>;
+			qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
+			qcom,additional-mapping =
+				/* modem tables in IMEM */
+				<0x146A8000 0x146A8000 0x2000>;
+			qcom,iommu-dma = "fastmap";
+			dma-coherent;
+			qcom,ipa-q6-smem-size = <36864>;
+		};
+
+		ipa_smmu_wlan: ipa_smmu_wlan {
+			compatible = "qcom,ipa-smmu-wlan-cb";
+			iommus = <&apps_smmu 0x5C1 0x0>;
+			qcom,iommu-dma = "atomic";
+			dma-coherent;
+		};
+
+		ipa_smmu_uc: ipa_smmu_uc {
+			compatible = "qcom,ipa-smmu-uc-cb";
+			iommus = <&apps_smmu 0x5C2 0x0>;
+			qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
+			qcom,iommu-dma = "atomic";
+			dma-coherent;
+		};
+
+		ipa_smmu_11ad: ipa_smmu_11ad {
+			compatible = "qcom,ipa-smmu-11ad-cb";
+			iommus = <&apps_smmu 0x5C4 0x0>;
+			dma-coherent;
+			qcom,shared-cb;
+			qcom,iommu-group = <>;
+		};
+	};
+
+	mhi_qrtr_cnss {
+		compatible = "qcom,qrtr-mhi";
+		qcom,dev-id = <0x1103>;
+		qcom,net-id = <0>;
+		qcom,low-latency;
+	};
+};
+
+#include "ipcc-test.dtsi"
+#include "waipio-qupv3.dtsi"
+#include "waipio-pinctrl.dtsi"
+#include "msm-arm-smmu-waipio.dtsi"
+#include "waipio-smp2p.dtsi"
+#include "waipio-regulators.dtsi"
+#include "waipio-usb.dtsi"
+#include "waipio-coresight.dtsi"
+#include "waipio-dma-heaps.dtsi"
+#include "waipio-debug.dtsi"
+#include "waipio-eva.dtsi"
+#include "waipio-pcie.dtsi"
+#include "msm-rdbg.dtsi"
+#include "waipio-gpu.dtsi"
+#include "waipio-thermal.dtsi"
+
+&pcie0_rp {
+	#address-cells = <5>;
+	#size-cells = <0>;
+
+	cnss_pci: cnss_pci {
+		reg = <0 0 0 0 0>;
+		qcom,iommu-group = <&cnss_pci_iommu_group>;
+		memory-region = <&cnss_wlan_mem>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cnss_pci_iommu_group: cnss_pci_iommu_group {
+			qcom,iommu-msi-size = <0x1000>;
+			qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
+			qcom,iommu-dma = "fastmap";
+			qcom,iommu-pagetable = "coherent";
+			qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE",
+					    "non-fatal";
+		};
+	};
+};
+
+&qupv3_se7_2uart {
+	status = "ok";
+};
+
+&qupv3_se20_4uart {
+	status = "ok";
+};
+
+&qupv3_se5_i2c {
+	status = "ok";
+	nq@64 {
+		compatible = "rtc6226";
+		reg = <0x64>;
+		fmint-gpio = <&tlmm 44 0>;
+		vdd-supply = <&L7E>;
+		rtc6226,vdd-supply-voltage = <2800000 2800000>;
+		rtc6226,vdd-load = <15000>;
+		vio-supply = <&S10B>;
+		rtc6226,vio-supply-voltage = <1800000 1800000 >;
+	};
+
+	fsa4480: fsa4480@42 {
+		compatible = "qcom,fsa4480-i2c";
+		reg = <0x42>;
+	};
+};
diff --git a/qcom/waipiop-cdp-pm8008.dts b/qcom/waipiop-cdp-pm8008.dts
new file mode 100644
index 00000000..45f09fb7
--- /dev/null
+++ b/qcom/waipiop-cdp-pm8008.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipiop.dtsi"
+#include "waipio-cdp.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP CDP with PM8008";
+	compatible = "qcom,waipiop-cdp", "qcom,waipiop", "qcom,cdp";
+	qcom,board-id = <1 0>;
+};
diff --git a/qcom/waipiop-cdp-pm8010.dts b/qcom/waipiop-cdp-pm8010.dts
new file mode 100644
index 00000000..52efb57e
--- /dev/null
+++ b/qcom/waipiop-cdp-pm8010.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipiop.dtsi"
+#include "waipio-cdp.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP CDP with PM8010";
+	compatible = "qcom,waipiop-cdp", "qcom,waipiop", "qcom,cdp";
+	qcom,board-id = <0x10001 0>;
+};
diff --git a/qcom/waipiop-hdk-pm8010-overlay.dts b/qcom/waipiop-hdk-pm8010-overlay.dts
new file mode 100644
index 00000000..e363704a
--- /dev/null
+++ b/qcom/waipiop-hdk-pm8010-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "waipio-hdk.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP HDK with PM8010";
+	compatible = "qcom,waipiop-hdk", "qcom,waipiop", "qcom,hdk";
+	qcom,msm-id = <482 0x10000>, <482 0x20000>;
+	qcom,board-id = <0x1001f 0>;
+};
diff --git a/qcom/waipiop-hdk-pm8010.dts b/qcom/waipiop-hdk-pm8010.dts
new file mode 100644
index 00000000..3b14fdec
--- /dev/null
+++ b/qcom/waipiop-hdk-pm8010.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipiop.dtsi"
+#include "waipio-hdk.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP HDK with PM8010";
+	compatible = "qcom,waipiop-hdk", "qcom,waipiop", "qcom,hdk";
+	qcom,board-id = <0x1001f 0>;
+};
diff --git a/qcom/waipiop-mtp-pm8008.dts b/qcom/waipiop-mtp-pm8008.dts
new file mode 100644
index 00000000..22065a9d
--- /dev/null
+++ b/qcom/waipiop-mtp-pm8008.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipiop.dtsi"
+#include "waipio-mtp.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP MTP with PM8008";
+	compatible = "qcom,waipiop-mtp", "qcom,waipiop", "qcom,mtp";
+	qcom,board-id = <8 0>;
+};
diff --git a/qcom/waipiop-mtp-pm8010.dts b/qcom/waipiop-mtp-pm8010.dts
new file mode 100644
index 00000000..52d055ce
--- /dev/null
+++ b/qcom/waipiop-mtp-pm8010.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipiop.dtsi"
+#include "waipio-mtp.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP MTP with PM8010";
+	compatible = "qcom,waipiop-mtp", "qcom,waipiop", "qcom,mtp";
+	qcom,board-id = <0x10008 0>;
+};
diff --git a/qcom/waipiop-qrd-pm8008.dts b/qcom/waipiop-qrd-pm8008.dts
new file mode 100644
index 00000000..7a092126
--- /dev/null
+++ b/qcom/waipiop-qrd-pm8008.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipiop.dtsi"
+#include "waipio-qrd.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP QRD with PM8008";
+	compatible = "qcom,waipiop-qrd", "qcom,waipiop", "qcom,qrd";
+	qcom,board-id = <11 0>;
+};
diff --git a/qcom/waipiop-qrd-pm8010-2s.dts b/qcom/waipiop-qrd-pm8010-2s.dts
new file mode 100644
index 00000000..f6b43da3
--- /dev/null
+++ b/qcom/waipiop-qrd-pm8010-2s.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipiop.dtsi"
+#include "waipio-qrd-2s.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP QRD with PM8010";
+	compatible = "qcom,waipiop-qrd", "qcom,waipiop", "qcom,qrd";
+	qcom,board-id = <0x2000b 0>;
+};
diff --git a/qcom/waipiop-qrd-pm8010.dts b/qcom/waipiop-qrd-pm8010.dts
new file mode 100644
index 00000000..6fdb588d
--- /dev/null
+++ b/qcom/waipiop-qrd-pm8010.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipiop.dtsi"
+#include "waipio-qrd.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP QRD with PM8010";
+	compatible = "qcom,waipiop-qrd", "qcom,waipiop", "qcom,qrd";
+	qcom,board-id = <0x1000b 0>;
+};
diff --git a/qcom/waipiop-v2-cdp-pm8008.dts b/qcom/waipiop-v2-cdp-pm8008.dts
new file mode 100644
index 00000000..5de26041
--- /dev/null
+++ b/qcom/waipiop-v2-cdp-pm8008.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipiop-v2.dtsi"
+#include "waipio-cdp.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP v2 CDP with PM8008";
+	compatible = "qcom,waipiop-cdp", "qcom,waipiop", "qcom,cdp";
+	qcom,board-id = <1 0>;
+};
diff --git a/qcom/waipiop-v2-cdp-pm8010.dts b/qcom/waipiop-v2-cdp-pm8010.dts
new file mode 100644
index 00000000..bbec9f1a
--- /dev/null
+++ b/qcom/waipiop-v2-cdp-pm8010.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipiop-v2.dtsi"
+#include "waipio-cdp.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP v2 CDP with PM8010";
+	compatible = "qcom,waipiop-cdp", "qcom,waipiop", "qcom,cdp";
+	qcom,board-id = <0x10001 0>;
+};
diff --git a/qcom/waipiop-v2-hdk-pm8010.dts b/qcom/waipiop-v2-hdk-pm8010.dts
new file mode 100644
index 00000000..97a76196
--- /dev/null
+++ b/qcom/waipiop-v2-hdk-pm8010.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipiop-v2.dtsi"
+#include "waipio-hdk.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. v2 WaipioP HDK with PM8010";
+	compatible = "qcom,waipiop-hdk", "qcom,waipiop", "qcom,hdk";
+	qcom,board-id = <0x1001f 0>;
+};
diff --git a/qcom/waipiop-v2-mtp-pm8008.dts b/qcom/waipiop-v2-mtp-pm8008.dts
new file mode 100644
index 00000000..a0e1a959
--- /dev/null
+++ b/qcom/waipiop-v2-mtp-pm8008.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipiop-v2.dtsi"
+#include "waipio-mtp.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP v2 MTP with PM8008";
+	compatible = "qcom,waipiop-mtp", "qcom,waipiop", "qcom,mtp";
+	qcom,board-id = <8 0>;
+};
diff --git a/qcom/waipiop-v2-mtp-pm8010.dts b/qcom/waipiop-v2-mtp-pm8010.dts
new file mode 100644
index 00000000..5e71e2ab
--- /dev/null
+++ b/qcom/waipiop-v2-mtp-pm8010.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipiop-v2.dtsi"
+#include "waipio-mtp.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP v2 MTP with PM8010";
+	compatible = "qcom,waipiop-mtp", "qcom,waipiop", "qcom,mtp";
+	qcom,board-id = <0x10008 0>;
+};
diff --git a/qcom/waipiop-v2-qrd-pm8008.dts b/qcom/waipiop-v2-qrd-pm8008.dts
new file mode 100644
index 00000000..7d6251e5
--- /dev/null
+++ b/qcom/waipiop-v2-qrd-pm8008.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipiop-v2.dtsi"
+#include "waipio-qrd.dtsi"
+#include "waipio-pm8008.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP v2 QRD with PM8008";
+	compatible = "qcom,waipiop-qrd", "qcom,waipiop", "qcom,qrd";
+	qcom,board-id = <11 0>;
+};
diff --git a/qcom/waipiop-v2-qrd-pm8010-2s.dts b/qcom/waipiop-v2-qrd-pm8010-2s.dts
new file mode 100644
index 00000000..e4a7e915
--- /dev/null
+++ b/qcom/waipiop-v2-qrd-pm8010-2s.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipiop-v2.dtsi"
+#include "waipio-qrd-2s.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP v2 QRD with PM8010";
+	compatible = "qcom,waipiop-qrd", "qcom,waipiop", "qcom,qrd";
+	qcom,board-id = <0x2000b 0>;
+};
diff --git a/qcom/waipiop-v2-qrd-pm8010.dts b/qcom/waipiop-v2-qrd-pm8010.dts
new file mode 100644
index 00000000..b79b8ee0
--- /dev/null
+++ b/qcom/waipiop-v2-qrd-pm8010.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "waipiop-v2.dtsi"
+#include "waipio-qrd.dtsi"
+#include "waipio-pm8010-spmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP v2 QRD with PM8010";
+	compatible = "qcom,waipiop-qrd", "qcom,waipiop", "qcom,qrd";
+	qcom,board-id = <0x1000b 0>;
+};
diff --git a/qcom/waipiop-v2.dts b/qcom/waipiop-v2.dts
new file mode 100644
index 00000000..e8f8e999
--- /dev/null
+++ b/qcom/waipiop-v2.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "waipiop-v2.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP v2 SoC";
+	compatible = "qcom,waipiop";
+	qcom,board-id = <0 0>;
+};
diff --git a/qcom/waipiop-v2.dtsi b/qcom/waipiop-v2.dtsi
new file mode 100644
index 00000000..6ed8dc7e
--- /dev/null
+++ b/qcom/waipiop-v2.dtsi
@@ -0,0 +1,7 @@
+#include "waipiop.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP v2";
+	compatible = "qcom,waipiop";
+	qcom,msm-id = <482 0x20000>;
+};
diff --git a/qcom/waipiop.dts b/qcom/waipiop.dts
new file mode 100644
index 00000000..969a53db
--- /dev/null
+++ b/qcom/waipiop.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "waipiop.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP SoC";
+	compatible = "qcom,waipiop";
+	qcom,board-id = <0 0>;
+};
diff --git a/qcom/waipiop.dtsi b/qcom/waipiop.dtsi
new file mode 100644
index 00000000..786abade
--- /dev/null
+++ b/qcom/waipiop.dtsi
@@ -0,0 +1,11 @@
+#include "waipio.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. WaipioP";
+	compatible = "qcom,waipiop";
+	qcom,msm-id = <482 0x10000>;
+};
+
+&ipa_hw {
+	status = "disabled";
+};