From 08f227de56c5283f31546efce013ec30c1d5ef0f Mon Sep 17 00:00:00 2001
From: Yatish Kumar Singh <yatishku@qti.qualcomm.com>
Date: Thu, 26 May 2022 17:52:27 +0530
Subject: [PATCH] ARM: dts: msm: Update QUPV3 UART DTSI Entries for Cinder

Updated QUPV3 UART DTSI Entries for Cinder.
Added QUPV3 HSUART aliases for Cinder.

Change-Id: I731d270e3282754ab95af039b42461fecfc3946a
---
 qcom/cinder-pinctrl.dtsi |  4 ++--
 qcom/cinder-qupv3.dtsi   | 22 ++++++----------------
 qcom/cinder.dtsi         |  2 ++
 3 files changed, 10 insertions(+), 18 deletions(-)

diff --git a/qcom/cinder-pinctrl.dtsi b/qcom/cinder-pinctrl.dtsi
index e7feffd4..cdbc7531 100644
--- a/qcom/cinder-pinctrl.dtsi
+++ b/qcom/cinder-pinctrl.dtsi
@@ -233,7 +233,7 @@
 			config {
 				pins = "gpio9";
 				drive-strength = <2>;
-				bias-disable;
+				bias-pull-down;
 			};
 		};
 	};
@@ -339,7 +339,7 @@
 			config {
 				pins = "gpio21";
 				drive-strength = <2>;
-				bias-disable;
+				bias-pull-down;
 			};
 		};
 	};
diff --git a/qcom/cinder-qupv3.dtsi b/qcom/cinder-qupv3.dtsi
index 199613c1..7b193c7d 100644
--- a/qcom/cinder-qupv3.dtsi
+++ b/qcom/cinder-qupv3.dtsi
@@ -61,6 +61,7 @@
 		qcom,iommu-geometry = <0x40000000 0x10000000>;
 		qcom,iommu-dma = "fastmap";
 		dma-coherent;
+		ranges;
 		status = "ok";
 
 		/* Debug UART Instance */
@@ -87,8 +88,7 @@
 			compatible = "qcom,msm-geni-serial-hs";
 			reg = <0x980000 0x4000>;
 			reg-names = "se_phys";
-			interrupts-extended = <&intc GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>,
-					<&tlmm 79 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 			clock-names = "se-clk";
 			clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 			interconnect-names = "qup-core", "qup-config", "qup-memory";
@@ -96,16 +96,11 @@
 			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
 			<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>,
 			<&system_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
-			pinctrl-names = "default", "active", "sleep", "shutdown";
+			pinctrl-names = "default", "sleep";
 			pinctrl-0 = <&qupv3_se0_default_cts>, <&qupv3_se0_default_rts>,
 			<&qupv3_se0_default_tx>, <&qupv3_se0_default_rx>;
 			pinctrl-1 = <&qupv3_se0_cts>, <&qupv3_se0_rts>,
 			<&qupv3_se0_tx>, <&qupv3_se0_rx>;
-			pinctrl-2 = <&qupv3_se0_cts>, <&qupv3_se0_rts>,
-			<&qupv3_se0_tx>, <&qupv3_se0_default_rx>;
-			pinctrl-3 = <&qupv3_se0_default_cts>, <&qupv3_se0_default_rts>,
-			<&qupv3_se0_default_tx>, <&qupv3_se0_default_rx>;
-			qcom,wakeup-byte = <0xFD>;
 			status = "disabled";
 		};
 
@@ -434,6 +429,7 @@
 		qcom,iommu-geometry = <0x40000000 0x10000000>;
 		qcom,iommu-dma = "fastmap";
 		dma-coherent;
+		ranges;
 		status = "ok";
 
 		/* IPC HSUART Instance */
@@ -441,8 +437,7 @@
 			compatible = "qcom,msm-geni-serial-hs";
 			reg = <0xa80000 0x4000>;
 			reg-names = "se_phys";
-			interrupts-extended = <&intc GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
-					<&tlmm 79 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 			clock-names = "se-clk";
 			clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 			interconnect-names = "qup-core", "qup-config", "qup-memory";
@@ -450,16 +445,11 @@
 			<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
 			<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_1>,
 			<&system_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
-			pinctrl-names = "default", "active", "sleep", "shutdown";
+			pinctrl-names = "default", "sleep";
 			pinctrl-0 = <&qupv3_se8_default_cts>, <&qupv3_se8_default_rts>,
 			<&qupv3_se8_default_tx>, <&qupv3_se8_default_rx>;
 			pinctrl-1 = <&qupv3_se8_cts>, <&qupv3_se8_rts>,
 			<&qupv3_se8_tx>, <&qupv3_se8_rx>;
-			pinctrl-2 = <&qupv3_se8_cts>, <&qupv3_se8_rts>,
-			<&qupv3_se8_tx>, <&qupv3_se8_default_rx>;
-			pinctrl-3 = <&qupv3_se8_default_cts>, <&qupv3_se8_default_rts>,
-			<&qupv3_se8_default_tx>, <&qupv3_se8_default_rx>;
-			qcom,wakeup-byte = <0xFD>;
 			status = "disabled";
 		};
 
diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi
index 6c86af5a..22c465f0 100644
--- a/qcom/cinder.dtsi
+++ b/qcom/cinder.dtsi
@@ -24,6 +24,8 @@
 	aliases {
 		serial0 = &qupv3_se7_2uart;
 		mmc0 = &sdhc_1; /*SDC1 eMMC slot*/
+		hsuart0 = &qupv3_se0_4uart; /* CerebrusX debug HSUART Instance */
+		hsuart1 = &qupv3_se8_4uart; /* IPC HSUART Instance */
 	};
 
 	firmware: firmware { };