From ecb6d523f2185faa97fb02011d1c9ef19795c9be Mon Sep 17 00:00:00 2001 From: Mao Jinlong Date: Mon, 18 Jul 2022 02:37:00 -0700 Subject: [PATCH] ARM: dts: msm: Disable tmess ctis Disable tmess ctis as registers of these CTIs can't be accessed on secure device. Change-Id: I13660456aec7e22a85d0281c1cbc5d5732efc1cf --- qcom/cinder-coresight.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/cinder-coresight.dtsi b/qcom/cinder-coresight.dtsi index 57fc76d3..e4e39307 100644 --- a/qcom/cinder-coresight.dtsi +++ b/qcom/cinder-coresight.dtsi @@ -2818,6 +2818,7 @@ arm,primecell-periphid = <0x000bb922>; coresight-name = "coresight-cti-tmess_cti_0"; qcom,extended_cti; + status = "disabled"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; }; @@ -2829,6 +2830,7 @@ arm,primecell-periphid = <0x000bb922>; coresight-name = "coresight-cti-tmess_cti_1"; qcom,extended_cti; + status = "disabled"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; }; @@ -2840,6 +2842,7 @@ arm,primecell-periphid = <0x000bb922>; coresight-name = "coresight-cti-tmess_cti_2"; qcom,extended_cti; + status = "disabled"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; }; @@ -2851,6 +2854,7 @@ arm,primecell-periphid = <0x000bb922>; coresight-name = "coresight-cti-tmess_cti_3"; qcom,extended_cti; + status = "disabled"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; }; @@ -2862,6 +2866,7 @@ arm,primecell-periphid = <0x000bb922>; coresight-name = "coresight-cti-tmess_cti_4"; qcom,extended_cti; + status = "disabled"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; }; @@ -2873,6 +2878,7 @@ arm,primecell-periphid = <0x000bb922>; coresight-name = "coresight-cti-tmess_cpu"; + status = "disabled"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; };