diff --git a/qcom/sa410m-pinctrl.dtsi b/qcom/sa410m-pinctrl.dtsi
index 176799d2..db93d342 100644
--- a/qcom/sa410m-pinctrl.dtsi
+++ b/qcom/sa410m-pinctrl.dtsi
@@ -1,4 +1,440 @@
 &tlmm {
+	qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
+		qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active {
+			mux {
+				pins = "gpio0";
+				function = "qup0_se0_l0";
+			};
+
+			config {
+				pins = "gpio0";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active {
+			mux {
+				pins = "gpio1";
+				function = "qup0_se0_l1";
+			};
+
+			config {
+				pins = "gpio1";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
+			mux {
+				pins = "gpio0", "gpio1";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio0", "gpio1";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se0_spi_pins: qupv3_se0_spi_pins {
+		qupv3_se0_spi_miso_active: qupv3_se0_spi_miso_active {
+			mux {
+				pins = "gpio0";
+				function = "qup0_se0_l0";
+			};
+
+			config {
+				pins = "gpio0";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se0_spi_mosi_active: qupv3_se0_spi_mosi_active {
+			mux {
+				pins = "gpio1";
+				function = "qup0_se0_l1";
+			};
+
+			config {
+				pins = "gpio1";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se0_spi_clk_active: qupv3_se0_spi_clk_active {
+			mux {
+				pins = "gpio2";
+				function = "qup0_se0_l2";
+			};
+
+			config {
+				pins = "gpio2";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active {
+			mux {
+				pins = "gpio3";
+				function = "qup0_se0_l3";
+			};
+
+			config {
+				pins = "gpio3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
+			mux {
+				pins = "gpio0", "gpio1",
+					"gpio2", "gpio3";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio0", "gpio1",
+					"gpio2", "gpio3";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
+		qupv3_se1_i2c_sda_active: qupv3_se1_i2c_sda_active {
+			mux {
+				pins = "gpio4";
+				function = "qup0_se1_l0";
+			};
+
+			config {
+				pins = "gpio4";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se1_i2c_scl_active: qupv3_se1_i2c_scl_active {
+			mux {
+				pins = "gpio5";
+				function = "qup0_se1_l1";
+			};
+
+			config {
+				pins = "gpio5";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
+			mux {
+				pins = "gpio4", "gpio5";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio4", "gpio5";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se1_spi_pins: qupv3_se1_spi_pins {
+		qupv3_se1_spi_miso_active: qupv3_se1_spi_miso_active {
+			mux {
+				pins = "gpio4";
+				function = "qup0_se1_l0";
+			};
+
+			config {
+				pins = "gpio4";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se1_spi_mosi_active: qupv3_se1_spi_mosi_active {
+			mux {
+				pins = "gpio5";
+				function = "qup0_se1_l1";
+			};
+
+			config {
+				pins = "gpio5";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se1_spi_clk_active: qupv3_se1_spi_clk_active {
+			mux {
+				pins = "gpio69";
+				function = "qup0_se1_l2";
+			};
+
+			config {
+				pins = "gpio69";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se1_spi_cs_active: qupv3_se1_spi_cs_active {
+			mux {
+				pins = "gpio70";
+				function = "qup0_se1_l3";
+			};
+
+			config {
+				pins = "gpio70";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
+			mux {
+				pins = "gpio4", "gpio5",
+					"gpio69", "gpio70";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio4", "gpio5",
+					"gpio69", "gpio70";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
+		qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active {
+			mux {
+				pins = "gpio6";
+				function = "qup0_se2_l0";
+			};
+
+			config {
+				pins = "gpio6";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active {
+			mux {
+				pins = "gpio7";
+				function = "qup0_se2_l1";
+			};
+
+			config {
+				pins = "gpio7";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
+			mux {
+				pins = "gpio6", "gpio7";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio6", "gpio7";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se2_spi_pins: qupv3_se2_spi_pins {
+		qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active {
+			mux {
+				pins = "gpio6";
+				function = "qup0_se2_l0";
+			};
+
+			config {
+				pins = "gpio6";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active {
+			mux {
+				pins = "gpio7";
+				function = "qup0_se2_l1";
+			};
+
+			config {
+				pins = "gpio7";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active {
+			mux {
+				pins = "gpio71";
+				function = "qup0_se2_l2";
+			};
+
+			config {
+				pins = "gpio71";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active {
+			mux {
+				pins = "gpio80";
+				function = "qup0_se2_l3";
+			};
+
+			config {
+				pins = "gpio80";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
+			mux {
+				pins = "gpio6", "gpio7",
+					"gpio71", "gpio80";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio6", "gpio7",
+					"gpio71", "gpio80";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se3_4uart_pins: qupv3_se3_4uart_pins {
+		qupv3_se3_default_cts: qupv3_se3_default_cts {
+			mux {
+				pins = "gpio8";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio8";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se3_default_rts: qupv3_se3_default_rts {
+			mux {
+				pins = "gpio9";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio9";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se3_default_tx: qupv3_se3_default_tx {
+			mux {
+				pins = "gpio10";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio10";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se3_default_rx: qupv3_se3_default_rx {
+			mux {
+				pins = "gpio11";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio11";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se3_cts: qupv3_se3_cts {
+			mux {
+				pins = "gpio8";
+				function = "qup0_se3_l0";
+			};
+
+			config {
+				pins = "gpio8";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se3_rts: qupv3_se3_rts {
+			mux {
+				pins = "gpio9";
+				function = "qup0_se3_l1";
+			};
+
+			config {
+				pins = "gpio9";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se3_tx: qupv3_se3_tx {
+			mux {
+				pins = "gpio10";
+				function = "qup0_se3_l2";
+			};
+
+			config {
+				pins = "gpio10";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se3_rx: qupv3_se3_rx {
+			mux {
+				pins = "gpio11";
+				function = "qup0_se3_l3";
+			};
+
+			config {
+				pins = "gpio11";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
 	qupv3_se4_2uart_pins: qupv3_se4_2uart_pins {
 		qupv3_se4_2uart_tx_active: qupv3_se4_2uart_tx_active {
 			mux {
@@ -39,4 +475,114 @@
 			};
 		};
 	};
+
+	qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
+		qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active {
+			mux {
+				pins = "gpio14";
+				function = "qup0_se5_l0";
+			};
+
+			config {
+				pins = "gpio14";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active {
+			mux {
+				pins = "gpio15";
+				function = "qup0_se5_l1";
+			};
+
+			config {
+				pins = "gpio15";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
+			mux {
+				pins = "gpio14", "gpio15";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio14", "gpio15";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se5_spi_pins: qupv3_se5_spi_pins {
+		qupv3_se5_spi_miso_active: qupv3_se5_spi_miso_active {
+			mux {
+				pins = "gpio14";
+				function = "qup0_se5_l0";
+			};
+
+			config {
+				pins = "gpio14";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se5_spi_mosi_active: qupv3_se5_spi_mosi_active {
+			mux {
+				pins = "gpio15";
+				function = "qup0_se5_l1";
+			};
+
+			config {
+				pins = "gpio15";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se5_spi_clk_active: qupv3_se5_spi_clk_active {
+			mux {
+				pins = "gpio16";
+				function = "qup0_se5_l2";
+			};
+
+			config {
+				pins = "gpio16";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se5_spi_cs_active: qupv3_se5_spi_cs_active {
+			mux {
+				pins = "gpio17";
+				function = "qup0_se5_l3";
+			};
+
+			config {
+				pins = "gpio17";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
+			mux {
+				pins = "gpio14", "gpio15",
+					"gpio16", "gpio17";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio14", "gpio15",
+					"gpio16", "gpio17";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
 };
diff --git a/qcom/sa410m-qupv3.dtsi b/qcom/sa410m-qupv3.dtsi
index 9f8fd45c..d96903a1 100644
--- a/qcom/sa410m-qupv3.dtsi
+++ b/qcom/sa410m-qupv3.dtsi
@@ -1,4 +1,30 @@
 &soc {
+	/* GPI Instance */
+	gpi_dma0: qcom,gpi-dma@4a00000 {
+		compatible = "qcom,gpi-dma";
+		#dma-cells = <5>;
+		reg = <0x4a00000 0x60000>;
+		reg-names = "gpi-top";
+		iommus = <&apps_smmu 0xf6 0x0>;
+		qcom,max-num-gpii = <10>;
+		interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,gpii-mask = <0x3ff>;
+		qcom,ev-factor = <2>;
+		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+		qcom,gpi-ee-offset = <0x10000>;
+		dma-coherent;
+		status = "ok";
+	};
+
 	/* QUPv3_0  wrapper  instance */
 	qupv3_0: qcom,qupv3_0_geni_se@4ac0000 {
 		compatible = "qcom,geni-se-qup";
@@ -33,5 +59,243 @@
 			pinctrl-1 = <&qupv3_se4_2uart_sleep>;
 			status = "disabled";
 		};
+
+		qupv3_se0_i2c: i2c@4a80000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x4a80000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se0_i2c_sleep>;
+			dmas = <&gpi_dma0 0 0 3 64 0>,
+				<&gpi_dma0 1 0 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se0_spi: spi@4a80000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x4a80000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>,
+						<&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se0_spi_sleep>;
+			dmas = <&gpi_dma0 0 0 1 64 0>,
+				<&gpi_dma0 1 0 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se0_4uart: qcom,qup_uart@4a80000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0x4a80000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "active", "sleep", "shutdown";
+			pinctrl-0 = <&qupv3_se0_default_cts>, <&qupv3_se0_default_rts>,
+					<&qupv3_se0_default_tx>, <&qupv3_se0_default_rx>;
+			pinctrl-1 = <&qupv3_se0_cts>, <&qupv3_se0_rts>,
+					<&qupv3_se0_tx>, <&qupv3_se0_rx>;
+			pinctrl-2 = <&qupv3_se0_cts>, <&qupv3_se0_rts>,
+					<&qupv3_se0_tx>, <&qupv3_se0_default_rx>;
+			pinctrl-3 = <&qupv3_se0_default_cts>, <&qupv3_se0_default_rts>,
+					<&qupv3_se0_default_tx>, <&qupv3_se0_default_rx>;
+			status = "disabled";
+		};
+
+		qupv3_se1_i2c: i2c@4a84000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x4a84000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se1_i2c_sleep>;
+			dmas = <&gpi_dma0 0 1 3 64 0>,
+				<&gpi_dma0 1 1 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se1_spi: spi@4a84000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x4a84000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>,
+						<&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se1_spi_sleep>;
+			dmas = <&gpi_dma0 0 1 1 64 0>,
+				<&gpi_dma0 1 1 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se2_i2c: i2c@4a88000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x4a88000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se2_i2c_sleep>;
+			dmas = <&gpi_dma0 0 2 3 64 0>,
+				<&gpi_dma0 1 2 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se2_spi: spi@4a88000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x4a88000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>,
+						<&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se2_spi_sleep>;
+			dmas = <&gpi_dma0 0 2 1 64 0>,
+				<&gpi_dma0 1 2 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		/* HS UART Instance */
+		qupv3_se3_4uart: qcom,qup_uart@4a8c000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0x4a8c000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "active", "sleep", "shutdown";
+			pinctrl-0 = <&qupv3_se3_default_cts>, <&qupv3_se3_default_rts>,
+					<&qupv3_se3_default_tx>, <&qupv3_se3_default_rx>;
+			pinctrl-1 = <&qupv3_se3_cts>, <&qupv3_se3_rts>,
+					<&qupv3_se3_tx>, <&qupv3_se3_rx>;
+			pinctrl-2 = <&qupv3_se3_cts>, <&qupv3_se3_rts>,
+					<&qupv3_se3_tx>, <&qupv3_se3_default_rx>;
+			pinctrl-3 = <&qupv3_se3_default_cts>, <&qupv3_se3_default_rts>,
+					<&qupv3_se3_default_tx>, <&qupv3_se3_default_rx>;
+			qcom,wakeup-byte = <0xFD>;
+			status = "disabled";
+		};
+
+		qupv3_se5_i2c: i2c@4a94000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x4a94000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se5_i2c_sleep>;
+			dmas = <&gpi_dma0 0 5 3 64 0>,
+				<&gpi_dma0 1 5 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se5_spi: spi@4a94000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x4a94000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
+			<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>,
+						<&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se5_spi_sleep>;
+			dmas = <&gpi_dma0 0 5 1 64 0>,
+				<&gpi_dma0 1 5 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
 	};
 };