From 680058afe8649589e9895005b276214c8b6e55ed Mon Sep 17 00:00:00 2001 From: Jyothi Kumar Seerapu Date: Fri, 28 Oct 2022 19:23:14 +0530 Subject: [PATCH] ARM: dts: msm: Set QSERDES_COM_SYSCLK_EN to 0x8 for PCIe2 PHY for sdxpinn For PCIe 2 PHY setting of QSERDES_COM_SYSCLK_EN to 0x4 which is internal diff cml clock, PHY is not coming up and hence changed the PCIe 2 PHY setting of QSERDES_COM_SYSCLK_EN to 0x8 which is SE cmos clock. Corrected SLV_Q2A_AXI_CLK clock for PCIe2. Updated reset names of core and phy of PCIe0. Change-Id: Ib227f03e2ddc4c581d538152e54fe036aef29895 --- qcom/sdxpinn-pcie.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/sdxpinn-pcie.dtsi b/qcom/sdxpinn-pcie.dtsi index e1d95457..50fbdcc1 100644 --- a/qcom/sdxpinn-pcie.dtsi +++ b/qcom/sdxpinn-pcie.dtsi @@ -105,8 +105,8 @@ <0>, <0>, <0>, <0>; resets = <&gcc GCC_PCIE_BCR>, <&gcc GCC_PCIE_PHY_BCR>; - reset-names = "pcie_core_reset", - "pcie_phy_reset"; + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; qcom,smmu-sid-base = <0x0800>; iommu-map = <0x0 &apps_smmu 0x0800 0x1>, @@ -648,7 +648,7 @@ <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, <&gcc GCC_PCIE_2_SLV_AXI_CLK>, <&gcc GCC_PCIE_2_CLKREF_EN>, - <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, <&gcc GCC_PCIE_2_PIPE_DIV2_CLK>, <&gcc GCC_PCIE_2_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_2_PIPE_CLK_SRC>, @@ -718,7 +718,7 @@ 0x00e0 0x90 0x0 0x00e4 0x82 0x0 0x00f4 0x07 0x0 - 0x0110 0x04 0x0 + 0x0110 0x08 0x0 0x0120 0x42 0x0 0x0140 0x14 0x0 0x0164 0x34 0x0