diff --git a/qcom/monaco-pinctrl.dtsi b/qcom/monaco-pinctrl.dtsi index 5709e882..d3e2ddec 100644 --- a/qcom/monaco-pinctrl.dtsi +++ b/qcom/monaco-pinctrl.dtsi @@ -10,19 +10,32 @@ wakeup-parent = <&wakegic>; qupv3_se6_2uart_pins: qupv3_se6_2uart_pins { - qupv3_se6_2uart_active: qupv3_se6_2uart_active { + qupv3_se6_2uart_tx_active: qupv3_se6_2uart_tx_active { mux { - pins = "gpio30", "gpio31"; - function = "qup06"; + pins = "gpio30"; + function = "qup0_l2"; }; config { - pins = "gpio30", "gpio31"; + pins = "gpio30"; drive-strength = <2>; bias-disable; }; }; + qupv3_se3_2uart_rx_active: qupv3_se3_2uart_rx_active { + mux { + pins = "gpio31"; + function = "qup0_l3"; + }; + + config { + pins = "gpio31"; + drive-strength= <2>; + bias-disable; + }; + }; + qupv3_se6_2uart_sleep: qupv3_se6_2uart_sleep { mux { pins = "gpio30", "gpio31"; @@ -768,15 +781,27 @@ }; qupv3_se5_4uart_pins: qupv3_se5_4uart_pins { - qupv3_se5_default_ctsrtsrx: - qupv3_se5_default_ctsrtsrx { + qupv3_se5_default_cts: qupv3_se5_default_cts { mux { - pins = "gpio26", "gpio27", "gpio29"; + pins = "gpio26"; function = "gpio"; }; config { - pins = "gpio26", "gpio27", "gpio29"; + pins = "gpio26"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se5_default_rts: qupv3_se5_default_rts { + mux { + pins = "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio27"; drive-strength = <2>; bias-pull-down; }; @@ -795,14 +820,27 @@ }; }; - qupv3_se5_ctsrx: qupv3_se5_ctsrx { + qupv3_se5_default_rx: qupv3_se5_default_rx { mux { - pins = "gpio26", "gpio29"; - function = "qup05"; + pins = "gpio29"; + function = "gpio"; }; config { - pins = "gpio26", "gpio29"; + pins = "gpio29"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se5_cts: qupv3_se5_cts { + mux { + pins = "gpio26"; + function = "qup0_l0"; + }; + + config { + pins = "gpio26"; drive-strength = <2>; bias-disable; }; @@ -811,7 +849,7 @@ qupv3_se5_rts: qupv3_se5_rts { mux { pins = "gpio27"; - function = "qup05"; + function = "qup0_l1"; }; config { @@ -824,7 +862,7 @@ qupv3_se5_tx: qupv3_se5_tx { mux { pins = "gpio28"; - function = "qup05"; + function = "qup0_l2"; }; config { @@ -833,6 +871,19 @@ bias-pull-up; }; }; + + qupv3_se5_rx: qupv3_se5_rx { + mux { + pins = "gpio29"; + function = "qup0_l3"; + }; + + config { + pins = "gpio29"; + drive-strength = <2>; + bias-disable; + }; + }; }; /* WSA speaker reset pin1 */ diff --git a/qcom/monaco-qupv3.dtsi b/qcom/monaco-qupv3.dtsi new file mode 100644 index 00000000..8ae413d2 --- /dev/null +++ b/qcom/monaco-qupv3.dtsi @@ -0,0 +1,65 @@ +&soc { + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x4ac0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0xe3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + ranges; + status = "ok"; + + /* Debug UART Instance */ + qupv3_se6_2uart: qcom,qup_uart@4a98000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x4a98000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_2uart_tx_active>, <&qupv3_se3_2uart_rx_active>; + pinctrl-1 = <&qupv3_se6_2uart_sleep>; + status = "disabled"; + }; + + /* HS UART Instance */ + qupv3_se5_4uart: qcom,qup_uart@4a94000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x4a94000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 29 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>, + <&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>; + pinctrl-1 = <&qupv3_se5_cts>, <&qupv3_se5_rts>, + <&qupv3_se5_tx>, <&qupv3_se5_rx>; + pinctrl-2 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>, + <&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>; + pinctrl-3 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>, + <&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index c6098997..c329b643 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -21,6 +21,8 @@ aliases { sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/ + serial0 = &qupv3_se6_2uart; + hsuart0 = &qupv3_se5_4uart; }; firmware: firmware {}; @@ -1214,6 +1216,7 @@ #include "monaco-regulators.dtsi" #include "monaco-pmic.dtsi" #include "monaco-pinctrl.dtsi" +#include "monaco-qupv3.dtsi" #include "monaco-coresight.dtsi" #include "msm-arm-smmu-monaco.dtsi" #include "monaco-dma-heaps.dtsi" @@ -1274,3 +1277,7 @@ io-channels= <&pm5100_charger PSY_IIO_USB_REAL_TYPE>; io-channel-names = "chg_type"; }; + +&qupv3_se6_2uart { + status = "ok"; +};