From 25bb2adbcb4df1e4f0101064a420ef2e98d52813 Mon Sep 17 00:00:00 2001
From: Elliot Berman <eberman@quicinc.com>
Date: Thu, 12 Aug 2021 21:35:42 -0700
Subject: [PATCH] dt-bindings: Add bindings for LLCC-perfmon

Add bindings to move LLCC-perfmon to its own node.

Change-Id: I19ad3fa6502b04dad072fb13464ceea992fbd0c6
---
 bindings/arm/msm/qcom,llcc.txt | 29 +++++++++++++++++++++++------
 1 file changed, 23 insertions(+), 6 deletions(-)

diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt
index 1218c854..8b9b975c 100644
--- a/bindings/arm/msm/qcom,llcc.txt
+++ b/bindings/arm/msm/qcom,llcc.txt
@@ -35,6 +35,22 @@ Properties:
 	Definition: The interrupt is associated with the llcc edac device.
 			It's used for llcc cache single and double bit error detection
 			and reporting.
+Example:
+
+	cache-controller@1100000 {
+		compatible = "qcom,sdm845-llcc";
+		reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
+		reg-names = "llcc_base", "llcc_broadcast_base";
+		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+LLCC Performance Monitor
+===
+
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: must be "qcom,llcc-perfom"
 
 - clocks:
 	Usage: required
@@ -51,10 +67,11 @@ Properties:
 Example:
 
 	cache-controller@1100000 {
-		compatible = "qcom,sdm845-llcc";
-		reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
-		reg-names = "llcc_base", "llcc_broadcast_base";
-		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clock_aop QDSS_CLK>;
-		clock-names = "qdss_clk";
+		...
+		llcc-perfmon {
+			compatible = "qcom,llcc-perfmon";
+			clocks = <&aoss_qmp QDSS_CLK>;
+			clock-names = "qdss_clk";
+		};
+		...
 	};