From 767f0fbc9b973916564cb2557fadd5230b9ea0f8 Mon Sep 17 00:00:00 2001 From: Shivali M S Date: Thu, 30 Jun 2022 17:18:44 +0530 Subject: [PATCH 1/2] ARM: dts: msm: Add PCIe pipe clock mux and external pipe clock Add PCIe pipe clock mux and external pipe clock to PCIe node. Change-Id: Id86a7a339d32584c3bd6719f27629589c51c97a9 --- qcom/cinder.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi index d8708e8b..957db25d 100644 --- a/qcom/cinder.dtsi +++ b/qcom/cinder.dtsi @@ -1122,12 +1122,16 @@ <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CLKREF_EN>, <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&pcie_0_pipe_clk>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "pcie_pipe_clk", "pcie_cfg_ahb_clk", "pcie_mstr_axi_clk", "pcie_slv_axi_clk", "pcie_aux_clk", "pcie_ldo", "pcie_slv_q2a_axi_clk", + "pcie_pipe_clk_mux", + "pcie_pipe_clk_ext_src", "pcie_0_ref_clk_src"; resets = <&gcc GCC_PCIE_0_BCR>, From 018a22881c4ea3f965db00a8ae5762ddad988327 Mon Sep 17 00:00:00 2001 From: Subramanian Ananthanarayanan Date: Fri, 24 Jun 2022 01:40:29 -0700 Subject: [PATCH 2/2] ARM: dts: msm: Change for CB mapping and common iommu mapping Change for Context Bank sharing with ECPRI and common node for iommu mapping. The changes allow, ECPRI SID's to access MHI mapped buffers. Change-Id: I2ec00fc88c53c9e285b03b674a5799e164b04c0a --- qcom/cinder.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi index 957db25d..18948f90 100644 --- a/qcom/cinder.dtsi +++ b/qcom/cinder.dtsi @@ -1257,6 +1257,10 @@ status = "disabled"; }; + ecpri_iommu_group: ecpri_common_iommu_group { + qcom,iommu-dma = "default"; + }; + mhi_device: mhi_dev@1c04000 { compatible = "qcom,msm-mhi-dev"; reg = <0x1c04000 0x1000>; @@ -1279,6 +1283,19 @@ qcom,mhi-is-flashless; qcom,mhi-has-smmu; + iommus = <&apps_smmu 0x0400 0x0>, + <&apps_smmu 0x0404 0x0>, + <&apps_smmu 0x0408 0x0>, + <&apps_smmu 0x040C 0x0>, + <&apps_smmu 0x0410 0x0>, + <&apps_smmu 0x0414 0x0>, + <&apps_smmu 0x0418 0x0>, + <&apps_smmu 0x041C 0x0>, + <&apps_smmu 0x0802 0x0>, + <&apps_smmu 0x0C02 0x0>; + qcom,iommu-group = <&ecpri_iommu_group>; + dma-coherent; + status = "ok"; };