From 268aba1062ca4f22a9618bab03301d7c95df6cd2 Mon Sep 17 00:00:00 2001 From: Venkata Manasa Kakarla Date: Thu, 3 Feb 2022 17:59:03 +0530 Subject: [PATCH] ARM: dts: msm: Add QUP node entries for SM8150 Add the top QUP and SSC QUP node entries for I2C, SPI, UART and BAM protocol for SM8150 target. Change-Id: I3860c5df2746a6ecf72599fbc4132191e723bf23 --- qcom/sm8150-pinctrl.dtsi | 591 ++++++++++----------- qcom/sm8150-qupv3.dtsi | 1028 ++++++++++++++++++++++++++++++++++++ qcom/sm8150-ssc-qupv3.dtsi | 117 ++++ qcom/sm8150.dtsi | 35 +- 4 files changed, 1425 insertions(+), 346 deletions(-) create mode 100644 qcom/sm8150-qupv3.dtsi create mode 100644 qcom/sm8150-ssc-qupv3.dtsi diff --git a/qcom/sm8150-pinctrl.dtsi b/qcom/sm8150-pinctrl.dtsi index 02a24fcf..d5ed5e8f 100644 --- a/qcom/sm8150-pinctrl.dtsi +++ b/qcom/sm8150-pinctrl.dtsi @@ -112,158 +112,6 @@ }; }; - qupv3_se10_2uart_pins: qupv3_se10_2uart_pins { - qupv3_se10_2uart_active: qupv3_se10_2uart_active { - mux { - pins = "gpio11", "gpio12"; - function = "qup10"; - }; - - config { - pins = "gpio11", "gpio12"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep { - mux { - pins = "gpio11", "gpio12"; - function = "gpio"; - }; - - config { - pins = "gpio11", "gpio12"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - - qupv3_se12_2uart_pins: qupv3_se12_2uart_pins { - qupv3_se12_2uart_active: qupv3_se12_2uart_active { - mux { - pins = "gpio85", "gpio86"; - function = "qup12"; - }; - - config { - pins = "gpio85", "gpio86"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se12_2uart_sleep: qupv3_se12_2uart_sleep { - mux { - pins = "gpio85", "gpio86"; - function = "gpio"; - }; - - config { - pins = "gpio85", "gpio86"; - drive-strength = <2>; - bias-pull-down; - }; - }; - }; - - qupv3_se16_2uart_pins: qupv3_se16_2uart_pins { - qupv3_se16_2uart_active: qupv3_se16_2uart_active { - mux { - pins = "gpio83", "gpio84"; - function = "qup16"; - }; - - config { - pins = "gpio83", "gpio84"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se16_2uart_sleep: qupv3_se16_2uart_sleep { - mux { - pins = "gpio83", "gpio84"; - function = "gpio"; - }; - - config { - pins = "gpio83", "gpio84"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - - qupv3_se13_4uart_pins: qupv3_se13_4uart_pins { - qupv3_se13_default_ctsrtsrx: - qupv3_se13_default_ctsrtsrx { - mux { - pins = "gpio43", "gpio44", "gpio46"; - function = "gpio"; - }; - - config { - pins = "gpio43", "gpio44", "gpio46"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - qupv3_se13_default_tx: qupv3_se13_default_tx { - mux { - pins = "gpio45"; - function = "gpio"; - }; - - config { - pins = "gpio45"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - qupv3_se13_ctsrx: qupv3_se13_ctsrx { - mux { - pins = "gpio43", "gpio46"; - function = "qup13"; - }; - - config { - pins = "gpio43", "gpio46"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se13_rts: qupv3_se13_rts { - mux { - pins = "gpio44"; - function = "qup13"; - }; - - config { - pins = "gpio44"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - qupv3_se13_tx: qupv3_se13_tx { - mux { - pins = "gpio45"; - function = "qup13"; - }; - - config { - pins = "gpio45"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - pmx_ts_active { ts_active: ts_active { mux { @@ -835,47 +683,6 @@ }; }; - qupv3_se4_2uart_pins: qupv3_se4_2uart_pins { - qupv3_se4_2uart_default: qupv3_se4_2uart_default { - mux { - pins = "gpio41", "gpio42"; - function = "gpio"; - }; - - config { - pins = "gpio41", "gpio42"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se4_2uart_active: qupv3_se4_2uart_active { - mux { - pins = "gpio41", "gpio42"; - function = "qup9"; - }; - - config { - pins = "gpio41", "gpio42"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep { - mux { - pins = "gpio41", "gpio42"; - function = "gpio"; - }; - - config { - pins = "gpio41", "gpio42"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - /* SE 5 pin mappings */ qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { qupv3_se5_i2c_active: qupv3_se5_i2c_active { @@ -1150,6 +957,79 @@ }; }; + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_active: qupv3_se9_spi_active { + mux { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + function = "qup9"; + }; + + config { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se9_2uart_pins: qupv3_se9_2uart_pins { + qupv3_se9_2uart_default: qupv3_se9_2uart_default { + mux { + pins = "gpio41", "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio41", "gpio42"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se9_2uart_active: qupv3_se9_2uart_active { + mux { + pins = "gpio41", "gpio42"; + function = "qup9"; + }; + + config { + pins = "gpio41", "gpio42"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se9_2uart_sleep: qupv3_se9_2uart_sleep { + mux { + pins = "gpio41", "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio41", "gpio42"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + nfc { nfc_int_active: nfc_int_active { /* active state */ @@ -1242,38 +1122,6 @@ }; }; - qupv3_se9_spi_pins: qupv3_se9_spi_pins { - qupv3_se9_spi_active: qupv3_se9_spi_active { - mux { - pins = "gpio39", "gpio40", "gpio41", - "gpio42"; - function = "qup9"; - }; - - config { - pins = "gpio39", "gpio40", "gpio41", - "gpio42"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { - mux { - pins = "gpio39", "gpio40", "gpio41", - "gpio42"; - function = "gpio"; - }; - - config { - pins = "gpio39", "gpio40", "gpio41", - "gpio42"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - /* SE 10 pin mappings */ qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { qupv3_se10_i2c_active: qupv3_se10_i2c_active { @@ -1457,16 +1305,44 @@ }; }; + qupv3_se12_2uart_pins: qupv3_se12_2uart_pins { + qupv3_se12_2uart_active: qupv3_se12_2uart_active { + mux { + pins = "gpio85", "gpio86"; + function = "qup12"; + }; + + config { + pins = "gpio85", "gpio86"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se12_2uart_sleep: qupv3_se12_2uart_sleep { + mux { + pins = "gpio85", "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio85", "gpio86"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + /* SE 13 pin mappings */ qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { qupv3_se13_i2c_active: qupv3_se13_i2c_active { mux { - pins = "gpio43", "gpio44"; - function = "qup13"; + pins = "gpio86", "gpio85"; + function = "qup16"; }; config { - pins = "gpio43", "gpio44"; + pins = "gpio86", "gpio85"; drive-strength = <2>; bias-disable; }; @@ -1474,12 +1350,12 @@ qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { mux { - pins = "gpio43", "gpio44"; + pins = "gpio86", "gpio85"; function = "gpio"; }; config { - pins = "gpio43", "gpio44"; + pins = "gpio86", "gpio85"; drive-strength = <2>; bias-pull-up; }; @@ -1489,14 +1365,14 @@ qupv3_se13_spi_pins: qupv3_se13_spi_pins { qupv3_se13_spi_active: qupv3_se13_spi_active { mux { - pins = "gpio43", "gpio44", "gpio45", - "gpio46"; - function = "qup13"; + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "qup16"; }; config { - pins = "gpio43", "gpio44", "gpio45", - "gpio46"; + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; drive-strength = <6>; bias-disable; }; @@ -1504,31 +1380,30 @@ qupv3_se13_spi_sleep: qupv3_se13_spi_sleep { mux { - pins = "gpio43", "gpio44", "gpio45", - "gpio46"; + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; function = "gpio"; }; config { - pins = "gpio43", "gpio44", "gpio45", - "gpio46"; + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; drive-strength = <6>; bias-disable; }; }; }; - /* SE 14 pin mappings */ qupv3_se14_i2c_pins: qupv3_se14_i2c_pins { qupv3_se14_i2c_active: qupv3_se14_i2c_active { mux { - pins = "gpio47", "gpio48"; - function = "qup14"; + pins = "gpio55", "gpio56"; + function = "qup17"; }; config { - pins = "gpio47", "gpio48"; + pins = "gpio55", "gpio56"; drive-strength = <2>; bias-disable; }; @@ -1536,12 +1411,12 @@ qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep { mux { - pins = "gpio47", "gpio48"; + pins = "gpio55", "gpio56"; function = "gpio"; }; config { - pins = "gpio47", "gpio48"; + pins = "gpio55", "gpio56"; drive-strength = <2>; bias-pull-up; }; @@ -1551,14 +1426,14 @@ qupv3_se14_spi_pins: qupv3_se14_spi_pins { qupv3_se14_spi_active: qupv3_se14_spi_active { mux { - pins = "gpio47", "gpio48", "gpio49", - "gpio50"; - function = "qup14"; + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + function = "qup17"; }; config { - pins = "gpio47", "gpio48", "gpio49", - "gpio50"; + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; drive-strength = <6>; bias-disable; }; @@ -1566,14 +1441,14 @@ qupv3_se14_spi_sleep: qupv3_se14_spi_sleep { mux { - pins = "gpio47", "gpio48", "gpio49", - "gpio50"; + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; function = "gpio"; }; config { - pins = "gpio47", "gpio48", "gpio49", - "gpio50"; + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; drive-strength = <6>; bias-disable; }; @@ -1584,12 +1459,12 @@ qupv3_se15_i2c_pins: qupv3_se15_i2c_pins { qupv3_se15_i2c_active: qupv3_se15_i2c_active { mux { - pins = "gpio27", "gpio28"; - function = "qup15"; + pins = "gpio23", "gpio24"; + function = "qup18"; }; config { - pins = "gpio27", "gpio28"; + pins = "gpio23", "gpio24"; drive-strength = <2>; bias-disable; }; @@ -1597,12 +1472,12 @@ qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep { mux { - pins = "gpio27", "gpio28"; + pins = "gpio23", "gpio24"; function = "gpio"; }; config { - pins = "gpio27", "gpio28"; + pins = "gpio23", "gpio24"; drive-strength = <2>; bias-pull-up; }; @@ -1612,14 +1487,14 @@ qupv3_se15_spi_pins: qupv3_se15_spi_pins { qupv3_se15_spi_active: qupv3_se15_spi_active { mux { - pins = "gpio27", "gpio28", "gpio29", - "gpio30"; - function = "qup15"; + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + function = "qup18"; }; config { - pins = "gpio27", "gpio28", "gpio29", - "gpio30"; + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; drive-strength = <6>; bias-disable; }; @@ -1627,14 +1502,14 @@ qupv3_se15_spi_sleep: qupv3_se15_spi_sleep { mux { - pins = "gpio27", "gpio28", "gpio29", - "gpio30"; + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; function = "gpio"; }; config { - pins = "gpio27", "gpio28", "gpio29", - "gpio30"; + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; drive-strength = <6>; bias-disable; }; @@ -1645,12 +1520,12 @@ qupv3_se16_i2c_pins: qupv3_se16_i2c_pins { qupv3_se16_i2c_active: qupv3_se16_i2c_active { mux { - pins = "gpio86", "gpio85"; - function = "qup16"; + pins = "gpio57", "gpio58"; + function = "qup19"; }; config { - pins = "gpio86", "gpio85"; + pins = "gpio57", "gpio58"; drive-strength = <2>; bias-disable; }; @@ -1658,12 +1533,12 @@ qupv3_se16_i2c_sleep: qupv3_se16_i2c_sleep { mux { - pins = "gpio86", "gpio85"; + pins = "gpio57", "gpio58"; function = "gpio"; }; config { - pins = "gpio86", "gpio85"; + pins = "gpio57", "gpio58"; drive-strength = <2>; bias-pull-up; }; @@ -1673,14 +1548,14 @@ qupv3_se16_spi_pins: qupv3_se16_spi_pins { qupv3_se16_spi_active: qupv3_se16_spi_active { mux { - pins = "gpio83", "gpio84", "gpio85", - "gpio86"; - function = "qup16"; + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + function = "qup19"; }; config { - pins = "gpio83", "gpio84", "gpio85", - "gpio86"; + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; drive-strength = <6>; bias-disable; }; @@ -1688,14 +1563,14 @@ qupv3_se16_spi_sleep: qupv3_se16_spi_sleep { mux { - pins = "gpio83", "gpio84", "gpio85", - "gpio86"; + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; function = "gpio"; }; config { - pins = "gpio83", "gpio84", "gpio85", - "gpio86"; + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; drive-strength = <6>; bias-disable; }; @@ -1706,12 +1581,12 @@ qupv3_se17_i2c_pins: qupv3_se17_i2c_pins { qupv3_se17_i2c_active: qupv3_se17_i2c_active { mux { - pins = "gpio55", "gpio56"; - function = "qup17"; + pins = "gpio43", "gpio44"; + function = "qup13"; }; config { - pins = "gpio55", "gpio56"; + pins = "gpio43", "gpio44"; drive-strength = <2>; bias-disable; }; @@ -1719,12 +1594,12 @@ qupv3_se17_i2c_sleep: qupv3_se17_i2c_sleep { mux { - pins = "gpio55", "gpio56"; + pins = "gpio43", "gpio44"; function = "gpio"; }; config { - pins = "gpio55", "gpio56"; + pins = "gpio43", "gpio44"; drive-strength = <2>; bias-pull-up; }; @@ -1734,14 +1609,14 @@ qupv3_se17_spi_pins: qupv3_se17_spi_pins { qupv3_se17_spi_active: qupv3_se17_spi_active { mux { - pins = "gpio55", "gpio56", "gpio57", - "gpio58"; - function = "qup17"; + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + function = "qup13"; }; config { - pins = "gpio55", "gpio56", "gpio57", - "gpio58"; + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; drive-strength = <6>; bias-disable; }; @@ -1749,30 +1624,98 @@ qupv3_se17_spi_sleep: qupv3_se17_spi_sleep { mux { - pins = "gpio55", "gpio56", "gpio57", - "gpio58"; + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; function = "gpio"; }; config { - pins = "gpio55", "gpio56", "gpio57", - "gpio58"; + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; drive-strength = <6>; bias-disable; }; }; }; + qupv3_se17_4uart_pins: qupv3_se17_4uart_pins { + qupv3_se17_default_ctsrtsrx: + qupv3_se17_default_ctsrtsrx { + mux { + pins = "gpio43", "gpio44", "gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio43", "gpio44", "gpio46"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se17_default_tx: qupv3_se17_default_tx { + mux { + pins = "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio45"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se17_ctsrx: qupv3_se17_ctsrx { + mux { + pins = "gpio43", "gpio46"; + function = "qup13"; + }; + + config { + pins = "gpio43", "gpio46"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se17_rts: qupv3_se17_rts { + mux { + pins = "gpio44"; + function = "qup13"; + }; + + config { + pins = "gpio44"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se17_tx: qupv3_se17_tx { + mux { + pins = "gpio45"; + function = "qup13"; + }; + + config { + pins = "gpio45"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + /* SE 18 pin mappings */ qupv3_se18_i2c_pins: qupv3_se18_i2c_pins { qupv3_se18_i2c_active: qupv3_se18_i2c_active { mux { - pins = "gpio23", "gpio24"; - function = "qup18"; + pins = "gpio47", "gpio48"; + function = "qup14"; }; config { - pins = "gpio23", "gpio24"; + pins = "gpio47", "gpio48"; drive-strength = <2>; bias-disable; }; @@ -1780,12 +1723,12 @@ qupv3_se18_i2c_sleep: qupv3_se18_i2c_sleep { mux { - pins = "gpio23", "gpio24"; + pins = "gpio47", "gpio48"; function = "gpio"; }; config { - pins = "gpio23", "gpio24"; + pins = "gpio47", "gpio48"; drive-strength = <2>; bias-pull-up; }; @@ -1795,14 +1738,14 @@ qupv3_se18_spi_pins: qupv3_se18_spi_pins { qupv3_se18_spi_active: qupv3_se18_spi_active { mux { - pins = "gpio23", "gpio24", "gpio25", - "gpio26"; - function = "qup18"; + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + function = "qup14"; }; config { - pins = "gpio23", "gpio24", "gpio25", - "gpio26"; + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; drive-strength = <6>; bias-disable; }; @@ -1810,14 +1753,14 @@ qupv3_se18_spi_sleep: qupv3_se18_spi_sleep { mux { - pins = "gpio23", "gpio24", "gpio25", - "gpio26"; + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; function = "gpio"; }; config { - pins = "gpio23", "gpio24", "gpio25", - "gpio26"; + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; drive-strength = <6>; bias-disable; }; @@ -1828,12 +1771,12 @@ qupv3_se19_i2c_pins: qupv3_se19_i2c_pins { qupv3_se19_i2c_active: qupv3_se19_i2c_active { mux { - pins = "gpio57", "gpio58"; - function = "qup19"; + pins = "gpio27", "gpio28"; + function = "qup15"; }; config { - pins = "gpio57", "gpio58"; + pins = "gpio27", "gpio28"; drive-strength = <2>; bias-disable; }; @@ -1841,12 +1784,12 @@ qupv3_se19_i2c_sleep: qupv3_se19_i2c_sleep { mux { - pins = "gpio57", "gpio58"; + pins = "gpio27", "gpio28"; function = "gpio"; }; config { - pins = "gpio57", "gpio58"; + pins = "gpio27", "gpio28"; drive-strength = <2>; bias-pull-up; }; @@ -1856,14 +1799,14 @@ qupv3_se19_spi_pins: qupv3_se19_spi_pins { qupv3_se19_spi_active: qupv3_se19_spi_active { mux { - pins = "gpio55", "gpio56", "gpio57", - "gpio58"; - function = "qup19"; + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + function = "qup15"; }; config { - pins = "gpio55", "gpio56", "gpio57", - "gpio58"; + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; drive-strength = <6>; bias-disable; }; @@ -1871,14 +1814,14 @@ qupv3_se19_spi_sleep: qupv3_se19_spi_sleep { mux { - pins = "gpio55", "gpio56", "gpio57", - "gpio58"; + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; function = "gpio"; }; config { - pins = "gpio55", "gpio56", "gpio57", - "gpio58"; + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; drive-strength = <6>; bias-disable; }; diff --git a/qcom/sm8150-qupv3.dtsi b/qcom/sm8150-qupv3.dtsi new file mode 100644 index 00000000..a6fff743 --- /dev/null +++ b/qcom/sm8150-qupv3.dtsi @@ -0,0 +1,1028 @@ +&soc { + /* QUPv3 SE Instances + * Qup0 0: SE 0 + * Qup0 1: SE 1 + * Qup0 2: SE 2 + * Qup0 3: SE 3 + * Qup0 4: SE 4 + * Qup0 5: SE 5 + * Qup0 6: SE 6 + * Qup0 7: SE 7 + * Qup1 0: SE 8 + * Qup1 1: SE 9 + * Qup1 2: SE 10 + * Qup1 3: SE 11 + * Qup1 4: SE 12 + * Qup1 5: SE 13 + * Qup2 0: SE 14 + * Qup2 1: SE 15 + * Qup2 2: SE 16 + * Qup2 3: SE 17 + * Qup2 4: SE 18 + * Qup2 5: SE 19 + */ + + /* GPI Instance */ + gpi_dma0: qcom,gpi-dma@800000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x800000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0xd6 0x0>; + qcom,max-num-gpii = <13>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0xfa>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + dma-coherent; + status = "disabled"; + }; + + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x8c0000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0xc3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + + qupv3_se0_i2c: i2c@880000 { + compatible = "qcom,i2c-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se0_spi: spi@880000 { + compatible = "qcom,spi-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se1_spi: spi@884000 { + compatible = "qcom,spi-geni"; + reg = <0x884000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se2_spi: spi@888000 { + compatible = "qcom,spi-geni"; + reg = <0x888000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se3_spi: spi@88c000 { + compatible = "qcom,spi-geni"; + reg = <0x88c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@890000 { + compatible = "qcom,i2c-geni"; + reg = <0x890000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se4_spi: spi@890000 { + compatible = "qcom,spi-geni"; + reg = <0x890000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@894000 { + compatible = "qcom,i2c-geni"; + reg = <0x894000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se5_spi: spi@894000 { + compatible = "qcom,spi-geni"; + reg = <0x894000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@898000 { + compatible = "qcom,i2c-geni"; + reg = <0x898000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se6_spi: spi@898000 { + compatible = "qcom,spi-geni"; + reg = <0x898000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@89c000 { + compatible = "qcom,i2c-geni"; + reg = <0x89c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se7_spi: spi@89c000 { + compatible = "qcom,spi-geni"; + reg = <0x89c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + }; + + /* GPI Instance */ + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x616 0x0>; + qcom,max-num-gpii = <13>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0xfa>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + dma-coherent; + status = "ok"; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x603 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + + /* Debug UART Instance */ + qupv3_se12_2uart: qcom,qup_uart@a90000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa90000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_2uart_active>; + pinctrl-1 = <&qupv3_se12_2uart_sleep>; + status = "disabled"; + }; + + qupv3_se8_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se8_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_active>; + pinctrl-1 = <&qupv3_se8_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se9_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* GNSS UART Instance */ + qupv3_se9_2uart: qcom,qup_uart@a84000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa84000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + dmas = <&gpi_dma1 0 1 2 64 0>, + <&gpi_dma1 1 1 2 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se9_2uart_default>; + pinctrl-1 = <&qupv3_se9_2uart_active>; + pinctrl-2 = <&qupv3_se9_2uart_sleep>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se10_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se11_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_spi_active>; + pinctrl-1 = <&qupv3_se11_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se12_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_spi_active>; + pinctrl-1 = <&qupv3_se12_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se13_i2c: i2c@a94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_i2c_active>; + pinctrl-1 = <&qupv3_se13_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se13_spi: spi@a94000 { + compatible = "qcom,spi-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_spi_active>; + pinctrl-1 = <&qupv3_se13_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + }; + + /* GPI Instance */ + gpi_dma2: qcom,gpi-dma@c00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xc00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x7b6 0x0>; + qcom,max-num-gpii = <13>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0xfa>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + dma-coherent; + status = "disabled"; + }; + + /* QUPv3_2 wrapper instance */ + qupv3_2: qcom,qupv3_2_geni_se@cc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xcc0000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x7a3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + + qupv3_se14_i2c: i2c@c80000 { + compatible = "qcom,i2c-geni"; + reg = <0xc80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_i2c_active>; + pinctrl-1 = <&qupv3_se14_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se14_spi: spi@c80000 { + compatible = "qcom,spi-geni"; + reg = <0xc80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_spi_active>; + pinctrl-1 = <&qupv3_se14_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se15_i2c: i2c@c84000 { + compatible = "qcom,i2c-geni"; + reg = <0xc84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_i2c_active>; + pinctrl-1 = <&qupv3_se15_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se15_spi: spi@c84000 { + compatible = "qcom,spi-geni"; + reg = <0xc84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_spi_active>; + pinctrl-1 = <&qupv3_se15_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se16_i2c: i2c@c88000 { + compatible = "qcom,i2c-geni"; + reg = <0xc88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_i2c_active>; + pinctrl-1 = <&qupv3_se16_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se16_spi: spi@c88000 { + compatible = "qcom,spi-geni"; + reg = <0xc88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_spi_active>; + pinctrl-1 = <&qupv3_se16_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se17_i2c: i2c@c8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xc8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_i2c_active>; + pinctrl-1 = <&qupv3_se17_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se17_spi: spi@c8c000 { + compatible = "qcom,spi-geni"; + reg = <0xc8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_spi_active>; + pinctrl-1 = <&qupv3_se17_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* HS UART Instance */ + qupv3_se17_4uart: qcom,qup_uart@c8c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xc8c000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 46 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se17_default_ctsrtsrx>, + <&qupv3_se17_default_tx>; + pinctrl-1 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>, + <&qupv3_se17_tx>; + pinctrl-2 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>, + <&qupv3_se17_tx>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + qupv3_se18_i2c: i2c@c90000 { + compatible = "qcom,i2c-geni"; + reg = <0xc90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_i2c_active>; + pinctrl-1 = <&qupv3_se18_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se18_spi: spi@c90000 { + compatible = "qcom,spi-geni"; + reg = <0xc90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_spi_active>; + pinctrl-1 = <&qupv3_se18_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se19_i2c: i2c@c94000 { + compatible = "qcom,i2c-geni"; + reg = <0xc94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_i2c_active>; + pinctrl-1 = <&qupv3_se19_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se19_spi: spi@c94000 { + compatible = "qcom,spi-geni"; + reg = <0xc94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_spi_active>; + pinctrl-1 = <&qupv3_se19_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/sm8150-ssc-qupv3.dtsi b/qcom/sm8150-ssc-qupv3.dtsi new file mode 100644 index 00000000..81d8698e --- /dev/null +++ b/qcom/sm8150-ssc-qupv3.dtsi @@ -0,0 +1,117 @@ +&soc { + /* QUPv3_3 wrapper instance */ + qupv3_3: qcom,qupv3_3_geni_se@26c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x26c0000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + iommus = <&apps_smmu 0x4e3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + + qupv3_se20_i2c: i2c@2680000 { + compatible = "qcom,i2c-geni"; + reg = <0x2680000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&scc SCC_QUPV3_SE0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se20_i2c_active>; + pinctrl-1 = <&qupv3_se20_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se21_i2c: i2c@2684000 { + compatible = "qcom,i2c-geni"; + reg = <0x2684000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&scc SCC_QUPV3_SE1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_i2c_active>; + pinctrl-1 = <&qupv3_se21_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se21_spi: spi@2684000 { + compatible = "qcom,spi-geni"; + reg = <0x2684000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&scc SCC_QUPV3_SE1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_spi_active>; + pinctrl-1 = <&qupv3_se21_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se22_i2c: i2c@2688000 { + compatible = "qcom,i2c-geni"; + reg = <0x2688000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&scc SCC_QUPV3_SE2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se22_i2c_active>; + pinctrl-1 = <&qupv3_se22_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se22_spi: spi@2688000 { + compatible = "qcom,spi-geni"; + reg = <0x2688000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&scc SCC_QUPV3_SE2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se22_spi_active>; + pinctrl-1 = <&qupv3_se22_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index f0949715..90da4c9c 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -25,9 +25,11 @@ memory { device_type = "memory"; reg = <0 0 0 0>; }; aliases { - serial0 = &uart2; pci-domain0 = &pcie0; /* PCIe0 domain */ pci-domain1 = &pcie1; /* PCIe1 domain */ + serial0 = &qupv3_se12_2uart; + hsuart0 = &qupv3_se17_4uart; + hsuart1 = &qupv3_se9_2uart; }; cpus { @@ -956,27 +958,6 @@ qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; }; - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0xac0000 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - status = "ok"; - - uart2: serial@a90000 { - compatible = "qcom,geni-debug-uart"; - reg = <0x00a90000 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - interrupts = ; - status = "ok"; - }; - }; - apcs: syscon@17c0000c { compatible = "syscon"; reg = <0x17c0000c 0x4>; @@ -1096,6 +1077,11 @@ interrupts = ; }; + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + qcom,mem-buf { compatible = "qcom,mem-buf"; qcom,mem-buf-capabilities = "supplier"; @@ -1381,4 +1367,9 @@ }; #include "sm8150-pcie.dtsi" +#include "sm8150-qupv3.dtsi" +#include "sm8150-ssc-qupv3.dtsi" +&qupv3_se12_2uart { + status = "ok"; +};