diff --git a/qcom/kalama-pinctrl.dtsi b/qcom/kalama-pinctrl.dtsi
index fe71a5f3..bce67177 100644
--- a/qcom/kalama-pinctrl.dtsi
+++ b/qcom/kalama-pinctrl.dtsi
@@ -26,4 +26,56 @@
 			};
 		};
 	};
+
+	sdc2_on: sdc2_on {
+		clk {
+			pins = "sdc2_clk";
+			bias-disable;
+			drive-strength = <16>;
+		};
+
+		cmd {
+			pins = "sdc2_cmd";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		data {
+			pins = "sdc2_data";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		sd-cd {
+			pins = "gpio92";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+	};
+
+	sdc2_off: sdc2_off {
+		clk {
+			pins = "sdc2_clk";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+		cmd {
+			pins = "sdc2_cmd";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		data {
+			pins = "sdc2_data";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		sd-cd {
+			pins = "gpio92";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+	};
 };
diff --git a/qcom/kalama-rumi.dtsi b/qcom/kalama-rumi.dtsi
index 878298f2..ee33cbe0 100644
--- a/qcom/kalama-rumi.dtsi
+++ b/qcom/kalama-rumi.dtsi
@@ -1,3 +1,5 @@
+#include <dt-bindings/gpio/gpio.h>
+
 &chosen {
 };
 
@@ -39,6 +41,26 @@
 	};
 };
 
+&sdhc_2 {
+	status = "ok";
+	vdd-supply = <&pm_humu_l9>;
+	qcom,vdd-voltage-level = <2950000 2960000>;
+	qcom,vdd-current-level = <200 800000>;
+
+	vdd-io-supply = <&pm_humu_l8>;
+	qcom,vdd-io-voltage-level = <1800000 1800000>;
+	qcom,vdd-io-current-level = <200 5600>;
+
+	cap-sd-highspeed;
+	max-frequency = <50000000>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_on>;
+	pinctrl-1 = <&sdc2_off>;
+
+	cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
+};
+
 &ufsphy_mem {
 	compatible = "qcom,ufs-phy-qrbtc-sdm845";
 
diff --git a/qcom/kalama.dtsi b/qcom/kalama.dtsi
index 97586ec6..3f858e2c 100644
--- a/qcom/kalama.dtsi
+++ b/qcom/kalama.dtsi
@@ -27,6 +27,7 @@
 
 	aliases {
 		serial0 = &qupv3_se7_2uart;
+		sdhc2 = &sdhc_2;
 		ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
 	};
 
@@ -800,6 +801,32 @@
 		regulator-name = "video_cc_mvs1c_gdsc";
 	};
 
+	sdhc_2: sdhci@8804000 {
+		status = "disabled";
+
+		compatible = "qcom,sdhci-msm-v5";
+		reg = <0x08804000 0x1000>;
+		reg-names = "hc_mem";
+
+		interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hc_irq", "pwr_irq";
+
+		bus-width = <4>;
+		no-sdio;
+		no-mmc;
+		qcom,restore-after-cx-collapse;
+
+		clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+			<&gcc GCC_SDCC2_APPS_CLK>;
+		clock-names = "iface", "core";
+
+		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+		qcom,dll-hsr-list = <0x0007642C 0xA800 0x10
+					0x2C010800 0x80040868>;
+
+	};
+
 	ufsphy_mem: ufsphy_mem@1d80000 {
 		reg = <0x1d80000 0x1934>;
 		reg-names = "phy_mem";