From 2d88f449591f3c93de8f2cc8035a3545f9b8dd09 Mon Sep 17 00:00:00 2001
From: LADI RAM SAI <lramsai@qti.qualcomm.com>
Date: Tue, 22 Nov 2022 15:09:07 +0530
Subject: [PATCH] ARM: dts: qcom: Remove delay in phy-init-seq of USB1 SS-PHY

Remove delay in qmp-phy-init-seq of USB1 ssphy for auto sa8155 vm.

Change-Id: I849e444c5e70070ed690cd5e26f7295e82bc1c26
---
 qcom/sa8155-vm-usb.dtsi | 199 ++++++++++++++++++++--------------------
 1 file changed, 99 insertions(+), 100 deletions(-)

diff --git a/qcom/sa8155-vm-usb.dtsi b/qcom/sa8155-vm-usb.dtsi
index 63e5cef5..056154e0 100644
--- a/qcom/sa8155-vm-usb.dtsi
+++ b/qcom/sa8155-vm-usb.dtsi
@@ -184,106 +184,105 @@
 		qcom,vdd-max-load-uA = <47000>;
 		core-supply = <&L8C>;
 		qcom,qmp-phy-init-seq =
-			/* <reg_offset, value, delay> */
-			<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1a 0
-			USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
-			USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0
-			USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0
-			USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab 0
-			USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea 0
-			USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
-			USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca 0
-			USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e 0
-			USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x02 0
-			USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
-			USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
-			USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
-			USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
-			USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
-			USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0
-			USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0
-			USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
-			USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
-			USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
-			USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0
-			USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab 0
-			USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea 0
-			USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
-			USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
-			USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
-			USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0
-			USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
-			USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
-			USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0
-			USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0
-			USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0
-			USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0
-			USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0
-			USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde 0
-			USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
-			USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde 0
-			USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
-			USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0
-			USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0
-			USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xa4 0
-			USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7f 0
-			USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x37 0
-			USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x2f 0
-			USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xaf 0
-			USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb6 0
-			USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b 0
-			USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c 0
-			USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc 0
-			USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc 0
-			USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0X99 0
-			USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04 0
-			USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0
-			USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05 0
-			USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05 0
-			USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2f 0
-			USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0
-			USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0
-			USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0
-			USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0a 0
-			USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0
-			USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x00 0
-			USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0
-			USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f 0
-			USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a 0
-			USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a 0
-			USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x04 0
-			USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
-			USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0
-			USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0
-			USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e 0
-			USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00 0
-			USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0
-			USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x20 0
-			USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06 0
-			USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0
-			USB3_UNI_QSERDES_TX_LANE_MODE_1 0x95 0
-			USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40 0
-			USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0xe4 0
-			USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0xd0 0
-			USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 0
-			USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0
-			USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0 0
-			USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0
-			USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0
-			USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0
-			USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0
-			USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
-			USB3_UNI_PCS_RX_SIGDET_LVL 0xaa 0
-			USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
-			USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0
-			USB3_UNI_PCS_CDR_RESET_TIME 0x0a 0
-			USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0
-			USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0
-			USB3_UNI_PCS_EQ_CONFIG1 0x4b 0
-			USB3_UNI_PCS_EQ_CONFIG5 0x10 0
-			USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0
-			USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c 0
-			0xffffffff 0xffffffff 0x00>;
+			/* <reg_offset, valuey> */
+			<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1a
+			USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11
+			USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01
+			USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82
+			USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab
+			USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea
+			USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
+			USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca
+			USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e
+			USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x02
+			USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16
+			USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36
+			USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24
+			USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34
+			USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14
+			USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04
+			USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a
+			USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02
+			USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24
+			USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08
+			USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82
+			USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab
+			USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea
+			USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
+			USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82
+			USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34
+			USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06
+			USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16
+			USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36
+			USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca
+			USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e
+			USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01
+			USB3_UNI_QSERDES_COM_SSC_PER1 0x31
+			USB3_UNI_QSERDES_COM_SSC_PER2 0x01
+			USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde
+			USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07
+			USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde
+			USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07
+			USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02
+			USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20
+			USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xa4
+			USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7f
+			USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x37
+			USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x2f
+			USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xaf
+			USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb6
+			USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b
+			USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c
+			USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc
+			USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc
+			USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99
+			USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04
+			USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08
+			USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05
+			USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05
+			USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2f
+			USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff
+			USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f
+			USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f
+			USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0a
+			USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54
+			USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x00
+			USB3_UNI_QSERDES_RX_GM_CAL 0x1f
+			USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f
+			USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a
+			USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a
+			USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x04
+			USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
+			USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80
+			USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04
+			USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e
+			USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00
+			USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0
+			USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x20
+			USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06
+			USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12
+			USB3_UNI_QSERDES_TX_LANE_MODE_1 0x95
+			USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40
+			USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0xe4
+			USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0xd0
+			USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10
+			USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c
+			USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0
+			USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07
+			USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20
+			USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13
+			USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7
+			USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
+			USB3_UNI_PCS_RX_SIGDET_LVL 0xaa
+			USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
+			USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8
+			USB3_UNI_PCS_CDR_RESET_TIME 0x0a
+			USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88
+			USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13
+			USB3_UNI_PCS_EQ_CONFIG1 0x4b
+			USB3_UNI_PCS_EQ_CONFIG5 0x10
+			USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21
+			USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c>;
 
 		qcom,qmp-phy-reg-offset =
 				<USB3_UNI_PCS_PCS_STATUS1