From 5ceaf3445545db8cc2ff4d98066c47a050ceda90 Mon Sep 17 00:00:00 2001 From: Bhaumik Bhatt Date: Mon, 24 Jan 2022 23:57:31 -0800 Subject: [PATCH 1/2] ARM: dts: msm: Add initial device trees for cinder emulation target Add pcie ep platform driver device tree entries to support cinder emulation target. Change-Id: I8fa193d6153ff6162dfeecf93476d3e043fa3bac --- qcom/cinder-pinctrl.dtsi | 41 ++++++++++++++++++++++ qcom/cinder-rumi.dtsi | 16 +++++++++ qcom/cinder.dtsi | 75 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 132 insertions(+) diff --git a/qcom/cinder-pinctrl.dtsi b/qcom/cinder-pinctrl.dtsi index 02c402dc..4ad6235f 100644 --- a/qcom/cinder-pinctrl.dtsi +++ b/qcom/cinder-pinctrl.dtsi @@ -76,4 +76,45 @@ bias-pull-down; }; }; + + pcie_ep { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio99"; + function = "pcie_clkreq"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; + bias-disable; + }; + }; + }; }; diff --git a/qcom/cinder-rumi.dtsi b/qcom/cinder-rumi.dtsi index 7f76faf9..0aaa9d7b 100644 --- a/qcom/cinder-rumi.dtsi +++ b/qcom/cinder-rumi.dtsi @@ -11,6 +11,22 @@ }; &soc { + pcie_ep: qcom,pcie@48020000 { + compatible = "qcom,pcie-ep"; + reg = <0x48020000 0x10000>, + <0x48000000 0xf20>, + <0x48000f40 0xa8>, + <0x48010000 0x10000>, + <0x01c00000 0x4000>, + <0x01c10000 0x10000>, + <0x01c04000 0x1000>, + <0x01c09054 0x4>; + reg-names = "msi", "dm_core", "elbi", "iatu", + "parf", "phy", "mmio", "rumi"; + + qcom,pcie-link-speed = <1>; + qcom,tcsr-not-supported; + }; }; diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi index 4daf977e..bf892e4b 100644 --- a/qcom/cinder.dtsi +++ b/qcom/cinder.dtsi @@ -500,6 +500,81 @@ ; }; + pcie_ep: qcom,pcie@48020000 { + compatible = "qcom,pcie-ep"; + reg = <0x48020000 0x10000>, + <0x48000000 0xf20>, + <0x48000f40 0xa8>, + <0x48010000 0x10000>, + <0x48002000 0x1400>, + <0x48004000 0x1000>, + <0x01c00000 0x4000>, + <0x01c10000 0x10000>, + <0x01c04000 0x1000>, + <0x01fcb000 0x1000>, + <0xc2f1000 0x4>; + reg-names = "msi", "dm_core", "elbi", "iatu", + "msix_table", "msix_pba", "parf", + "phy", "mmio", "tcsr_pcie_perst_en", + "aoss_cc_reset"; + + #address-cells = <0>; + interrupt-parent = <&pcie_ep>; + interrupts = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 172 0>; + interrupt-names = "int_global"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; + clkreq-gpio = <&tlmm 99 0>; + perst-gpio = <&tlmm 98 0>; + wake-gpio = <&tlmm 100 0>; + + gdsc-vdd-supply = <&gcc_pcie_0_gdsc>; + vreg-1p8-supply = <&pm8150_a_l3>; + vreg-0p9-supply = <&pm8150_a_l6>; + vreg-mx-supply = <&VDD_MX_LEVEL>; + qcom,vreg-1p8-voltage-level = <1200000 1200000 30000>; + qcom,vreg-0p9-voltage-level = <912000 912000 132000>; + qcom,vreg-mx-voltage-level = ; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + + clock-names = "pcie_pipe_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_aux_clk", "pcie_ldo", + "pcie_slv_q2a_axi_clk", + "pcie_0_ref_clk_src"; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>; + + reset-names = "pcie_core_reset", + "pcie_phy_reset"; + qcom,pcie-vendor-id = /bits/ 16 <0x17cb>; + qcom,pcie-device-id = /bits/ 16 <0x0600>; + qcom,pcie-link-speed = <4>; + qcom,pcie-phy-ver = <6>; + qcom,pcie-active-config; + qcom,pcie-aggregated-irq; + qcom,pcie-mhi-a7-irq; + qcom,phy-status-reg2 = <0x1214>; + qcom,mhi-soc-reset-offset = <0xb01b8>; + qcom,aux-clk = <0x11>; + + status = "ok"; + }; + }; &firmware { From a40c8ce42b5853af92c10b7e7e3899bec439e1d6 Mon Sep 17 00:00:00 2001 From: Bhaumik Bhatt Date: Mon, 24 Jan 2022 23:57:42 -0800 Subject: [PATCH 2/2] ARM: dts: msm: Add initial device tree for MHI on cinder On Cinder platform, add initial device tree information for MHI. Change-Id: Ic2ce72f577391e4718e34ba2ef575be1db661150 --- qcom/cinder.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi index bf892e4b..b01026df 100644 --- a/qcom/cinder.dtsi +++ b/qcom/cinder.dtsi @@ -575,6 +575,25 @@ status = "ok"; }; + mhi_device: mhi_dev@1c04000 { + compatible = "qcom,msm-mhi-dev"; + reg = <0x1c04000 0x1000>; + reg-names = "mhi_mmio_base"; + qcom,mhi-ep-msi = <0>; + qcom,mhi-version = <0x1000000>; + qcom,use-mhi-dma-software-channel; + interrupts = ; + interrupt-names = "mhi-device-inta"; + qcom,mhi-ifc-id = <0x060017cb>; + qcom,mhi-interrupt; + qcom,no-m0-timeout; + status = "ok"; + }; + + mhi_net_device: qcom,mhi_net_dev { + compatible = "qcom,msm-mhi-dev-net"; + status = "ok"; + }; }; &firmware {