From 3198aaac50cf310b3d8ea703a79f378f695f8325 Mon Sep 17 00:00:00 2001 From: Veerabhadrarao Badiganti Date: Fri, 24 Jun 2022 23:39:30 +0530 Subject: [PATCH] ARM: dts: msm: Add PCIe PHY settings for cinder Add PCIe PHY settings for end-point mode for cinder. Update setting as per HSR v0.93. Change-Id: I7cbc9b403395d4cf11274b1b069275080825ab5b --- qcom/cinder.dtsi | 98 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi index 7438b7a3..3a0e9bb0 100644 --- a/qcom/cinder.dtsi +++ b/qcom/cinder.dtsi @@ -1137,6 +1137,104 @@ qcom,mhi-soc-reset-offset = <0xb01b8>; qcom,aux-clk = <0x11>; + qcom,phy-init = <0x9040 0x01 0x0 + 0x80c4 0x00 0x0 + 0x80c8 0x1f 0x0 + 0x80d4 0x12 0x0 + 0x80d8 0x1a 0x0 + 0x80dc 0xba 0x0 + 0x80e0 0x8a 0x0 + 0x80e4 0x8b 0x0 + 0x80e8 0x82 0x0 + 0x80ec 0x65 0x0 + 0x80f0 0x1f 0x0 + 0x80f4 0x1f 0x0 + 0x80f8 0x1f 0x0 + 0x80fc 0x1f 0x0 + 0x8100 0x1f 0x0 + 0x8104 0x1f 0x0 + 0x810c 0x1f 0x0 + 0x8114 0x1f 0x0 + 0x811c 0x1f 0x0 + 0x880c 0x02 0x0 + 0x8844 0x1c 0x0 + 0x884c 0x07 0x0 + 0x8858 0x0f 0x0 + 0x8874 0x28 0x0 + 0x8878 0x28 0x0 + 0x887c 0x0d 0x0 + 0x8880 0x0d 0x0 + 0x8884 0x00 0x0 + 0x8888 0x00 0x0 + 0x8894 0x00 0x0 + 0x88a4 0x46 0x0 + 0x88a8 0x04 0x0 + 0x88ac 0xff 0x0 + 0x88b0 0x04 0x0 + 0x88b4 0xff 0x0 + 0x88b8 0x04 0x0 + 0x88bc 0x32 0x0 + 0x88c4 0x28 0x0 + 0x88ec 0xfb 0x0 + 0x88f0 0x03 0x0 + 0x88f4 0xfb 0x0 + 0x88f8 0x03 0x0 + 0x890c 0x02 0x0 + 0x8958 0x13 0x0 + 0x895c 0x00 0x0 + 0x8968 0x0a 0x0 + 0x896c 0x08 0x0 + 0x8974 0x20 0x0 + 0x897c 0x16 0x0 + 0x899c 0x88 0x0 + 0x89a0 0x14 0x0 + 0x89a8 0x0f 0x0 + 0x917c 0x2e 0x0 + 0x9194 0x66 0x0 + 0x91bc 0x11 0x0 + 0x91f8 0x16 0x0 + 0x91fc 0x22 0x0 + 0x9858 0x02 0x0 + 0x988c 0x08 0x0 + 0x98a8 0x16 0x0 + 0x9910 0x02 0x0 + 0x9964 0x2e 0x0 + 0x9984 0x03 0x0 + 0x998c 0x28 0x0 + 0x999c 0x03 0x0 + 0xe030 0x00 0x0 + 0xe034 0x00 0x0 + 0xe078 0x01 0x0 + 0xe07c 0x80 0x0 + 0xe080 0x50 0x0 + 0xe208 0x0a 0x0 + 0xe20c 0x0a 0x0 + 0xe220 0x16 0x0 + 0xe234 0x00 0x0 + 0xe2b4 0x05 0x0 + 0xe2e8 0x0a 0x0 + 0xe30c 0x0d 0x0 + 0xe320 0x0b 0x0 + 0xe348 0x1c 0x0 + 0xe388 0x20 0x0 + 0xe394 0x38 0x0 + 0xe3f4 0x12 0x0 + 0xe3f8 0x1a 0x0 + 0xe3fc 0xba 0x0 + 0xe400 0xca 0x0 + 0xe404 0x8b 0x0 + 0xe408 0x82 0x0 + 0xe40c 0xef 0x0 + 0xe410 0x2c 0x0 + 0xe414 0x5b 0x0 + 0xe418 0x7c 0x0 + 0xe41c 0xeb 0x0 + 0xe420 0x4b 0x0 + 0xe424 0x86 0x0 + 0xe428 0xff 0x0 + 0x9000 0x00 0x0 + 0x9044 0x03 0x0>; + status = "ok"; };