diff --git a/qcom/sdxbaagha-pcie.dtsi b/qcom/sdxbaagha-pcie.dtsi new file mode 100644 index 00000000..b50fea61 --- /dev/null +++ b/qcom/sdxbaagha-pcie.dtsi @@ -0,0 +1,222 @@ +#include +#include + +&soc { + pcie0: qcom,pcie@1bf0000 { + compatible = "qcom,pci-msm"; + + reg = <0x01bf0000 0x4000>, + <0x01bf6000 0x2000>, + <0x48000000 0xf1d>, + <0x48000f20 0xa8>, + <0x48001000 0x1000>, + <0x48100000 0x100000>, + <0x1bf4000 0x1000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf","mhi"; + + cell-index = <0>; + linux,pci-domain = <0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x48200000 0x48200000 0x0 0x100000>, + <0x02000000 0x0 0x48300000 0x48300000 0x0 0x3d00000>; + + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + + msi-parent = <&pcie0_msi>; + + perst-gpio = <&tlmm 57 GPIO_ACTIVE_HIGH>; + wake-gpio = <&tlmm 53 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + pinctrl-1 = <&pcie0_clkreq_sleep + &pcie0_perst_default + &pcie0_wake_default>; + + gdsc-vdd-supply = <&gcc_pcie_gdsc>; + + vreg-1p2-supply = <&L14A>; + vreg-0p9-supply = <&L3A>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; + qcom,vreg-1p2-voltage-level = <1200000 1200000 15000>; + qcom,vreg-0p9-voltage-level = <880000 880000 48100>; + qcom,vreg-cx-voltage-level = ; + qcom,vreg-mx-voltage-level = ; + + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + //interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>, + <&gcc GCC_PCIE_PIPE_CLK_SRC>, + <&pcie_pipe_clk>; + + clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", + "pcie_aux_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_clkref_en", "pcie_slv_q2a_axi_clk", + "pcie_sleep_clk", "pcie_phy_refgen_clk", + "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src"; + + clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <100000000>, <0>, <0>; + clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>, + <0>, <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_BCR>, + <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "pcie_core_reset", + "pcie_phy_reset"; + + qcom,smmu-sid-base = <0x0400>; + iommu-map = <0x0 &apps_smmu 0x0400 0x1>, + <0x100 &apps_smmu 0x0401 0x1>; + + qcom,target-link-speed = <1>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ + qcom,tpwr-on-scale = <1>; + qcom,tpwr-on-value = <9>; + qcom,eq-fmdc-t-min-phase23 = <1>; + qcom,slv-addr-space-size = <0x4000000>; + qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; + + qcom,pcie-phy-ver = <107>; + qcom,phy-status-offset = <0x214>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x240>; + + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xca 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0xa2 0x0 + 0x0050 0x07 0x0 + 0x0010 0x01 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0ee4 0x20 0x0 + 0x0e84 0x75 0x0 + 0x0e90 0x3f 0x0 + 0x115c 0x7f 0x0 + 0x1160 0xff 0x0 + 0x1164 0xbf 0x0 + 0x1168 0x3f 0x0 + 0x116c 0xd8 0x0 + 0x1170 0xdc 0x0 + 0x1174 0xdc 0x0 + 0x1178 0x5c 0x0 + 0x117c 0x34 0x0 + 0x1180 0xa6 0x0 + 0x1190 0x34 0x0 + 0x1194 0x38 0x0 + 0x10d8 0x0f 0x0 + 0x0e3c 0x12 0x0 + 0x0e40 0x01 0x0 + 0x10dc 0x00 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x1044 0xf0 0x0 + 0x11a4 0x38 0x0 + 0x10cc 0xf0 0x0 + 0x10f4 0x07 0x0 + 0x1008 0x09 0x0 + 0x1014 0x05 0x0 + 0x0694 0x00 0x0 + 0x0654 0x00 0x0 + 0x06a8 0x0f 0x0 + 0x0048 0x90 0x0 + 0x0620 0xc1 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x02dc 0x05 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + pcie0_rp: pcie0_rp { + reg = <0 0 0 0 0>; + }; +}; + + pcie0_msi: qcom,pcie0_msi@a0000000 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0xa0000000 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + ; + qcom,snps; + }; +}; diff --git a/qcom/sdxbaagha-pinctrl.dtsi b/qcom/sdxbaagha-pinctrl.dtsi index 8a5dd3c8..57eb8cd1 100644 --- a/qcom/sdxbaagha-pinctrl.dtsi +++ b/qcom/sdxbaagha-pinctrl.dtsi @@ -50,4 +50,58 @@ }; }; }; +pcie0 { + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio56"; + function = "pcie0_clkreq_n"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_clkreq_sleep: pcie0_clkreq_sleep { + mux { + pins = "gpio56"; + function = "gpio"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + }; diff --git a/qcom/sdxbaagha-rumi.dtsi b/qcom/sdxbaagha-rumi.dtsi index 893253f1..84c43d30 100644 --- a/qcom/sdxbaagha-rumi.dtsi +++ b/qcom/sdxbaagha-rumi.dtsi @@ -1,4 +1,23 @@ &soc { + pcie0: qcom,pcie@1bf0000 { + status = "disabled"; + reg = <0x01bf0000 0x4000>, + <0x01bf6000 0x2000>, + <0x48000000 0xf1d>, + <0x48000f20 0xa8>, + <0x48001000 0x1000>, + <0x48100000 0x100000>, + <0x1bf4000 0x1000>, + <0x1bf5000 0x1000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", + "conf", "mhi", "rumi"; + qcom,target-link-speed = <0x1>; + qcom,link-check-max-count = <200>; /* 1 sec */ + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-l0s-supported; + qcom,no-aux-clk-sync; + }; }; &qupv3_se3_2uart { diff --git a/qcom/sdxbaagha.dtsi b/qcom/sdxbaagha.dtsi index 57f09519..0ec8e715 100644 --- a/qcom/sdxbaagha.dtsi +++ b/qcom/sdxbaagha.dtsi @@ -15,7 +15,9 @@ serial0 = &qupv3_se3_2uart; }; - chosen { }; + chosen { + bootargs = "pcie_ports=compat"; + }; memory { device_type = "memory"; reg = <0 0>; }; @@ -297,6 +299,7 @@ #include "sdxbaagha-pinctrl.dtsi" #include "sdxbaagha-dma-heaps.dtsi" #include "msm-arm-smmu-sdxbaagha.dtsi" +#include "sdxbaagha-pcie.dtsi" #include "sdxbaagha-qupv3.dtsi" &qupv3_se3_2uart {