From e3917390044a52317f41835deeb5223c50811837 Mon Sep 17 00:00:00 2001
From: Maulik Shah <mkshah@qti.qualcomm.com>
Date: Sat, 8 Jan 2022 21:38:31 +0530
Subject: [PATCH 1/4] ARM: dts: msm: Update apps_rsc device node for sm8150

Update apps_rsc device node to use channel.

Change-Id: I1750576cccc1575d4736cfe145f2005cfd478a9a
---
 qcom/sm8150.dtsi | 31 +++++++++++++++++++------------
 1 file changed, 19 insertions(+), 12 deletions(-)

diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi
index b4ab1a68..02c4abae 100644
--- a/qcom/sm8150.dtsi
+++ b/qcom/sm8150.dtsi
@@ -513,22 +513,29 @@
 		      <0x18210000 0x10000>,
 		      <0x18220000 0x10000>;
 		reg-names = "drv-0", "drv-1", "drv-2";
+		qcom,drv-count = <3>;
 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
-		qcom,tcs-offset = <0xd00>;
-		qcom,drv-id = <2>;
-		qcom,tcs-config = <ACTIVE_TCS  2>,
-				  <SLEEP_TCS   1>,
-				  <WAKE_TCS    1>,
-				  <CONTROL_TCS 0>;
 
-		rpmhcc: clock-controller {
-			compatible = "qcom,sm8150-rpmh-clk";
-			#clock-cells = <1>;
-			clock-names = "xo";
-			clocks = <&xo_board>;
-			status = "okay";
+		apps_rsc_drv2: drv@2 {
+			qcom,drv-id = <2>;
+			qcom,tcs-offset = <0xd00>;
+			channel@0 {
+				qcom,tcs-config = <ACTIVE_TCS    2>,
+						  <SLEEP_TCS     3>,
+						  <WAKE_TCS      3>,
+						  <CONTROL_TCS   1>,
+						  <FAST_PATH_TCS 0>;
+			};
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,sm8150-rpmh-clk";
+				#clock-cells = <1>;
+				clock-names = "xo";
+				clocks = <&xo_board>;
+				status = "okay";
+			};
 		};
 	};
 

From 798c1484955debbea9673b152ae9f378fee0431a Mon Sep 17 00:00:00 2001
From: Maulik Shah <mkshah@qti.qualcomm.com>
Date: Wed, 19 Jan 2022 11:25:40 +0530
Subject: [PATCH 2/4] ARM: dts: msm: Add disp_rsc device for sm8150

Add disp_rsc device for RPMH communication.

Change-Id: I7ce28497047a83defacf8f0e1510a960494f8ff0
---
 qcom/sm8150.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi
index 02c4abae..27679438 100644
--- a/qcom/sm8150.dtsi
+++ b/qcom/sm8150.dtsi
@@ -539,6 +539,27 @@
 		};
 	};
 
+	disp_rsc: rsc@af20000 {
+		label = "disp_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0xaf20000 0x10000>;
+		reg-names = "drv-0";
+		qcom,drv-count = <1>;
+		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+
+		disp_rsc_drv0: drv@0 {
+			qcom,drv-id = <0>;
+			qcom,tcs-offset = <0x1c00>;
+			channel@0 {
+				qcom,tcs-config = <SLEEP_TCS     1>,
+						  <WAKE_TCS      1>,
+						  <ACTIVE_TCS    2>,
+						  <CONTROL_TCS   0>,
+						  <FAST_PATH_TCS 0>;
+			};
+		};
+	};
+
 	gcc: clock-controller@100000 {
 		compatible = "qcom,gcc-sm8150";
 		reg = <0x100000 0x1f0000>;

From 75dcd8ab6209de3c6da2e33d5a02f8614c3e2a9a Mon Sep 17 00:00:00 2001
From: Maulik Shah <mkshah@qti.qualcomm.com>
Date: Mon, 24 Jan 2022 13:04:45 +0530
Subject: [PATCH 3/4] bindings: interrupt-controller: qcom-pdc: Add compatible
 for SM8150

Document SM8150 compatible.

Change-Id: I32f8c3a5c537884b3f8b2a878a588417c1c23891
---
 bindings/interrupt-controller/qcom,pdc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/bindings/interrupt-controller/qcom,pdc.txt b/bindings/interrupt-controller/qcom,pdc.txt
index 98d89e53..bd353964 100644
--- a/bindings/interrupt-controller/qcom,pdc.txt
+++ b/bindings/interrupt-controller/qcom,pdc.txt
@@ -21,6 +21,7 @@ Properties:
 		    - "qcom,sc7180-pdc": For SC7180
 		    - "qcom,sc7280-pdc": For SC7280
 		    - "qcom,sdm845-pdc": For SDM845
+		    - "qcom,sdm8150-pdc": For SM8150
 		    - "qcom,sdm8250-pdc": For SM8250
 		    - "qcom,sdm8350-pdc": For SM8350
 

From aab077dac8cfda8c67e5107c2dc9c292dd295f5c Mon Sep 17 00:00:00 2001
From: Maulik Shah <mkshah@qti.qualcomm.com>
Date: Mon, 24 Jan 2022 13:06:09 +0530
Subject: [PATCH 4/4] ARM: dts: msm: Add PDC interrupt controller for SM8150

Add PDC interrupt controller to support wakeup capable interrupts
and as wakeup parent device to TLMM.

Change-Id: I0382f9254016915441a470b94f94d3bee210eb1b
---
 qcom/sm8150-pinctrl.dtsi | 1 +
 qcom/sm8150.dtsi         | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/qcom/sm8150-pinctrl.dtsi b/qcom/sm8150-pinctrl.dtsi
index be7401a8..02a24fcf 100644
--- a/qcom/sm8150-pinctrl.dtsi
+++ b/qcom/sm8150-pinctrl.dtsi
@@ -12,6 +12,7 @@
 		#gpio-cells = <2>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
+		wakeup-parent = <&pdc>;
 
 		ufs_dev_reset_assert: ufs_dev_reset_assert {
 			config {
diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi
index 27679438..453c9db9 100644
--- a/qcom/sm8150.dtsi
+++ b/qcom/sm8150.dtsi
@@ -433,6 +433,15 @@
 		interrupt-parent = <&intc>;
 	};
 
+	pdc: interrupt-controller@b220000 {
+		compatible = "qcom,sm8150-pdc", "qcom,pdc";
+		reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
+		qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&intc>;
+		interrupt-controller;
+	};
+
 	arch_timer: timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,