From 3d585b804c656157df270d73b5f611604a70634d Mon Sep 17 00:00:00 2001
From: Krishna Kurapati <kriskura@qti.qualcomm.com>
Date: Thu, 28 Jul 2022 19:14:02 +0530
Subject: [PATCH] ARM: dts: msm: Add usb device nodes for sdxbaagha

Add USB device node to support USB peripheral mode on
RUMI platform for sdxbaagha.

Change-Id: I64e6a91cb37b2cf7dfe69f7bdd6f632f8e79222b
---
 qcom/sdxbaagha-rumi.dtsi | 28 ++++++++++++++++++++++++
 qcom/sdxbaagha-usb.dtsi  | 46 ++++++++++++++++++++++++++++++++++++++++
 qcom/sdxbaagha.dtsi      |  1 +
 3 files changed, 75 insertions(+)
 create mode 100644 qcom/sdxbaagha-usb.dtsi

diff --git a/qcom/sdxbaagha-rumi.dtsi b/qcom/sdxbaagha-rumi.dtsi
index 26af1922..e2f47e70 100644
--- a/qcom/sdxbaagha-rumi.dtsi
+++ b/qcom/sdxbaagha-rumi.dtsi
@@ -18,6 +18,27 @@
 		qcom,no-l0s-supported;
 		qcom,no-aux-clk-sync;
 	};
+
+	usb_nop_phy: usb_nop_phy {
+		compatible = "usb-nop-xceiv";
+	};
+
+	usb_emuphy: phy@a71c000 {
+		compatible = "qcom,usb-emu-phy";
+		reg = <0xA71C000 0x9500>;
+
+		qcom,emu-init-seq = <0xfff0 0x4
+					0xfff3 0x4
+					0xfff0 0x4
+					0x100000 0x20
+					0x0 0x20
+					0x1e0 0x20
+					0x100000 0x3c
+					0x0 0x3c
+					0x4 0x3c
+					0x0 0x4
+					0x9 0x14>;
+	};
 };
 
 &qupv3_se3_2uart {
@@ -27,3 +48,10 @@
 &gcc {
 	clocks = <&bi_tcxo>, <&pcie_pipe_clk>, <&sleep_clk>;
 };
+
+&usb0 {
+	dwc3@a600000 {
+		usb-phy = <&usb_emuphy>, <&usb_nop_phy>;
+		dr_mode = "peripheral";
+	};
+};
diff --git a/qcom/sdxbaagha-usb.dtsi b/qcom/sdxbaagha-usb.dtsi
new file mode 100644
index 00000000..14d8e38b
--- /dev/null
+++ b/qcom/sdxbaagha-usb.dtsi
@@ -0,0 +1,46 @@
+#include <dt-bindings/clock/qcom,gcc-sdxbaagha.h>
+
+&soc {
+	usb0: hsusb@a600000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0xa600000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		USB3_GDSC-supply = <&gcc_usb20_gdsc>;
+
+		clocks = <&gcc GCC_USB20_MASTER_CLK>,
+			<&gcc GCC_SYS_NOC_USB_SF_AXI_CLK>,
+			<&gcc GCC_USB20_SLEEP_CLK>,
+			<&gcc GCC_USB20_MOCK_UTMI_CLK>;
+
+		clock-names = "core_clk", "iface_clk", "sleep_clk", "utmi_clk";
+
+		resets = <&gcc GCC_USB20_BCR>;
+		reset-names = "core_reset";
+
+		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pwr_event_irq";
+
+		qcom,core-clk-rate = <60000000>;
+
+		dwc3@a600000 {
+			compatible = "snps,dwc3";
+			reg = <0xa600000 0xd93c>;
+
+			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+			snps,disable-clk-gating;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,is-utmi-l1-suspend;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			maximum-speed = "high-speed";
+			dr_mode = "otg";
+			usb-role-switch;
+		};
+	};
+};
diff --git a/qcom/sdxbaagha.dtsi b/qcom/sdxbaagha.dtsi
index 2e17a39d..e347f5a7 100644
--- a/qcom/sdxbaagha.dtsi
+++ b/qcom/sdxbaagha.dtsi
@@ -491,6 +491,7 @@
 #include "msm-arm-smmu-sdxbaagha.dtsi"
 #include "sdxbaagha-pcie.dtsi"
 #include "sdxbaagha-qupv3.dtsi"
+#include "sdxbaagha-usb.dtsi"
 
 &qupv3_se3_2uart {
 	status = "ok";