From 595490f425f897f44d80f0fe18234d2eefb40bad Mon Sep 17 00:00:00 2001 From: Yatish Kumar Singh Date: Fri, 29 Jul 2022 14:51:20 +0530 Subject: [PATCH] ARM: dts: msm: Add QUPv3 DT nodes in Monaco Add I2C,SPI and GPI DT nodes in Monaco. Change-Id: I5642c8b6af24b44e23a7e3a22c3230ef54b8e844 --- qcom/monaco-pinctrl.dtsi | 578 ++++++++++++++++++++++++++++++--------- qcom/monaco-qupv3.dtsi | 437 +++++++++++++++++++++++++++++ 2 files changed, 887 insertions(+), 128 deletions(-) diff --git a/qcom/monaco-pinctrl.dtsi b/qcom/monaco-pinctrl.dtsi index d3e2ddec..b727131b 100644 --- a/qcom/monaco-pinctrl.dtsi +++ b/qcom/monaco-pinctrl.dtsi @@ -51,14 +51,27 @@ }; qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { - qupv3_se0_i2c_active: qupv3_se0_i2c_active { + qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active { mux { - pins = "gpio4", "gpio5"; - function = "qup00"; + pins = "gpio4"; + function = "qup0_l0"; }; config { - pins = "gpio4", "gpio5"; + pins = "gpio4"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active { + mux { + pins = "gpio5"; + function = "qup0_l1"; + }; + + config { + pins = "gpio5"; drive-strength = <2>; bias-pull-up; }; @@ -141,16 +154,53 @@ }; qupv3_se0_spi_pins: qupv3_se0_spi_pins { - qupv3_se0_spi_active: qupv3_se0_spi_active { + qupv3_se0_spi_miso_active: qupv3_se0_spi_miso_active { mux { - pins = "gpio4", "gpio5", - "gpio6", "gpio7"; - function = "qup00"; + pins = "gpio4"; + function = "qup0_l0"; }; config { - pins = "gpio4", "gpio5", - "gpio6", "gpio7"; + pins = "gpio4"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_mosi_active: qupv3_se0_spi_mosi_active { + mux { + pins = "gpio5"; + function = "qup0_l1"; + }; + + config { + pins = "gpio5"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_clk_active: qupv3_se0_spi_clk_active { + mux { + pins = "gpio6"; + function = "qup0_l2"; + }; + + config { + pins = "gpio6"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active { + mux { + pins = "gpio7"; + function = "qup0_l3"; + }; + + config { + pins = "gpio7"; drive-strength = <6>; bias-disable; }; @@ -159,13 +209,13 @@ qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { mux { pins = "gpio4", "gpio5", - "gpio6", "gpio7"; + "gpio6", "gpio7"; function = "gpio"; }; config { pins = "gpio4", "gpio5", - "gpio6", "gpio7"; + "gpio6", "gpio7"; drive-strength = <6>; bias-disable; }; @@ -173,14 +223,27 @@ }; qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { - qupv3_se1_i2c_active: qupv3_se1_i2c_active { + qupv3_se1_i2c_sda_active: qupv3_se1_i2c_sda_active { mux { - pins = "gpio10", "gpio11"; - function = "qup01"; + pins = "gpio10"; + function = "qup0_l0"; }; config { - pins = "gpio10", "gpio11"; + pins = "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_scl_active: qupv3_se1_i2c_scl_active { + mux { + pins = "gpio11"; + function = "qup0_l1"; + }; + + config { + pins = "gpio11"; drive-strength = <2>; bias-pull-up; }; @@ -201,16 +264,53 @@ }; qupv3_se1_spi_pins: qupv3_se1_spi_pins { - qupv3_se1_spi_active: qupv3_se1_spi_active { + qupv3_se1_spi_miso_active: qupv3_se1_spi_miso_active { mux { - pins = "gpio10", "gpio11", - "gpio12", "gpio13"; - function = "qup01"; + pins = "gpio10"; + function = "qup0_l0"; }; config { - pins = "gpio10", "gpio11", - "gpio12", "gpio13"; + pins = "gpio10"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_mosi_active: qupv3_se1_spi_mosi_active { + mux { + pins = "gpio11"; + function = "qup0_l1"; + }; + + config { + pins = "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_clk_active: qupv3_se1_spi_clk_active { + mux { + pins = "gpio12"; + function = "qup0_l2"; + }; + + config { + pins = "gpio12"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_cs_active: qupv3_se1_spi_cs_active { + mux { + pins = "gpio13"; + function = "qup0_l3"; + }; + + config { + pins = "gpio13"; drive-strength = <6>; bias-disable; }; @@ -219,13 +319,13 @@ qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { mux { pins = "gpio10", "gpio11", - "gpio12", "gpio13"; + "gpio12", "gpio13"; function = "gpio"; }; config { pins = "gpio10", "gpio11", - "gpio12", "gpio13"; + "gpio12", "gpio13"; drive-strength = <6>; bias-disable; }; @@ -233,14 +333,27 @@ }; qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { - qupv3_se2_i2c_active: qupv3_se2_i2c_active { + qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active { mux { - pins = "gpio0", "gpio1"; - function = "qup02"; + pins = "gpio0"; + function = "qup0_l0"; }; config { - pins = "gpio0", "gpio1"; + pins = "gpio0"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active { + mux { + pins = "gpio1"; + function = "qup0_l1"; + }; + + config { + pins = "gpio1"; drive-strength = <2>; bias-pull-up; }; @@ -261,16 +374,53 @@ }; qupv3_se2_spi_pins: qupv3_se2_spi_pins { - qupv3_se2_spi_active: qupv3_se2_spi_active { + qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active { mux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "qup02"; + pins = "gpio0"; + function = "qup0_l0"; }; config { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; + pins = "gpio0"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active { + mux { + pins = "gpio1"; + function = "qup0_l1"; + }; + + config { + pins = "gpio1"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active { + mux { + pins = "gpio2"; + function = "qup0_l2"; + }; + + config { + pins = "gpio2"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active { + mux { + pins = "gpio3"; + function = "qup0_l3"; + }; + + config { + pins = "gpio3"; drive-strength = <6>; bias-disable; }; @@ -279,13 +429,13 @@ qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { mux { pins = "gpio0", "gpio1", - "gpio2", "gpio3"; + "gpio2", "gpio3"; function = "gpio"; }; config { pins = "gpio0", "gpio1", - "gpio2", "gpio3"; + "gpio2", "gpio3"; drive-strength = <6>; bias-disable; }; @@ -293,14 +443,27 @@ }; qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { - qupv3_se3_i2c_active: qupv3_se3_i2c_active { + qupv3_se3_i2c_sda_active: qupv3_se3_i2c_sda_active { mux { - pins = "gpio14", "gpio15"; - function = "qup03"; + pins = "gpio14"; + function = "qup0_l0"; }; config { - pins = "gpio14", "gpio15"; + pins = "gpio14"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_scl_active: qupv3_se3_i2c_scl_active { + mux { + pins = "gpio15"; + function = "qup0_l1"; + }; + + config { + pins = "gpio15"; drive-strength = <2>; bias-pull-up; }; @@ -321,16 +484,53 @@ }; qupv3_se3_spi_pins: qupv3_se3_spi_pins { - qupv3_se3_spi_active: qupv3_se3_spi_active { + qupv3_se3_spi_miso_active: qupv3_se3_spi_miso_active { mux { - pins = "gpio14", "gpio15", - "gpio16", "gpio17"; - function = "qup03"; + pins = "gpio14"; + function = "qup0_l0"; }; config { - pins = "gpio14", "gpio15", - "gpio16", "gpio17"; + pins = "gpio14"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_mosi_active: qupv3_se3_spi_mosi_active { + mux { + pins = "gpio15"; + function = "qup0_l1"; + }; + + config { + pins = "gpio15"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_clk_active: qupv3_se3_spi_clk_active { + mux { + pins = "gpio16"; + function = "qup0_l2"; + }; + + config { + pins = "gpio16"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_cs_active: qupv3_se3_spi_cs_active { + mux { + pins = "gpio17"; + function = "qup0_l3"; + }; + + config { + pins = "gpio17"; drive-strength = <6>; bias-disable; }; @@ -339,13 +539,13 @@ qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { mux { pins = "gpio14", "gpio15", - "gpio16", "gpio17"; + "gpio16", "gpio17"; function = "gpio"; }; config { pins = "gpio14", "gpio15", - "gpio16", "gpio17"; + "gpio16", "gpio17"; drive-strength = <6>; bias-disable; }; @@ -353,14 +553,27 @@ }; qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { - qupv3_se4_i2c_active: qupv3_se4_i2c_active { + qupv3_se4_i2c_sda_active: qupv3_se4_i2c_sda_active { mux { - pins = "gpio20", "gpio21"; - function = "qup04"; + pins = "gpio20"; + function = "qup0_l0"; }; config { - pins = "gpio20", "gpio21"; + pins = "gpio20"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se4_i2c_scl_active: qupv3_se4_i2c_scl_active { + mux { + pins = "gpio21"; + function = "qup0_l1"; + }; + + config { + pins = "gpio21"; drive-strength = <2>; bias-pull-up; }; @@ -381,16 +594,53 @@ }; qupv3_se4_spi_pins: qupv3_se4_spi_pins { - qupv3_se4_spi_active: qupv3_se4_spi_active { + qupv3_se4_spi_miso_active: qupv3_se4_spi_miso_active { mux { - pins = "gpio20", "gpio21", - "gpio22"; - function = "qup04"; + pins = "gpio20"; + function = "qup0_l0"; }; config { - pins = "gpio20", "gpio21", - "gpio22"; + pins = "gpio20"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_mosi_active: qupv3_se4_spi_mosi_active { + mux { + pins = "gpio21"; + function = "qup0_l1"; + }; + + config { + pins = "gpio21"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_clk_active: qupv3_se4_spi_clk_active { + mux { + pins = "gpio22"; + function = "qup0_l2"; + }; + + config { + pins = "gpio22"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_cs_active: qupv3_se4_spi_cs_active { + mux { + pins = "gpio23"; + function = "qup0_l3"; + }; + + config { + pins = "gpio23"; drive-strength = <6>; bias-disable; }; @@ -399,54 +649,41 @@ qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { mux { pins = "gpio20", "gpio21", - "gpio22"; + "gpio22", "gpio23"; function = "gpio"; }; config { pins = "gpio20", "gpio21", - "gpio22"; + "gio22", "gpio23"; drive-strength = <6>; bias-disable; }; }; - - qupv3_se4_spi_cs0_active: qupv3_se4_spi_cs0_active { - mux { - pins = "gpio23"; - function = "qup04"; - }; - - config { - pins = "gpio23"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - qupv3_se4_spi_cs0_sleep: qupv3_se4_spi_cs0_sleep { - mux { - pins = "gpio23"; - function = "gpio"; - }; - - config { - pins = "gpio23"; - drive-strength = <6>; - bias-pull-up; - }; - }; }; qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { - qupv3_se5_i2c_active: qupv3_se5_i2c_active { + qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active { mux { - pins = "gpio26", "gpio27"; - function = "qup05"; + pins = "gpio26"; + function = "qup0_l0"; }; config { - pins = "gpio26", "gpio27"; + pins = "gpio26"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active { + mux { + pins = "gpio27"; + function = "qup0_l1"; + }; + + config { + pins = "gpio27"; drive-strength = <2>; bias-pull-up; }; @@ -467,16 +704,53 @@ }; qupv3_se5_spi_pins: qupv3_se5_spi_pins { - qupv3_se5_spi_active: qupv3_se5_spi_active { + qupv3_se5_spi_miso_active: qupv3_se5_spi_miso_active { mux { - pins = "gpio26", "gpio27", - "gpio28", "gpio29"; - function = "qup05"; + pins = "gpio26"; + function = "qup0_l0"; }; config { - pins = "gpio26", "gpio27", - "gpio28", "gpio29"; + pins = "gpio26"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_mosi_active: qupv3_se5_spi_mosi_active { + mux { + pins = "gpio27"; + function = "qup0_l1"; + }; + + config { + pins = "gpio21"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_clk_active: qupv3_se5_spi_clk_active { + mux { + pins = "gpio28"; + function = "qup0_l2"; + }; + + config { + pins = "gpio28"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_cs_active: qupv3_se5_spi_cs_active { + mux { + pins = "gpio29"; + function = "qup0_l3"; + }; + + config { + pins = "gpio29"; drive-strength = <6>; bias-disable; }; @@ -485,13 +759,13 @@ qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { mux { pins = "gpio26", "gpio27", - "gpio28", "gpio29"; + "gpio28", "gpio29"; function = "gpio"; }; config { pins = "gpio26", "gpio27", - "gpio28", "gpio29"; + "gpio28", "gpio29"; drive-strength = <6>; bias-disable; }; @@ -499,14 +773,27 @@ }; qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { - qupv3_se6_i2c_active: qupv3_se6_i2c_active { + qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active { mux { - pins = "gpio24", "gpio25"; - function = "qup06"; + pins = "gpio24"; + function = "qup0_10"; }; config { - pins = "gpio24", "gpio25"; + pins = "gpio24"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active { + mux { + pins = "gpio25"; + function = "qup0_11"; + }; + + config { + pins = "gpio25"; drive-strength = <2>; bias-pull-up; }; @@ -527,16 +814,53 @@ }; qupv3_se6_spi_pins: qupv3_se6_spi_pins { - qupv3_se6_spi_active: qupv3_se6_spi_active { + qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active { mux { - pins = "gpio24", "gpio25", - "gpio30", "gpio31"; - function = "qup06"; + pins = "gpio24"; + function = "qup0_l0"; }; config { - pins = "gpio24", "gpio25", - "gpio30", "gpio31"; + pins = "gpio24"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active { + mux { + pins = "gpio25"; + function = "qup0_l1"; + }; + + config { + pins = "gpio25"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active { + mux { + pins = "gpio30"; + function = "qup0_l2"; + }; + + config { + pins = "gpio30"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active { + mux { + pins = "gpio31"; + function = "qup0_l3"; + }; + + config { + pins = "gpio33"; drive-strength = <6>; bias-disable; }; @@ -545,13 +869,13 @@ qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { mux { pins = "gpio24", "gpio25", - "gpio30", "gpio31"; + "gpio30", "gpio31"; function = "gpio"; }; config { pins = "gpio24", "gpio25", - "gpio30", "gpio31"; + "gpio30", "gpio31"; drive-strength = <6>; bias-disable; }; @@ -559,7 +883,7 @@ }; qupv3_se7_i2c_pins_a: qupv3_se7_i2c_pins_a { - qupv3_se7_i2c_active_L0_a: qupv3_se7_i2c_active_L0_a { + qupv3_se7_i2c_sda_a: qupv3_se7_i2c_sda_a { mux { pins = "gpio101"; function = "QUP0_L0"; @@ -570,10 +894,9 @@ drive-strength = <2>; bias-pull-up; }; - }; - qupv3_se7_i2c_active_L1_a: qupv3_se7_i2c_active_L1_a { + qupv3_se7_i2c_scl_a: qupv3_se7_i2c_scl_a { mux { pins = "gpio102"; function = "QUP0_L1"; @@ -601,7 +924,7 @@ }; qupv3_se7_spi_pins_a: qupv3_se7_spi_pins_a { - qupv3_se7_spi_active_L0_a: qupv3_se7_spi_active_L0_a { + qupv3_se7_spi_mosi_a: qupv3_se7_spi_mosi_a { mux { pins = "gpio101"; function = "QUP0_L0"; @@ -614,7 +937,7 @@ }; }; - qupv3_se7_spi_active_L1_a: qupv3_se7_spi_active_L1_a { + qupv3_se7_spi_miso_a: qupv3_se7_spi_miso_a { mux { pins = "gpio102"; function = "QUP0_L1"; @@ -627,7 +950,7 @@ }; }; - qupv3_se7_spi_active_L2_a: qupv3_se7_spi_active_L2_a { + qupv3_se7_spi_clk_a: qupv3_se7_spi_clk_a { mux { pins = "gpio104"; function = "QUP0_L2"; @@ -640,7 +963,7 @@ }; }; - qupv3_se7_spi_active_L3_a: qupv3_se7_spi_active_L3_a { + qupv3_se7_spi_cs_a: qupv3_se7_spi_cs_a { mux { pins = "gpio105"; function = "QUP0_L3"; @@ -656,13 +979,13 @@ qupv3_se7_spi_sleep_a: qupv3_se7_spi_sleep_a { mux { pins = "gpio101", "gpio102", - "gpio104", "gpio105"; + "gpio104", "gpio105"; function = "gpio"; }; config { pins = "gpio101", "gpio102", - "gpio104", "gpio105"; + "gpio104", "gpio105"; drive-strength = <6>; bias-disable; }; @@ -670,7 +993,7 @@ }; qupv3_se7_i2c_pins_b: qupv3_se7_i2c_pins_b { - qupv3_se7_i2c_active_L0_b: qupv3_se7_i2c_active_L0_b { + qupv3_se7_i2c_sda_b: qupv3_se7_i2c_sda_b { mux { pins = "gpio104"; function = "QUP0_L0"; @@ -681,10 +1004,9 @@ drive-strength = <2>; bias-pull-up; }; - }; - qupv3_se7_i2c_active_L1_b: qupv3_se7_i2c_active_L1_b { + qupv3_se7_i2c_scl_b: qupv3_se7_i2c_scl_b { mux { pins = "gpio105"; function = "QUP0_L1"; @@ -712,7 +1034,7 @@ }; qupv3_se7_spi_pins_b: qupv3_se7_spi_pins_b { - qupv3_se7_spi_active_L0_b: qupv3_se7_spi_active_L0_b { + qupv3_se7_spi_miso_b: qupv3_se7_spi_miso_b { mux { pins = "gpio104"; function = "QUP0_L0"; @@ -725,7 +1047,7 @@ }; }; - qupv3_se7_spi_active_L1_b: qupv3_se7_spi_active_L1_b { + qupv3_se7_spi_mosi_b: qupv3_se7_spi_mosi_b { mux { pins = "gpio105"; function = "QUP0_L1"; @@ -738,7 +1060,7 @@ }; }; - qupv3_se7_spi_active_L2_b: qupv3_se7_spi_active_L2_b { + qupv3_se7_spi_clk_b: qupv3_se7_spi_clk_b { mux { pins = "gpio101"; function = "QUP0_L2"; @@ -751,7 +1073,7 @@ }; }; - qupv3_se7_spi_active_L3_b: qupv3_se7_spi_active_L3_b { + qupv3_se7_spi_cs_b: qupv3_se7_spi_cs_b { mux { pins = "gpio102"; function = "QUP0_L3"; @@ -767,13 +1089,13 @@ qupv3_se7_spi_sleep_b: qupv3_se7_spi_sleep_b { mux { pins = "gpio104", "gpio105", - "gpio101", "gpio102"; + "gpio101", "gpio102"; function = "gpio"; }; config { pins = "gpio104", "gpio105", - "gpio101", "gpio102"; + "gpio101", "gpio102"; drive-strength = <6>; bias-disable; }; diff --git a/qcom/monaco-qupv3.dtsi b/qcom/monaco-qupv3.dtsi index 8ae413d2..4abcfea1 100644 --- a/qcom/monaco-qupv3.dtsi +++ b/qcom/monaco-qupv3.dtsi @@ -1,4 +1,43 @@ &soc { + /* QUPv3 SE Instances + * Qup0 0: SE 0 + * Qup0 1: SE 1 + * Qup0 2: SE 2 + * Qup0 3: SE 3 + * Qup0 4: SE 4 + * Qup0 5: SE 5 + * Qup0 6: SE 6 + * Qup0 7: SE 7 + */ + + /* GPI Instance */ + gpi_dma0: qcom,gpi-dma@4a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x4a00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0xf6 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0xf>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + dma-coherent; + status = "ok"; + }; + /* QUPv3_0 wrapper instance */ qupv3_0: qcom,qupv3_0_geni_se@4ac0000 { compatible = "qcom,geni-se-qup"; @@ -61,5 +100,403 @@ qcom,wakeup-byte = <0xFD>; status = "disabled"; }; + + qupv3_se0_i2c: i2c@4a80000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se0_spi: spi@4a80000 { + compatible = "qcom,spi-geni"; + reg = <0x4a80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>, + <&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma0 0 0 1 64 0>, + <&gpi_dma0 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@4a84000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + dmas = <&gpi_dma0 1 0 3 64 0>, + <&gpi_dma0 1 1 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se1_spi: spi@4a84000 { + compatible = "qcom,spi-geni"; + reg = <0x4a84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>, + <&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + dmas = <&gpi_dma0 0 1 1 64 0>, + <&gpi_dma0 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@4a88000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se2_spi: spi@4a88000 { + compatible = "qcom,spi-geni"; + reg = <0x4a88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>, + <&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + dmas = <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@4a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + dmas = <&gpi_dma0 0 3 3 64 0>, + <&gpi_dma0 1 3 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se3_spi: spi@4a8c000 { + compatible = "qcom,spi-geni"; + reg = <0x4a8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>, + <&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + dmas = <&gpi_dma0 0 3 1 64 0>, + <&gpi_dma0 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@4a90000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + dmas = <&gpi_dma0 0 4 3 64 0>, + <&gpi_dma0 1 4 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se4_spi: spi@4a90000 { + compatible = "qcom,spi-geni"; + reg = <0x4a90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>, + <&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + dmas = <&gpi_dma0 0 4 1 64 0>, + <&gpi_dma0 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@4a94000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + dmas = <&gpi_dma0 0 5 3 64 0>, + <&gpi_dma0 1 5 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se5_spi: spi@4a94000 { + compatible = "qcom,spi-geni"; + reg = <0x4a94000 0x4000>; + reg-names = "se_phys"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>, + <&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + dmas = <&gpi_dma0 0 5 1 64 0>, + <&gpi_dma0 1 5 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@4a98000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + dmas = <&gpi_dma0 0 6 3 64 0>, + <&gpi_dma0 1 6 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se6_spi: spi@4a98000 { + compatible = "qcom,spi-geni"; + reg = <0x4a98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>, + <&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + dmas = <&gpi_dma0 0 6 1 64 0>, + <&gpi_dma0 1 6 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se7_i2c_a: i2c_a@4a9c000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_sda_a>, <&qupv3_se7_i2c_scl_a>; + pinctrl-1 = <&qupv3_se7_i2c_sleep_a>; + dmas = <&gpi_dma0 0 7 3 64 0>, + <&gpi_dma0 1 7 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se7_spi_a: spi@4a9c000 { + compatible = "qcom,spi-geni"; + reg = <0x4a9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_mosi_a>, <&qupv3_se7_spi_miso_a>, + <&qupv3_se7_spi_clk_a>, <&qupv3_se7_spi_cs_a>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma0 0 7 1 64 0>, + <&gpi_dma0 1 7 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se7_i2c_b: i2c_b@4a9c000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_sda_b>, <&qupv3_se7_i2c_scl_b>; + pinctrl-1 = <&qupv3_se7_i2c_sleep_b>; + dmas = <&gpi_dma0 0 7 3 64 0>, + <&gpi_dma0 1 7 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; }; };