From fd4db3b32f51b5f9ba8ba38d2407e595449ccbee Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Sun, 4 Apr 2021 17:31:48 +0530 Subject: [PATCH 1/2] dt-bindings: Add device-tree bindings for gic-interrupt-router Add device tree bindings for qcom,gic-interrupt-router. Change-Id: Ibb0b8e8a2c0ac875476d61f1ce54e76673818f15 --- .../soc/qcom/qcom,gic-interrupt-router.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 bindings/soc/qcom/qcom,gic-interrupt-router.yaml diff --git a/bindings/soc/qcom/qcom,gic-interrupt-router.yaml b/bindings/soc/qcom/qcom,gic-interrupt-router.yaml new file mode 100644 index 00000000..357b4440 --- /dev/null +++ b/bindings/soc/qcom/qcom,gic-interrupt-router.yaml @@ -0,0 +1,31 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,gic-interrupt-router.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. GIC Interrupt Router + +properties: + compatible: + Usage: required + Value type: + Definition: Must be "qcom,gic-intr-routing" + + qcom,gic-class0-cpus: + Usage: required + Value type: + Definition: List of CPUs in GIC class 0. + + qcom,gic-class1-cpus: + Usage: required + Value type: + Definition: List of CPUs in GIC class 1. + +examples: + - |+ + qcom,gic-interrupt-router { + compatible = "qcom,gic-intr-routing"; + qcom,gic-class0-cpus = <0 1 2 3>; + qcom,gic-class1-cpus = <4 5 6 7>; + }; +... From dbe395b3cebef6e80229be7f0d0ef60fab62be28 Mon Sep 17 00:00:00 2001 From: Yogesh Lal Date: Tue, 26 Apr 2022 18:37:19 +0530 Subject: [PATCH 2/2] ARM: dts: msm: Add GIC interrupt router device for Kalama Add GIC interrupt router device tree node, to enable interrupt balancing on Kalama. Change-Id: I64dcf33b5598c38bea08d091a3d3807bb47937e5 --- qcom/kalama.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/kalama.dtsi b/qcom/kalama.dtsi index 1ee0c0be..8d0870a9 100644 --- a/qcom/kalama.dtsi +++ b/qcom/kalama.dtsi @@ -1446,6 +1446,14 @@ status = "ok"; }; + gic-interrupt-router { + compatible = "qcom,gic-intr-routing"; + /* keep silver core only to avoid wakeup of gold cores */ + qcom,gic-class0-cpus = <0 1 2>; + /* keep gold and gold+ cores in class1 */ + qcom,gic-class1-cpus = <3 4 5 6 7>; + }; + qcom,secure-buffer { compatible = "qcom,secure-buffer"; qcom,vmid-cp-camera-preview-ro;