From 40980df01ecb2ed256e897ea74169c50a042330c Mon Sep 17 00:00:00 2001
From: Taniya Das <tdas@qti.qualcomm.com>
Date: Fri, 20 May 2022 23:50:50 +0530
Subject: [PATCH] ARM: dts: msm: Add the PCIE/USB fixed clocks for Cinder

Update the fixed clock phandles for GCC clock node.

Change-Id: I791600e7b9fe30ac154c6d44f741fc1ca1c54935
---
 qcom/cinder-rumi.dtsi |  6 ++++--
 qcom/cinder.dtsi      | 31 +++++++++++++++++++++++++++++--
 2 files changed, 33 insertions(+), 4 deletions(-)

diff --git a/qcom/cinder-rumi.dtsi b/qcom/cinder-rumi.dtsi
index 5e6090b9..42246ef5 100644
--- a/qcom/cinder-rumi.dtsi
+++ b/qcom/cinder-rumi.dtsi
@@ -100,8 +100,10 @@
 };
 
 &gcc {
-	clocks = <&bi_tcxo>, <&sleep_clk>;
-	clock-names = "bi_tcxo", "sleep_clk";
+	clocks = <&bi_tcxo>, <&sleep_clk>, <&pcie_0_pipe_clk>,
+		<&pcie_0_phy_aux_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
+	clock-names = "bi_tcxo", "sleep_clk", "pcie_0_pipe_clk",
+		"pcie_0_phy_aux_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk";
 };
 
 &tsens0 {
diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi
index 31ca5b6f..1b919b76 100644
--- a/qcom/cinder.dtsi
+++ b/qcom/cinder.dtsi
@@ -921,13 +921,40 @@
 		#reset-cells = <1>;
 	};
 
+	pcie_0_pipe_clk: pcie_0_pipe_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "pcie_0_pipe_clk";
+		#clock-cells = <0>;
+	};
+
+	pcie_0_phy_aux_clk: pcie_0_phy_aux_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "pcie_0_phy_aux_clk";
+		#clock-cells = <0>;
+	};
+
+	usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
+		#clock-cells = <0>;
+	};
+
 	gcc: clock-controller@80000 {
 		compatible = "qcom,cinder-gcc", "syscon";
 		reg = <0x80000 0x1f4200>;
 		reg-name = "cc_base";
 		vdd_cx-supply = <&VDD_CX_LEVEL>;
-		clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
-		clock-names = "bi_tcxo", "sleep_clk";
+		clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
+			 <&pcie_0_pipe_clk>,
+			 <&pcie_0_phy_aux_clk>,
+			 <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
+		clock-names = "bi_tcxo", "sleep_clk",
+			      "pcie_0_pipe_clk",
+			      "pcie_0_phy_aux_clk",
+			      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
 		protected-clocks = <GCC_AGGRE_NOC_ECPRI_DMA_CLK>,
 				<GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC>,
 				<GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC>,