diff --git a/qcom/Makefile b/qcom/Makefile index 8abfd129..bfae374a 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -65,6 +65,23 @@ cinder-dtb-$(CONFIG_ARCH_CINDER) += cinder-rumi.dtb \ cinder-ru-idp.dtb \ cinder-du-idp.dtb dtb-y += $(cinder-dtb-y) + +SA8155_BASE_DTB += sa8155.dtb sa8155-v2.dtb +SA8155P_BASE_DTB += sa8155p.dtb sa8155p-v2.dtb + +SA8155_BOARDS += \ + sa8155-adp-star-overlay.dtbo \ + sa8155-adp-air-overlay.dtbo + +SA8155P_BOARDS += \ + sa8155p-adp-star-overlay.dtbo \ + sa8155p-adp-air-overlay.dtbo + +gen3auto-dtb-$(CONFIG_ARCH_SA8155) += \ + $(call add-overlays, $(SA8155_BOARDS),$(SA8155_BASE_DTB))\ + $(call add-overlays, $(SA8155P_BOARDS),$(SA8155P_BASE_DTB)) +gen3auto-overlays-dtb-$(CONFIG_ARCH_SA8155) += $(SA8155_BOARDS) $(SA8155P_BOARDS) $(SA8155_BASE_DTB) $(SA8155P_BASE_DTB) +dtb-y += $(gen3auto-dtb-y) endif ifeq ($(CONFIG_ARCH_KALAMA), y) diff --git a/qcom/sa8155-adp-air-overlay.dts b/qcom/sa8155-adp-air-overlay.dts new file mode 100644 index 00000000..a342483d --- /dev/null +++ b/qcom/sa8155-adp-air-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "sa8155-adp-common.dtsi" + +/ { + model = "ADP-AIR"; + compatible = "qcom,sa8155-v2-adp-air", "qcom,sa8155", + "qcom,adp-air"; + qcom,board-id = <0X01000019 0>; +}; diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi new file mode 100644 index 00000000..79aa6b2a --- /dev/null +++ b/qcom/sa8155-adp-common.dtsi @@ -0,0 +1,7 @@ +#include +#include + +/* Empty node to generate minimal overlay fragment */ +&soc { + +}; diff --git a/qcom/sa8155-adp-star-overlay.dts b/qcom/sa8155-adp-star-overlay.dts new file mode 100644 index 00000000..13d64ac1 --- /dev/null +++ b/qcom/sa8155-adp-star-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "sa8155-adp-star.dtsi" + +/ { + model = "ADP-STAR"; + compatible = "qcom,sa8155-adp-star", "qcom,sa8155", + "qcom,adp-star"; + qcom,board-id = <25 0>; +}; diff --git a/qcom/sa8155-adp-star.dtsi b/qcom/sa8155-adp-star.dtsi new file mode 100644 index 00000000..3fd19bf8 --- /dev/null +++ b/qcom/sa8155-adp-star.dtsi @@ -0,0 +1 @@ +#include "sa8155-adp-common.dtsi" diff --git a/qcom/sa8155-v1.dtsi b/qcom/sa8155-v1.dtsi new file mode 100644 index 00000000..50d09d7a --- /dev/null +++ b/qcom/sa8155-v1.dtsi @@ -0,0 +1,9 @@ +#include "sm8150.dtsi" +#include "sa8155.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155"; + compatible = "qcom,sa8155"; + qcom,msm-name = "SA8155 V1"; + qcom,msm-id = <362 0x10000>; +}; diff --git a/qcom/sa8155-v2.dts b/qcom/sa8155-v2.dts new file mode 100644 index 00000000..d565663f --- /dev/null +++ b/qcom/sa8155-v2.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sa8155-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 v2 SoC"; + compatible = "qcom,sa8155"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/sa8155-v2.dtsi b/qcom/sa8155-v2.dtsi new file mode 100644 index 00000000..09d9488c --- /dev/null +++ b/qcom/sa8155-v2.dtsi @@ -0,0 +1,8 @@ +#include "sm8150-v2.dtsi" +#include "sa8155.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 V2"; + qcom,msm-name = "SA8155 V2"; + qcom,msm-id = <362 0x20000>; +}; diff --git a/qcom/sa8155.dts b/qcom/sa8155.dts new file mode 100644 index 00000000..85a8196c --- /dev/null +++ b/qcom/sa8155.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sa8155-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 SoC"; + compatible = "qcom,sa8155"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi new file mode 100644 index 00000000..bbfa0b09 --- /dev/null +++ b/qcom/sa8155.dtsi @@ -0,0 +1 @@ +#include diff --git a/qcom/sa8155p-adp-air-overlay.dts b/qcom/sa8155p-adp-air-overlay.dts new file mode 100644 index 00000000..57ac3cae --- /dev/null +++ b/qcom/sa8155p-adp-air-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "sa8155-adp-common.dtsi" + +/ { + model = "ADP-AIR"; + compatible = "qcom,sa8155p-v2-adp-air", "qcom,sa8155p", + "qcom,adp-air"; + qcom,board-id = <0x01000019 0>; +}; diff --git a/qcom/sa8155p-adp-star-overlay.dts b/qcom/sa8155p-adp-star-overlay.dts new file mode 100644 index 00000000..db8d3b48 --- /dev/null +++ b/qcom/sa8155p-adp-star-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "sa8155-adp-star.dtsi" + +/ { + model = "ADP-STAR"; + compatible = "qcom,sa8155p-adp-star", "qcom,sa8155p", + "qcom,adp-star"; + qcom,board-id = <25 0>; +}; diff --git a/qcom/sa8155p-v2.dts b/qcom/sa8155p-v2.dts new file mode 100644 index 00000000..57e5e093 --- /dev/null +++ b/qcom/sa8155p-v2.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sa8155p-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155P v2 SoC"; + compatible = "qcom,sa8155p"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/sa8155p-v2.dtsi b/qcom/sa8155p-v2.dtsi new file mode 100644 index 00000000..ae4368c6 --- /dev/null +++ b/qcom/sa8155p-v2.dtsi @@ -0,0 +1,7 @@ +#include "sa8155-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155P v2"; + qcom,msm-name = "SA8155P v2"; + qcom,msm-id = <367 0x20000>; +}; diff --git a/qcom/sa8155p.dts b/qcom/sa8155p.dts new file mode 100644 index 00000000..2b77e6fc --- /dev/null +++ b/qcom/sa8155p.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sa8155p.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155P SoC"; + compatible = "qcom,sa8155p"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/sa8155p.dtsi b/qcom/sa8155p.dtsi new file mode 100644 index 00000000..c5bce24b --- /dev/null +++ b/qcom/sa8155p.dtsi @@ -0,0 +1,8 @@ +#include "sa8155-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155P "; + qcom,msm-name = "SA8155P V1"; + compatible = "qcom,sa8155p"; + qcom,msm-id = <367 0x10000>; +}; diff --git a/qcom/sm8150-v2.dtsi b/qcom/sm8150-v2.dtsi new file mode 100644 index 00000000..3f6b99c9 --- /dev/null +++ b/qcom/sm8150-v2.dtsi @@ -0,0 +1,7 @@ +#include "sm8150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150 V2"; + qcom,msm-name = "SM8150 V2"; + qcom,msm-id = <339 0x20000>; +}; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi new file mode 100644 index 00000000..cf5d6c06 --- /dev/null +++ b/qcom/sm8150.dtsi @@ -0,0 +1,566 @@ +#include +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. SM8150"; + compatible = "qcom,sm8150"; + qcom,msm-name = "SM8150 V1"; + qcom,msm-id = <339 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + aliases { + serial0 = &uart2; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + i-cache-size = <0x8000>; + d-cache-size = <0x8000>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-size = <0x200000>; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + i-cache-size = <0x8000>; + d-cache-size = <0x8000>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + i-cache-size = <0x8000>; + d-cache-size = <0x8000>; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + i-cache-size = <0x8000>; + d-cache-size = <0x8000>; + next-level-cache = <&L2_3>; + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + next-level-cache = <&L2_4>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + next-level-cache = <&L2_6>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + next-level-cache = <&L2_7>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x80000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + }; + + cluster2 { + core0 { + cpu = <&CPU7>; + }; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + chosen { }; + + soc: soc { }; + + firmware: firmware { }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp_mem { + no-map; + reg = <0x0 0x85700000 0x0 0x600000>; + }; + + xbl_mem: xbl_mem { + no-map; + reg = <0x0 0x85e00000 0x0 0x100000>; + }; + + aop_mem: memory@85f00000 { + reg = <0x0 0x85f00000 0x0 0x20000>; + no-map; + }; + + aop_cmd_db: memory@85f20000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x85f20000 0x0 0x20000>; + no-map; + }; + + smem_region: smem { + no-map; + reg = <0x0 0x86000000 0x0 0x200000>; + }; + + removed_regions: removed_regions { + no-map; + reg = <0x0 0x86200000 0x0 0x5500000>; + }; + + pil_camera_mem: camera_region { + no-map; + reg = <0x0 0x8b700000 0x0 0x500000>; + }; + + pil_wlan_fw_mem: pil_wlan_fw_region { + no-map; + reg = <0x0 0x8bc00000 0x0 0x180000>; + }; + + pil_npu_mem: pil_npu_region { + no-map; + reg = <0x0 0x8bd80000 0x0 0x80000>; + }; + + pil_adsp_mem: pil_adsp_region { + no-map; + reg = <0x0 0x8be00000 0x0 0x1a00000>; + }; + + pil_modem_mem: modem_region { + no-map; + reg = <0x0 0x8d800000 0x0 0x9600000>; + }; + + pil_video_mem: pil_video_region { + no-map; + reg = <0x0 0x96e00000 0x0 0x500000>; + }; + + pil_slpi_mem: pil_slpi_region { + no-map; + reg = <0x0 0x97300000 0x0 0x1400000>; + }; + + pil_ipa_fw_mem: pil_ipa_fw_region { + no-map; + reg = <0x0 0x98700000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: pil_ipa_gsi_region { + no-map; + reg = <0x0 0x98710000 0x0 0x5000>; + }; + + pil_gpu_mem: pil_gpu_region { + no-map; + reg = <0x0 0x98715000 0x0 0x2000>; + }; + + pil_spss_mem: pil_spss_region { + no-map; + reg = <0x0 0x98800000 0x0 0x100000>; + }; + + pil_cdsp_mem: cdsp_regions { + no-map; + reg = <0x0 0x98900000 0x0 0x1400000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + no-map; + reg = <0x0 0x9e400000 0x0 0x1400000>; + }; + + cdsp_sec_mem: cdsp_sec_regions { + no-map; + reg = <0x0 0xa4c00000 0x0 0x3c00000>; + }; + + cont_splash_memory: cont_splash_region { + reg = <0x0 0x9c000000 0x0 0x2400000>; + label = "cont_splash_region"; + }; + + disp_rdump_memory: disp_rdump_region { + reg = <0x0 0x9c000000 0x0 0x02400000>; + label = "disp_rdump_region"; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + cdsp_mem: cdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; + + secure_display_memory: secure_display_region { /* Secure UI */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xA000000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x2400000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2800000>; + linux,cma-default; + }; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + }; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = ; + interrupt-parent = <&intc>; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + timer@17c20000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c20000 0x1000>; + clock-frequency = <19200000>; + + frame@17c21000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = ; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = ; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = ; + reg = <0x17c26000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = ; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = ; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = ; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + apps_rsc: rsc@18200000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x18200000 0x10000>, + <0x18210000 0x10000>, + <0x18220000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + rpmhcc: clock-controller { + compatible = "qcom,sm8150-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + status = "okay"; + }; + }; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sm8150"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + clock-names = "bi_tcxo", + "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + status = "ok"; + + uart2: serial@a90000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x00a90000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + status = "ok"; + }; + }; +}; diff --git a/qcom/sm8150p-v2.dtsi b/qcom/sm8150p-v2.dtsi new file mode 100644 index 00000000..19171ba4 --- /dev/null +++ b/qcom/sm8150p-v2.dtsi @@ -0,0 +1,7 @@ +#include "sm8150-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150P v2"; + qcom,msm-name = "SM8150P v2"; + qcom,msm-id = <361 0x20000>; +}; diff --git a/qcom/sm8150p.dtsi b/qcom/sm8150p.dtsi new file mode 100644 index 00000000..c80c56a3 --- /dev/null +++ b/qcom/sm8150p.dtsi @@ -0,0 +1,7 @@ +#include "sm8150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150P v1"; + qcom,msm-name = "SM8150P v1"; + qcom,msm-id = <361 0x10000>; +};