diff --git a/qcom/Makefile b/qcom/Makefile index 63beddda..e7ff7a6f 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -65,6 +65,23 @@ kalama-dtb-$(CONFIG_ARCH_KALAMA) += \ kalama-overlays-dtb-$(CONFIG_ARCH_KALAMA) += $(KALAMA_BOARDS) $(NOAPQ_KALAMA_BOARDS) $(KALAMA_BASE_DTB) $(KALAMA_APQ_BASE_DTB) dtb-y += $(kalama-dtb-y) +KHAJE_BASE_DTB += khaje.dtb + +KHAJE_BOARDS += \ + khaje-idp-overlay.dtbo \ + khaje-qrd-overlay.dtbo \ + khaje-qrd-hvdcp3p5-overlay.dtbo \ + khaje-qrd-nowcd9375-overlay.dtbo \ + khaje-idp-nopmi-overlay.dtbo \ + khaje-qrd-nopmi-overlay.dtbo \ + khaje-idps-display-90hz-overlay.dtbo \ + khaje-atp-overlay.dtbo + +khaje-dtb-$(CONFIG_ARCH_KHAJE) += \ + $(call add-overlays, $(KHAJE_BOARDS) ,$(KHAJE_BASE_DTB)) +khaje-overlays-dtb-$(CONFIG_ARCH_KHAJE) += $(KHAJE_BOARDS) $(KHAJE_BASE_DTB) +dtb-y += $(khaje-dtb-y) + cinder-dtb-$(CONFIG_ARCH_CINDER) += cinder-rumi.dtb \ cinder-ru-idp.dtb \ cinder-du-idp.dtb \ diff --git a/qcom/bengal-coresight.dtsi b/qcom/bengal-coresight.dtsi new file mode 100644 index 00000000..5bd4d1dd --- /dev/null +++ b/qcom/bengal-coresight.dtsi @@ -0,0 +1,1767 @@ +&soc { + hwevent { + compatible = "qcom,coresight-hwevent"; + + coresight-name = "coresight-hwevent"; + coresight-csr = <&csr>; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + apss_tgu: tgu@9900000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b999>; + reg = <0x09900000 0x1000>; + reg-names = "tgu-base"; + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <8>; + tgu-timer-counters = <8>; + interrupts = <0 53 1>, <0 54 1>, <0 55 1>, <0 56 1>; + coresight-name = "coresight-tgu-apss"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + csr: csr@8001000 { + compatible = "qcom,coresight-csr"; + reg = <0x8001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + qcom,usb-bam-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + + qcom,blk-size = <1>; + }; + + swao_csr: csr@8a03000 { + compatible = "qcom,coresight-csr"; + reg = <0x8a03000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-swao-csr"; + + qcom,timestamp-support; + qcom,aodbg-csr-support; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,blk-size = <1>; + }; + + stm: stm@8002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb962>; + + reg = <0x8002000 0x1000>, + <0xe280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + coresight-name = "coresight-stm"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + nvmem-cells = <&stm_debug_fuse>; + nvmem-cell-names = "debug_fuse"; + + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + + }; + + tpdm_center: tpdm@8b58000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8b58000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-center"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_dl_ct_out_tpda0: endpoint { + remote-endpoint = + <&tpda0_in_tpdm_dl_ct>; + }; + }; + }; + + tpdm_gpu: tpdm@8940000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8940000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-gpu"; + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_gpu_out_funnel_gpu: endpoint { + remote-endpoint = + <&funnel_gpu_in_tpdm_gpu>; + }; + }; + }; + + modem_rfxe: modem_rfxe { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-modem-rfxe"; + qcom,dummy-source; + + port { + modem_rxfe_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_modem_rxfe>; + }; + }; + }; + + audio_etm0: audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-audio-etm0"; + + qcom,inst-id = <5>; + + port { + audio_etm0_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_audio_etm0>; + }; + }; + }; + + snoc: snoc { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-snoc"; + qcom,dummy-source; + + port { + snoc_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_snoc>; + }; + }; + }; + + tpdm_lpass: tpdm@8a26000 { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpdm-lpass"; + qcom,dummy-source; + + port { + tpdm_lpass_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpdm_lpass>; + }; + }; + }; + + tpdm_turing: tpdm@8860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8860000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-turing"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_turing_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_tpdm_turing>; + }; + }; + }; + + turing_etm0: turing_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-turing-etm0"; + + qcom,inst-id = <13>; + + port { + turing_etm0_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_turing_etm0>; + }; + }; + }; + + tpdm_vsense: tpdm@8840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8840000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-vsense"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_vsense_out_tpda7: endpoint { + remote-endpoint = + <&tpda7_in_tpdm_vsense>; + }; + }; + }; + + tpdm_dcc: tpdm@8870000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8870000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dcc"; + + qcom,hw-enable-check; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_dcc_out_tpda8: endpoint { + remote-endpoint = + <&tpda8_in_tpdm_dcc>; + }; + }; + }; + + tpdm_prng: tpdm@884c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x884c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-prng"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_prng_out_tpda10: endpoint { + remote-endpoint = + <&tpda10_in_tpdm_prng>; + }; + }; + }; + + tpdm_qm: tpdm@89d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x89d0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-qm"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_qm_out_tpda12: endpoint { + remote-endpoint = + <&tpda12_in_tpdm_qm>; + }; + }; + }; + + tpdm_west: tpdm@8a58000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8a58000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-west"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_west_out_tpda13: endpoint { + remote-endpoint = + <&tpda13_in_tpdm_west>; + }; + }; + }; + + tpdm_pimem: tpdm@8850000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8850000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-pimem"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_pimem_out_tpda15: endpoint { + remote-endpoint = + <&tpda15_in_tpdm_pimem>; + }; + }; + }; + + tpdm_mapss: tpdm@8a01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8a01000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-mapss"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_mapss_out_tpda_mapss: endpoint { + remote-endpoint = + <&tpda_mapss_in_tpdm_mapss>; + }; + }; + }; + + tpdm_wcss: tpdm@899c000 { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpdm-wcss"; + qcom,dummy-source; + + port { + tpdm_wcss_silver_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_tpdm_wcss_silver>; + }; + }; + }; + + modem_etm0: modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-modem-etm0"; + + qcom,inst-id = <2>; + + port { + modem_etm0_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_modem_etm0>; + }; + }; + }; + + etm0: etm@9040000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x9040000 0x1000>; + cpu = <&CPU0>; + qcom,tupwr-disable; + coresight-name = "coresight-etm0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm0_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_etm0>; + }; + }; + }; + + etm1: etm@9140000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x9140000 0x1000>; + cpu = <&CPU1>; + qcom,tupwr-disable; + coresight-name = "coresight-etm1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm1_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_etm1>; + }; + }; + }; + + etm2: etm@9240000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x9240000 0x1000>; + cpu = <&CPU2>; + qcom,tupwr-disable; + coresight-name = "coresight-etm2"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm2_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_etm2>; + }; + }; + }; + + etm3: etm@9340000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x9340000 0x1000>; + cpu = <&CPU3>; + qcom,tupwr-disable; + coresight-name = "coresight-etm3"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm3_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_etm3>; + }; + }; + }; + + etm4: etm@9440000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x9440000 0x1000>; + cpu = <&CPU4>; + qcom,tupwr-disable; + coresight-name = "coresight-etm4"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm4_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_etm4>; + }; + }; + }; + + etm5: etm@9540000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x9540000 0x1000>; + cpu = <&CPU5>; + qcom,tupwr-disable; + coresight-name = "coresight-etm5"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm5_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_etm5>; + }; + }; + }; + + etm6: etm@9640000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x9640000 0x1000>; + cpu = <&CPU6>; + qcom,tupwr-disable; + coresight-name = "coresight-etm6"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm6_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_etm6>; + }; + }; + }; + + etm7: etm@9740000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x9740000 0x1000>; + cpu = <&CPU7>; + qcom,tupwr-disable; + coresight-name = "coresight-etm7"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm7_out_funnel_apss0: endpoint { + remote-endpoint = + <&funnel_apss0_in_etm7>; + }; + }; + }; + + tpdm_actpm: tpd@9830000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x9830000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-actpm"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_actpm_out_tpda_actpm: endpoint { + remote-endpoint = + <&tpda_actpm_in_tpdm_actpm>; + }; + }; + }; + + tpdm_llm_silver: tpdm@98a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x98a0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-silver"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_llm_silver_out_tpda_llm_silver: endpoint { + remote-endpoint = + <&tpda_llm_silver_in_tpdm_llm_silver>; + }; + }; + }; + + tpdm_apss: tpdm@9860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x9860000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-apss"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_apss_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_apss>; + }; + }; + }; + + funnel_apss0: funnel@9800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x9800000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_apss0_out_funnel_apss1: endpoint { + remote-endpoint = + <&funnel_apss1_in_funnel_apss0>; + }; + }; + + port@1 { + reg = <0>; + funnel_apss0_in_etm0: endpoint { + slave-mode; + remote-endpoint = + <&etm0_out_funnel_apss0>; + }; + }; + + port@2 { + reg = <1>; + funnel_apss0_in_etm1: endpoint { + slave-mode; + remote-endpoint = + <&etm1_out_funnel_apss0>; + }; + }; + + port@3 { + reg = <2>; + funnel_apss0_in_etm2: endpoint { + slave-mode; + remote-endpoint = + <&etm2_out_funnel_apss0>; + }; + }; + + port@4 { + reg = <3>; + funnel_apss0_in_etm3: endpoint { + slave-mode; + remote-endpoint = + <&etm3_out_funnel_apss0>; + }; + }; + + port@5 { + reg = <4>; + funnel_apss0_in_etm4: endpoint { + slave-mode; + remote-endpoint = + <&etm4_out_funnel_apss0>; + }; + }; + + port@6 { + reg = <5>; + funnel_apss0_in_etm5: endpoint { + slave-mode; + remote-endpoint = + <&etm5_out_funnel_apss0>; + }; + }; + + port@7 { + reg = <6>; + funnel_apss0_in_etm6: endpoint { + slave-mode; + remote-endpoint = + <&etm6_out_funnel_apss0>; + }; + }; + + port@8 { + reg = <7>; + funnel_apss0_in_etm7: endpoint { + slave-mode; + remote-endpoint = + <&etm7_out_funnel_apss0>; + }; + }; + + }; + }; + + tpda_actpm: tpda@9832000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x9832000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-actpm"; + + qcom,tpda-atid = <77>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_actpm_out_funnel_apss1: endpoint { + remote-endpoint = + <&funnel_apss1_in_tpda_actpm>; + }; + }; + + port@1 { + reg = <0>; + tpda_actpm_in_tpdm_actpm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_actpm_out_tpda_actpm>; + }; + }; + }; + }; + + tpda_apss: tpda@9862000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x9862000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-apss"; + + + qcom,tpda-atid = <66>; + qcom,dsb-elem-size = <0 32>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_apss_out_funnel_apss1: endpoint { + remote-endpoint = + <&funnel_apss1_in_tpda_apss>; + }; + }; + + port@1 { + reg = <0>; + tpda_apss_in_tpdm_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_apss_out_tpda_apss>; + }; + }; + }; + }; + + + tpda_llm_silver: tpda@98c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x98c0000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-llm-silver"; + + qcom,tpda-atid = <72>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_llm_silver_out_funnel_apss1: endpoint { + remote-endpoint = + <&funnel_apss1_in_tpda_llm_silver>; + }; + }; + + port@1 { + reg = <0>; + tpda_llm_silver_in_tpdm_llm_silver: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_llm_silver_out_tpda_llm_silver>; + }; + }; + }; + }; + + + funnel_apss1: funnel@9810000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x9810000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_apss1_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_apss1>; + }; + }; + + port@1 { + reg = <0>; + funnel_apss1_in_funnel_apss0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss0_out_funnel_apss1>; + }; + }; + + port@2 { + reg = <2>; + funnel_apss1_in_tpda_actpm: endpoint { + slave-mode; + remote-endpoint = + <&tpda_actpm_out_funnel_apss1>; + }; + }; + + port@3 { + reg = <3>; + funnel_apss1_in_tpda_llm_silver: endpoint { + slave-mode; + remote-endpoint = + <&tpda_llm_silver_out_funnel_apss1>; + }; + }; + + port@4 { + reg = <4>; + funnel_apss1_in_tpda_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_apss_out_funnel_apss1>; + }; + }; + + }; + }; + + tpda_mapss: tpda@8a04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x8a04000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-mapss"; + + qcom,tpda-atid = <76>; + qcom,cmb-elem-size = <0 32>; + qcom,dsb-elem-size = <0 32>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_mapss_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_tpda_mapss>; + }; + }; + + port@1 { + reg = <0>; + tpda_mapss_in_tpdm_mapss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_mapss_out_tpda_mapss>; + }; + }; + }; + }; + + funnel_gpu: funnel@8944000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x8944000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-gpu"; + status = "disabled"; + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_gpu_out_tpda1: endpoint { + remote-endpoint = + <&tpda1_in_funnel_gpu>; + }; + }; + + port@1 { + reg = <0>; + funnel_gpu_in_tpdm_gpu: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_gpu_out_funnel_gpu>; + }; + }; + + }; + }; + + funnel_turing: funnel@8861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x8861000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-turing"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_turing_out_tpda5: endpoint { + remote-endpoint = + <&tpda5_in_funnel_turing>; + source = <&tpdm_turing>; + }; + }; + + port@1 { + reg = <1>; + funnel_turing_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_funnel_turing>; + source = <&turing_etm0>; + }; + }; + + port@2 { + reg = <0>; + funnel_turing_in_tpdm_turing: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_turing_out_funnel_turing>; + }; + }; + + port@3 { + reg = <1>; + funnel_turing_in_turing_etm0: endpoint { + slave-mode; + remote-endpoint = + <&turing_etm0_out_funnel_turing>; + }; + }; + + }; + }; + + tpda: tpda@8004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x8004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <65>; + qcom,dsb-elem-size = <0 32>, + <1 32>, + <5 32>, + <12 32>, + <13 32>, + <15 32>; + qcom,cmb-elem-size = <7 32>, + <8 32>, + <10 32>, + <15 64>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpda>; + }; + }; + + port@1 { + reg = <0>; + tpda0_in_tpdm_dl_ct: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dl_ct_out_tpda0>; + }; + }; + + port@2 { + reg = <1>; + tpda1_in_funnel_gpu: endpoint { + slave-mode; + remote-endpoint = + <&funnel_gpu_out_tpda1>; + }; + }; + + port@3 { + reg = <5>; + tpda5_in_funnel_turing: endpoint { + slave-mode; + remote-endpoint = + <&funnel_turing_out_tpda5>; + }; + }; + + port@4 { + reg = <7>; + tpda7_in_tpdm_vsense: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_vsense_out_tpda7>; + }; + }; + + port@5 { + reg = <8>; + tpda8_in_tpdm_dcc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dcc_out_tpda8>; + }; + }; + + port@6 { + reg = <10>; + tpda10_in_tpdm_prng: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_prng_out_tpda10>; + }; + }; + + port@7 { + reg = <12>; + tpda12_in_tpdm_qm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_qm_out_tpda12>; + }; + }; + + port@8 { + reg = <13>; + tpda13_in_tpdm_west: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_west_out_tpda13>; + }; + }; + + port@9 { + reg = <15>; + tpda15_in_tpdm_pimem: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_pimem_out_tpda15>; + }; + }; + + }; + }; + + funnel_qatb: funnel@8005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x8005000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qatb"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_qatb>; + }; + }; + + port@1 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + slave-mode; + remote-endpoint = + <&tpda_out_funnel_qatb>; + }; + }; + + port@2 { + reg = <6>; + funnel_qatb_in_funnel_turing: endpoint { + slave-mode; + remote-endpoint = + <&funnel_turing_out_funnel_qatb>; + }; + }; + + port@3 { + reg = <5>; + funnel_qatb_in_tpdm_lpass: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_lpass_out_funnel_qatb>; + }; + }; + + port@4 { + reg = <5>; + funnel_qatb_in_audio_etm0: endpoint { + slave-mode; + remote-endpoint = + <&audio_etm0_out_funnel_qatb>; + }; + }; + }; + }; + + funnel_in0: funnel@8041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x8041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_in0_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in0>; + }; + }; + + port@1 { + reg = <5>; + funnel_in0_in_snoc: endpoint { + slave-mode; + remote-endpoint = + <&snoc_out_funnel_in0>; + }; + }; + + port@2 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_qatb_out_funnel_in0>; + }; + }; + + port@3 { + reg = <7>; + funnel_in0_in_stm: endpoint { + slave-mode; + remote-endpoint = + <&stm_out_funnel_in0>; + }; + }; + + }; + }; + + funnel_in1: funnel@8042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x8042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_in1_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in1>; + }; + }; + + port@1 { + reg = <1>; + funnel_in1_in_tpda_mapss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_mapss_out_funnel_in1>; + }; + }; + + port@2 { + reg = <2>; + funnel_in1_in_modem_rxfe: endpoint { + slave-mode; + remote-endpoint = + <&modem_rxfe_out_funnel_in1>; + }; + }; + + port@3 { + reg = <3>; + funnel_in1_in_tpdm_wcss_silver: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_wcss_silver_out_funnel_in1>; + }; + }; + + port@4 { + reg = <4>; + funnel_in1_in_modem_etm0: endpoint { + slave-mode; + remote-endpoint = + <&modem_etm0_out_funnel_in1>; + }; + }; + + port@5 { + reg = <6>; + funnel_in1_in_funnel_apss1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss1_out_funnel_in1>; + }; + }; + + }; + }; + + funnel_merg: funnel@8045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x8045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merg"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_merg_out_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_merg>; + }; + }; + + port@1 { + reg = <0>; + funnel_merg_in_funnel_in0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in0_out_funnel_merg>; + }; + }; + + port@2 { + reg = <1>; + funnel_merg_in_funnel_in1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in1_out_funnel_merg>; + }; + }; + + }; + }; + + tmc_etf: tmc@8047000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x8047000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + coresight-ctis = <&cti0>; + coresight-csr = <&csr>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tmc_etf_out_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_in_tmc_etf>; + }; + }; + + port@1 { + reg = <0>; + tmc_etf_in_funnel_merg: endpoint { + slave-mode; + remote-endpoint = + <&funnel_merg_out_tmc_etf>; + }; + }; + + }; + }; + + replicator_qdss: replicator@8046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x8046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-qdss"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + replicator_qdss_out_tmc_etr: endpoint { + remote-endpoint = + <&tmc_etr_in_replicator_qdss>; + }; + }; + + port@1 { + reg = <0>; + replicator_qdss_in_tmc_etf: endpoint { + slave-mode; + remote-endpoint = + <&tmc_etf_out_replicator_qdss>; + }; + }; + + }; + }; + + tmc_etr: tmc@8048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x8048000 0x1000>, + <0x8064000 0x15000>; + reg-names = "tmc-base","bam-base"; + + coresight-name = "coresight-tmc-etr"; + + + iommus = <&apps_smmu 0x0180 0>, + <&apps_smmu 0x0160 0>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + arm,buffer-size = <0x400000>; + arm,scatter-gather; + + coresight-ctis = <&cti0>; + coresight-csr = <&csr>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tmc_etr_in_replicator_qdss: endpoint { + slave-mode; + remote-endpoint = + <&replicator_qdss_out_tmc_etr>; + }; + }; + + }; + }; + + cti_cortex_M3: cti@8B30000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8B30000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cortex_M3"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_apss_cti0: cti@98E0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x98E0000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss-cti0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_apss_cti1: cti@98F0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x98F0000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss-cti1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_wcss_cti0: cti@89A4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x89A4000 0x1000>; + reg-names = "cti-base"; + status = "disabled"; + coresight-name = "coresight-cti-wcss-cti0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_wcss_cti1: cti@89A5000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x89A5000 0x1000>; + reg-names = "cti-base"; + status = "disabled"; + coresight-name = "coresight-cti-wcss-cti1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_wcss_cti2: cti@89A6000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x89A6000 0x1000>; + reg-names = "cti-base"; + status = "disabled"; + coresight-name = "coresight-cti-wcss-cti2"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_lpass_q6: cti@8A21000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8A21000 0x1000>; + reg-names = "cti-base"; + + status = "disabled"; + coresight-name = "coresight-cti-lpass-q6"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_turing_q6: cti@8867000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8867000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-turing-q6"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_mss_q6: cti@8833000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8833000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-mss-q6"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_isdb_gpu: cti@8941000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8941000 0x1000>; + reg-names = "cti-base"; + status = "disabled"; + coresight-name = "coresight-cti-isdb-gpu"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_mapss: cti@8A02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8A02000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-mapss"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dlct_cti0: cti@8B59000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8B59000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct-cti0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dlct_cti1: cti@8B5A000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8B5A000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct-cti1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dlct_cti2: cti@8B5B000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8B5B000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct-cti2"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dlct_cti3: cti@8B5C000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8B5C000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct-cti3"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0: cti@8010000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1: cti@8011000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti10: cti@801a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x801a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti11: cti@801b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x801b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti12: cti@801c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x801c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti13: cti@801d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x801d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti14: cti@801e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x801e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti15: cti@801f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x801f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2: cti@8012000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti3: cti@8013000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti4: cti@8014000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti5: cti@8015000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti6: cti@8016000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti7: cti@8017000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti8: cti@8018000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti9: cti@8019000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + +}; diff --git a/qcom/bengal-gdsc.dtsi b/qcom/bengal-gdsc.dtsi new file mode 100644 index 00000000..16c1a0a7 --- /dev/null +++ b/qcom/bengal-gdsc.dtsi @@ -0,0 +1,115 @@ +&soc { + /* GDSCs in GCC */ + gcc_camss_top_gdsc: qcom,gdsc@1458004 { + compatible = "qcom,gdsc"; + reg = <0x1458004 0x4>; + regulator-name = "gcc_camss_top_gdsc"; + status = "disabled"; + }; + + gcc_ufs_phy_gdsc: qcom,gdsc@1445004 { + compatible = "qcom,gdsc"; + reg = <0x1445004 0x4>; + regulator-name = "gcc_ufs_phy_gdsc"; + status = "disabled"; + }; + + gcc_usb30_prim_gdsc: qcom,gdsc@141a004 { + compatible = "qcom,gdsc"; + reg = <0x141a004 0x4>; + regulator-name = "gcc_usb30_prim_gdsc"; + status = "disabled"; + }; + + gcc_vcodec0_gdsc: qcom,gdsc@1458098 { + compatible = "qcom,gdsc"; + reg = <0x1458098 0x4>; + regulator-name = "gcc_vcodec0_gdsc"; + status = "disabled"; + }; + + gcc_venus_gdsc: qcom,gdsc@145807c { + compatible = "qcom,gdsc"; + reg = <0x145807c 0x4>; + regulator-name = "gcc_venus_gdsc"; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@147d060 { + compatible = "qcom,gdsc"; + reg = <0x147d060 0x4>; + regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@147d07c { + compatible = "qcom,gdsc"; + reg = <0x147d07c 0x4>; + regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 { + compatible = "qcom,gdsc"; + reg = <0x147d074 0x4>; + regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 { + compatible = "qcom,gdsc"; + reg = <0x147d078 0x4>; + regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + /* GDSCs in DISPCC */ + mdss_core_gdsc: qcom,gdsc@5f03000 { + compatible = "qcom,gdsc"; + reg = <0x5f03000 0x4>; + regulator-name = "mdss_core_gdsc"; + proxy-supply = <&mdss_core_gdsc>; + qcom,proxy-consumer-enable; + status = "disabled"; + }; + + /* GDSCs in GPUCC */ + gpu_gx_domain_addr: syscon@5991508 { + compatible = "syscon"; + reg = <0x5991508 0x4>; + }; + + gpu_cx_hw_ctrl: syscon@5991540 { + compatible = "syscon"; + reg = <0x5991540 0x4>; + }; + + gpu_gx_sw_reset: syscon@5991008 { + compatible = "syscon"; + reg = <0x5991008 0x4>; + }; + + gpu_cx_gdsc: qcom,gdsc@599106c { + compatible = "qcom,gdsc"; + reg = <0x599106c 0x4>; + regulator-name = "gpu_cx_gdsc"; + hw-ctrl-addr = <&gpu_cx_hw_ctrl>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + qcom,clk-dis-wait-val = <8>; + status = "disabled"; + }; + + gpu_gx_gdsc: qcom,gdsc@599100c { + compatible = "qcom,gdsc"; + reg = <0x599100c 0x4>; + regulator-name = "gpu_gx_gdsc"; + sw-reset = <&gpu_gx_sw_reset>; + domain-addr = <&gpu_gx_domain_addr>; + status = "disabled"; + }; +}; diff --git a/qcom/bengal-pinctrl.dtsi b/qcom/bengal-pinctrl.dtsi new file mode 100644 index 00000000..b3834ded --- /dev/null +++ b/qcom/bengal-pinctrl.dtsi @@ -0,0 +1,1196 @@ +&soc { + tlmm: pinctrl@400000 { + compatible = "qcom,bengal-pinctrl"; + reg = <0x400000 0xc00000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + irqdomain-map = <0 0 &wakegpio 84 0>, + <3 0 &wakegpio 75 0>, + <4 0 &wakegpio 16 0>, + <6 0 &wakegpio 59 0>, + <8 0 &wakegpio 63 0>, + <11 0 &wakegpio 17 0>, + <13 0 &wakegpio 18 0>, + <14 0 &wakegpio 51 0>, + <17 0 &wakegpio 20 0>, + <18 0 &wakegpio 52 0>, + <19 0 &wakegpio 53 0>, + <24 0 &wakegpio 6 0>, + <25 0 &wakegpio 71 0>, + <27 0 &wakegpio 73 0>, + <28 0 &wakegpio 41 0>, + <31 0 &wakegpio 27 0>, + <32 0 &wakegpio 54 0>, + <33 0 &wakegpio 55 0>, + <34 0 &wakegpio 56 0>, + <35 0 &wakegpio 57 0>, + <36 0 &wakegpio 58 0>, + <39 0 &wakegpio 28 0>, + <46 0 &wakegpio 29 0>, + <62 0 &wakegpio 60 0>, + <63 0 &wakegpio 61 0>, + <64 0 &wakegpio 62 0>, + <65 0 &wakegpio 30 0>, + <66 0 &wakegpio 31 0>, + <67 0 &wakegpio 32 0>, + <69 0 &wakegpio 33 0>, + <70 0 &wakegpio 34 0>, + <72 0 &wakegpio 72 0>, + <75 0 &wakegpio 35 0>, + <79 0 &wakegpio 36 0>, + <80 0 &wakegpio 21 0>, + <81 0 &wakegpio 38 0>, + <83 0 &wakegpio 9 0>, + <84 0 &wakegpio 39 0>, + <85 0 &wakegpio 40 0>, + <86 0 &wakegpio 19 0>, + <87 0 &wakegpio 42 0>, + <88 0 &wakegpio 43 0>, + <89 0 &wakegpio 45 0>, + <91 0 &wakegpio 74 0>, + <93 0 &wakegpio 46 0>, + <94 0 &wakegpio 47 0>, + <95 0 &wakegpio 48 0>, + <96 0 &wakegpio 49 0>, + <97 0 &wakegpio 50 0>, + <99 0 &wakegpio 64 0>, /* LPI_GPIO 7 */ + <102 0 &wakegpio 65 0>, /* LPI_GPIO 10 */ + <103 0 &wakegpio 66 0>, /* LPI_GPIO 11 */ + <104 0 &wakegpio 67 0>, /* LPI_GPIO 12 */ + <105 0 &wakegpio 69 0>, /* LPI_GPIO 17 */ + <106 0 &wakegpio 14 0>, /* LPI_GPIO 16 */ + <107 0 &wakegpio 7 0>, /* LPI_GPIO 17 */ + <109 0 &wakegpio 37 0>, /* LPI_GPIO 19 */ + <112 0 &wakegpio 25 0>; /* LPI_GPIO 24 */ + irqdomain-map-pass-thru = <0 0xff>; + irqdomain-map-mask = <0xff 0>; + + ufs_dev_reset_assert: ufs_dev_reset_assert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + + /* SDC pin type */ + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_rclk_on: sdc1_rclk_on { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc1_rclk_off: sdc1_rclk_off { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_on: cd_on { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_cd_off: cd_off { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + + tb_trig1_on: tb_trig1_on { + mux { + pins = "gpio19"; + function = "SDC1_TB"; + }; + + config { + pins = "gpio19"; + bias-pull-up; /* PULL UP */ + drive-strength = <8>; /* 8 MA */ + input-enable; + }; + }; + + /* WSA speaker reset pin1 */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio106"; + function = "gpio"; + }; + + config { + pins = "gpio106"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio106"; + function = "gpio"; + }; + + config { + pins = "gpio106"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + wcd937x_reset_active: wcd937x_reset_active { + mux { + pins = "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio92"; + drive-strength = <16>; + output-high; + }; + }; + + wcd937x_reset_sleep: wcd937x_reset_sleep { + mux { + pins = "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio92"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + + qupv3_se4_2uart_pins: qupv3_se4_2uart_pins { + qupv3_se4_2uart_active: qupv3_se4_2uart_active { + mux { + pins = "gpio12", "gpio13"; + function = "qup4"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se3_4uart_pins: qupv3_se3_4uart_pins { + qupv3_se3_default_ctsrtsrx: + qupv3_se3_default_ctsrtsrx { + mux { + pins = "gpio8", "gpio9", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_default_tx: + qupv3_se3_default_tx { + mux { + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_ctsrx: qupv3_se3_ctsrx { + mux { + pins = "gpio8", "gpio11"; + function = "qup3"; + }; + + config { + pins = "gpio8", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_rts: qupv3_se3_rts { + mux { + pins = "gpio9"; + function = "qup3"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_tx: qupv3_se3_tx { + mux { + pins = "gpio10"; + function = "qup3"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup0"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio4", "gpio5"; + function = "qup1"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 70 NFC Read Interrupt */ + pins = "gpio70"; + function = "gpio"; + }; + + config { + pins = "gpio70"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 70 NFC Read Interrupt */ + pins = "gpio70"; + function = "gpio"; + }; + + config { + pins = "gpio70"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* 69: Enable 31: Firmware */ + pins = "gpio69", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio69", "gpio31"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* 69: Enable 31: Firmware */ + pins = "gpio69", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio69", "gpio31"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active: nfc_clk_req_active { + /* active state */ + mux { + /* GPIO 86: NFC CLOCK REQUEST */ + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend: nfc_clk_req_suspend { + /* sleep state */ + mux { + /* GPIO 86: NFC CLOCK REQUEST */ + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio6", "gpio7"; + function = "qup2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "qup0"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_active: qupv3_se1_spi_active { + mux { + pins = "gpio4", "gpio5", + "gpio69", "gpio70"; + function = "qup1"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio69", "gpio70"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio69", "gpio70"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio69", "gpio70"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_active: qupv3_se5_spi_active { + mux { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + function = "qup5"; + }; + + config { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA*/ + pins = "gpio23", "gpio22"; + function = "cci_i2c"; + }; + + config { + pins = "gpio23", "gpio22"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_active: cci0_active { + mux { + /* CLK, DATA*/ + pins = "gpio23", "gpio22"; + function = "cci_i2c"; + }; + + config { + pins = "gpio23", "gpio22"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA*/ + pins = "gpio30", "gpio29"; + function = "cci_i2c"; + }; + + config { + pins = "gpio30", "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA*/ + pins = "gpio30", "gpio29"; + function = "cci_i2c"; + }; + + config { + pins = "gpio30", "gpio29"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK 0*/ + mux { + pins = "gpio20"; + function = "cam_mclk"; + }; + + config { + pins = "gpio20"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK 0*/ + mux { + pins = "gpio20"; + function = "cam_mclk"; + }; + + config { + pins = "gpio20"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK 1*/ + mux { + pins = "gpio21"; + function = "cam_mclk"; + }; + + config { + pins = "gpio21"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK 1*/ + mux { + pins = "gpio21"; + function = "cam_mclk"; + }; + + config { + pins = "gpio21"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK 2*/ + mux { + pins = "gpio27"; + function = "cam_mclk"; + }; + + config { + pins = "gpio27"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK 2*/ + mux { + pins = "gpio27"; + function = "cam_mclk"; + }; + + config { + pins = "gpio27"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK 3*/ + mux { + pins = "gpio28"; + function = "cam_mclk"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK 3*/ + mux { + pins = "gpio28"; + function = "cam_mclk"; + }; + + config { + pins = "gpio28"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear0_reset_active: cam_sensor_rear0_reset_active { + /* RESET0 */ + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear0_reset_suspend: cam_sensor_rear0_reset_suspend { + /* RESET0 */ + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_rear1_reset_active: cam_sensor_rear1_reset_active { + /* RESET1 */ + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear1_reset_suspend: cam_sensor_rear1_reset_suspend { + /* RESET1 */ + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_rear2_reset_active: cam_sensor_rear2_reset_active { + /* RESET2 */ + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear2_reset_suspend: cam_sensor_rear2_reset_suspend { + /* RESET2 */ + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_front0_reset_active: cam_sensor_front0_reset_active { + /* RESET0 */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front0_reset_suspend: cam_sensor_front0_reset_suspend { + /* RESET0 */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_csi_mux_oe_active: cam_sensor_csi_mux_oe_active { + /*CSIMUX_OE*/ + mux { + pins = "gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio66"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_csi_mux_oe_suspend: cam_sensor_csi_mux_oe_suspend { + /* CSIMUX_OE */ + mux { + pins = "gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio66"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_csi_mux_sel_active: cam_sensor_csi_mux_sel_active { + /*CSIMUX_SEL*/ + mux { + pins = "gpio67"; + function = "gpio"; + }; + + config { + pins = "gpio67"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_csi_mux_sel_suspend: cam_sensor_csi_mux_sel_suspend { + /* CSIMUX_SEL */ + mux { + pins = "gpio67"; + function = "gpio"; + }; + + config { + pins = "gpio67"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio82"; + function = "gpio"; + }; + + config { + pins = "gpio82"; + drive-strength = <8>; + bias-disable = <0>; + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio82"; + function = "gpio"; + }; + + config { + pins = "gpio82"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio81"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio81"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_int_active { + ts_int_active: ts_int_active { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_reset_active { + ts_reset_active: ts_reset_active { + mux { + pins = "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio71"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio71"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio80", "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio80", "gpio71"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pm8008_active: pm8008_active { + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-pull-up; + output-high; + drive-strength = <2>; + }; + }; + + pm8008_interrupt: pm8008_interrupt { + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; + input-enable; + }; + }; + }; +}; diff --git a/qcom/bengal-qupv3.dtsi b/qcom/bengal-qupv3.dtsi new file mode 100644 index 00000000..ff1660e2 --- /dev/null +++ b/qcom/bengal-qupv3.dtsi @@ -0,0 +1,198 @@ + +&soc { + + /* GPI Instance */ + gpi_dma0: qcom,gpi-dma@4a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x4a00000 0x60000>; + reg-names = "gpi-top"; + interrupts = , + , + , + , + , + , + , + , + , + ; + qcom,max-num-gpii = <10>; + qcom,gpii-mask = <0xf>; + qcom,ev-factor = <2>; + iommus = <&apps_smmu 0xf6 0x0>; + qcom,gpi-ee-offset = <0x10000>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + status = "ok"; + }; + + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x4ac0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + ranges; + status = "ok"; + + /* Debug UART Instance */ + qupv3_se4_2uart: qcom,qup_uart@4a90000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x4a90000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_2uart_active>; + pinctrl-1 = <&qupv3_se4_2uart_sleep>; + + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* HS UART Instance */ + qupv3_se3_4uart: qcom,qup_uart@4a8c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x4a8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default", "active", "sleep"; + interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 11 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qupv3_se3_default_ctsrtsrx>, + <&qupv3_se3_default_tx>; + pinctrl-1 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>, + <&qupv3_se3_tx>; + pinctrl-2 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>, + <&qupv3_se3_tx>; + qcom,wrapper-core = <&qupv3_0>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + /* I2C Instance */ + qupv3_se0_i2c: i2c@4a80000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* I2C Instance */ + qupv3_se1_i2c: i2c@4a84000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + dmas = <&gpi_dma0 0 1 3 64 0>, + <&gpi_dma0 1 1 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* I2C Instance */ + qupv3_se2_i2c: i2c@4a88000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* SPI Instance */ + qupv3_se0_spi: spi@4a80000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + reg = <0x4a80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + dmas = <&gpi_dma0 0 0 1 64 0>, + <&gpi_dma0 1 0 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + /* SPI Instance */ + qupv3_se1_spi: spi@4a84000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + reg = <0x4a84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + dmas = <&gpi_dma0 0 1 1 64 0>, + <&gpi_dma0 1 1 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + /* SPI Instance */ + qupv3_se5_spi: spi@4a94000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + reg = <0x4a94000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + dmas = <&gpi_dma0 0 5 1 64 0>, + <&gpi_dma0 1 5 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; +}; diff --git a/qcom/bengal-regulator.dtsi b/qcom/bengal-regulator.dtsi new file mode 100644 index 00000000..ba3ca199 --- /dev/null +++ b/qcom/bengal-regulator.dtsi @@ -0,0 +1,394 @@ +#include +#include + +&rpm_bus { + /* PM6125 S3/S4 - VDD_CX supply */ + rpm-regulator-smpa3 { + status = "okay"; + VDD_CX_LEVEL: + VDD_GFX_LEVEL: + VDD_MSS_LEVEL: + S3A_LEVEL: pm6125_s3_level: regulator-s3-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s3_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + VDD_CX_FLOOR_LEVEL: + VDD_MSS_FLOOR_LEVEL: + S3A_FLOOR_LEVEL: + pm6125_s3_floor_level: regulator-s3-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s3_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + VDD_CX_LEVEL_AO: + VDD_MSS_LEVEL_AO: + S3A_LEVEL_AO: pm6125_s3_level_ao: regulator-s3-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s3_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + cx_cdev: cx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&VDD_CX_FLOOR_LEVEL>; + regulator-levels = ; + #cooling-cells = <2>; + }; + }; + + /* PM6125 S5 - VDD_MX/WCSS_MX supply */ + rpm-regulator-smpa5 { + status = "okay"; + VDD_MX_LEVEL: + S5A_LEVEL: pm6125_s5_level: regulator-s5-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s5_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + VDD_MX_FLOOR_LEVEL: + S5A_FLOOR_LEVEL: + pm6125_s5_floor_level: regulator-s5-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s5_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + VDD_MX_LEVEL_AO: + S5A_LEVEL_AO: pm6125_s5_level_ao: regulator-s5-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s5_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + mx_cdev: mx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&VDD_MX_LEVEL>; + regulator-levels = ; + #cooling-cells = <2>; + }; + }; + + rpm-regulator-smpa6 { + status = "okay"; + S6A: pm6125_s6: regulator-s6 { + regulator-min-microvolt = <304000>; + regulator-max-microvolt = <1456000>; + qcom,init-voltage = <304000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa7 { + status = "okay"; + S7A: pm6125_s7: regulator-s7 { + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <2080000>; + qcom,init-voltage = <1280000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa8 { + status = "okay"; + S8A: pm6125_s8: regulator-s8 { + regulator-min-microvolt = <1064000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1064000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + L1A: pm6125_l1: regulator-l1 { + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <1152000>; + qcom,init-voltage = <952000>; + status = "okay"; + }; + }; + + /* VDD_LPI_MX supply */ + rpm-regulator-ldoa2 { + status = "okay"; + qcom,resource-name = "rwlm"; + qcom,resource-id = <0>; + L2A_LEVEL: pm6125_l2_level: regulator-l2-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l2_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + /* VDD_LPI_CX supply */ + rpm-regulator-ldoa3 { + status = "okay"; + qcom,resource-name = "rwlc"; + qcom,resource-id = <0>; + L3A_LEVEL: pm6125_l3_level: regulator-l3-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l3_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + }; + + rpm-regulator-ldoa4 { + status = "okay"; + L4A: pm6125_l4: regulator-l4 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <488000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + L5A: pm6125_l5: regulator-l5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3056000>; + qcom,init-voltage = <1648000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + L6A: pm6125_l6: regulator-l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + qcom,init-voltage = <576000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + L7A: pm6125_l7: regulator-l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + /* WCSS_CX */ + rpm-regulator-ldoa8 { + status = "okay"; + L8A: pm6125_l8: regulator-l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + qcom,init-voltage = <400000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + L9A: pm6125_l9: regulator-l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + L10A: pm6125_l10: regulator-l10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1704000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + L11A: pm6125_l11: regulator-l11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1952000>; + qcom,init-voltage = <1704000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + L12A: pm6125_l12: regulator-l12 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <1984000>; + qcom,init-voltage = <1624000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + L13A: pm6125_l13: regulator-l13 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1952000>; + qcom,init-voltage = <1504000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + L14A: pm6125_l14: regulator-l14 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1704000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + L15A: pm6125_l15: regulator-l15 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + qcom,init-voltage = <2920000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa16 { + status = "okay"; + L16A: pm6125_l16: regulator-l16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1704000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + L17A: pm6125_l17: regulator-l17 { + regulator-min-microvolt = <1152000>; + regulator-max-microvolt = <1384000>; + qcom,init-voltage = <1152000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa18 { + status = "okay"; + L18A: pm6125_l18: regulator-l18 { + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1312000>; + qcom,init-voltage = <1104000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + L19A: pm6125_l19: regulator-l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + qcom,init-voltage = <1624000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa20 { + status = "okay"; + L20A: pm6125_l20: regulator-l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + qcom,init-voltage = <1624000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa21 { + status = "okay"; + L21A: pm6125_l21: regulator-l21 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3600000>; + qcom,init-voltage = <2400000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa22 { + status = "okay"; + L22A: pm6125_l22: regulator-l22 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <3304000>; + qcom,init-voltage = <2952000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa23 { + status = "okay"; + L23A: pm6125_l23: regulator-l23 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + qcom,init-voltage = <3200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa24 { + status = "okay"; + L24A: pm6125_l24: regulator-l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3600000>; + qcom,init-voltage = <2704000>; + status = "okay"; + }; + }; +}; diff --git a/qcom/bengal-thermal-overlay.dtsi b/qcom/bengal-thermal-overlay.dtsi new file mode 100644 index 00000000..39a1c400 --- /dev/null +++ b/qcom/bengal-thermal-overlay.dtsi @@ -0,0 +1,56 @@ +#include + +&thermal_zones { + pm6125-tz { + cooling-maps { + trip0_cpu0 { + trip = <&pm6125_trip0>; + cooling-device = + <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + trip0_cpu4 { + trip = <&pm6125_trip0>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + trip1_cpu1 { + trip = <&pm6125_trip1>; + cooling-device = <&cpu1_isolate 1 1>; + }; + + trip1_cpu2 { + trip = <&pm6125_trip1>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + trip1_cpu3 { + trip = <&pm6125_trip1>; + cooling-device = <&cpu3_isolate 1 1>; + }; + + trip1_cpu4 { + trip = <&pm6125_trip1>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + trip1_cpu5 { + trip = <&pm6125_trip1>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + trip1_cpu6 { + trip = <&pm6125_trip1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + trip1_cpu7 { + trip = <&pm6125_trip1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; +}; diff --git a/qcom/bengal-thermal.dtsi b/qcom/bengal-thermal.dtsi new file mode 100644 index 00000000..8e20d52f --- /dev/null +++ b/qcom/bengal-thermal.dtsi @@ -0,0 +1,1223 @@ +#include +#include + +&cpufreq_hw { + #address-cells = <1>; + #size-cells = <1>; + lmh_dcvs0: qcom,limits-dcvs@f521000 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <0>; + reg = <0xf550800 0x1000>, + <0xf521000 0x1000>; + qcom,no-cooling-device-register; + #thermal-sensor-cells = <0>; + }; + + lmh_dcvs1: qcom,limits-dcvs@f523000 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <1>; + reg = <0xf550800 0x1000>, + <0xf523000 0x1000>; + qcom,no-cooling-device-register; + #thermal-sensor-cells = <0>; + }; + + qcom,cpu-isolation { + compatible = "qcom,cpu-isolate"; + cpu0_isolate: cpu0-isolate { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_isolate: cpu1-isolate { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_isolate: cpu2-isolate { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_isolate: cpu3-isolate { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + + cpu4_isolate: cpu4-isolate { + qcom,cpu = <&CPU4>; + #cooling-cells = <2>; + }; + + cpu5_isolate: cpu5-isolate { + qcom,cpu = <&CPU5>; + #cooling-cells = <2>; + }; + + cpu6_isolate: cpu6-isolate { + qcom,cpu = <&CPU6>; + #cooling-cells = <2>; + }; + + cpu7_isolate: cpu7-isolate { + qcom,cpu = <&CPU7>; + #cooling-cells = <2>; + }; + }; +}; + +&soc { + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem { + qcom,instance-id = ; + + modem_pa: modem_pa { + qcom,qmi-dev-name = "pa"; + #cooling-cells = <2>; + }; + + modem_proc: modem_proc { + qcom,qmi-dev-name = "modem"; + #cooling-cells = <2>; + }; + + modem_current: modem_current { + qcom,qmi-dev-name = "modem_current"; + #cooling-cells = <2>; + }; + + modem_skin: modem_skin { + qcom,qmi-dev-name = "modem_skin"; + #cooling-cells = <2>; + }; + + modem_vdd: modem_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + + modem_wlan: modem_wlan { + qcom,qmi-dev-name = "wlan"; + #cooling-cells = <2>; + }; + }; + + cdsp { + qcom,instance-id = ; + + cdsp_sw: cdsp { + qcom,qmi-dev-name = "cdsp_sw"; + #cooling-cells = <2>; + }; + + cdsp_hw: hvx { + qcom,qmi-dev-name = "cdsp_hw"; + #cooling-cells = <2>; + }; + }; + + adsp { + qcom,instance-id = ; + + adsp_vdd: adsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; + + lmh_cpu_vdd: qcom,lmh-cpu-vdd@f550800 { + compatible = "qcom,lmh-cpu-vdd"; + reg = <0xf550800 0x1000>; + #cooling-cells = <2>; + }; + + cxip_cdev: cxip-cdev@3ed000 { + compatible = "qcom,cxip-lm-cooling-device"; + reg = <0x3ed000 0xc00c>; + qcom,thermal-client-offset = <0x8000>; + /* 4th and 5th offsets to bypass VICTIM1 */ + qcom,bypass-client-list = <0x1004 0x4004 0x6004 0xc004 0xc008>; + #cooling-cells = <2>; + }; +}; + +&thermal_zones { + mapss-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cdsp-hvx-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + wlan-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 4>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 5>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 6>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 7>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 8>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 9>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 10>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 11>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 12>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 13>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + display-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 14>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpu-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 15>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + xo-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC5_XO_THERM_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM1_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM2_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm_iio ADC5_GPIO1_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + emmc-ufs-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm_iio ADC5_GPIO2_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + gpu-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 15>; + wake-capable-sensor; + trips { + gpu_step_trip: gpu-trip { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + gpu_cx_mon: gpu-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev { + trip = <&gpu_step_trip>; + }; + + gpu-cx-cdev0 { + trip = <&gpu_cx_mon>; + }; + + gpu-cx-cdev1 { + trip = <&gpu_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + + gpu-cx-cdev2 { + trip = <&gpu_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + + gpu-cx-cdev3 { + trip = <&gpu_cx_mon>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + hepta-cpu-max-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + wake-capable-sensor; + + trips { + silver-trip { + temperature = <120000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + cpuss-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 10>; + wake-capable-sensor; + + trips { + cpu4_5_config: cpu-4-5-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu4_cdev { + trip = <&cpu4_5_config>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + cpu5_cdev { + trip = <&cpu4_5_config>; + cooling-device = <&cpu5_isolate 1 1>; + }; + }; + }; + + cpuss-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 11>; + wake-capable-sensor; + + trips { + cpu6_7_config: cpu-6-7-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu6_cdev { + trip = <&cpu6_7_config>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + cpu7_cdev { + trip = <&cpu6_7_config>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + cpuss-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 12>; + wake-capable-sensor; + + trips { + silv_cpus_config: silv-cpus-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_cdev { + trip = <&silv_cpus_config>; + cooling-device = <&cpu0_isolate 1 1>; + }; + + cpu1_cdev { + trip = <&silv_cpus_config>; + cooling-device = <&cpu1_isolate 1 1>; + }; + + cpu2_cdev { + trip = <&silv_cpus_config>; + cooling-device = <&cpu2_isolate 1 1>; + }; + + cpu3_cdev { + trip = <&silv_cpus_config>; + cooling-device = <&cpu3_isolate 1 1>; + }; + }; + }; + + cpu-1-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 6>; + wake-capable-sensor; + + trips { + cpu4_config: cpu4-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu4_cdev { + trip = <&cpu4_config>; + cooling-device = <&cpu4_isolate 1 1>; + }; + }; + }; + + cpu-1-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 7>; + wake-capable-sensor; + + trips { + cpu5_config: cpu5-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu5_cdev { + trip = <&cpu5_config>; + cooling-device = <&cpu5_isolate 1 1>; + }; + }; + }; + + cpu-1-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 8>; + wake-capable-sensor; + + trips { + cpu6_config: cpu6-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu6_cdev { + trip = <&cpu6_config>; + cooling-device = <&cpu6_isolate 1 1>; + }; + }; + }; + + cpu-1-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 9>; + wake-capable-sensor; + + trips { + cpu7_config: cpu7-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu7_cdev { + trip = <&cpu7_config>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + cdsp-hvx-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + thermal-governor = "step_wise"; + wake-capable-sensor; + + trips { + cdsp_trip0: cdsp-trip0 { + temperature = <95000>; + hysteresis = <20000>; + type = "passive"; + }; + + cdsp_trip1: cdsp-trip1 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + cdsp_cx_mon: cdsp-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cxip-cdev { + trip = <&cdsp_trip0>; + cooling-device = <&cxip_cdev 1 1>; + }; + + cdsp-cdev0 { + trip = <&cdsp_trip1>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + + cdsp-cx-cdev0 { + trip = <&cdsp_cx_mon>; + }; + + cdsp-cx-cdev1 { + trip = <&cdsp_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + + cdsp-cx-cdev2 { + trip = <&cdsp_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + + cdsp-cx-cdev3 { + trip = <&cdsp_cx_mon>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + mdm-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 13>; + wake-capable-sensor; + trips { + mdm0_cx_mon: mdm0-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + mdm0-cx-cdev0 { + trip = <&mdm0_cx_mon>; + }; + + mdm0-cx-cdev1 { + trip = <&mdm0_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + + mdm0-cx-cdev2 { + trip = <&mdm0_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + + mdm0-cx-cdev3 { + trip = <&mdm0_cx_mon>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + mdm-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 5>; + wake-capable-sensor; + trips { + mdm1_cx_mon: mdm1-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + mdm1-cx-cdev0 { + trip = <&mdm1_cx_mon>; + }; + + mdm1-cx-cdev1 { + trip = <&mdm1_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + + mdm1-cx-cdev2 { + trip = <&mdm1_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + + mdm1-cx-cdev3 { + trip = <&mdm1_cx_mon>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + mapss-lowc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&tsens0 0>; + wake-capable-sensor; + tracks-low; + + trips { + mapss_cap_trip: mapss-cap-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + lmh_cpu_cdev { + trip = <&mapss_cap_trip>; + cooling-device = <&lmh_cpu_vdd 1 1>; + }; + }; + }; + + mapss-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 0>; + wake-capable-sensor; + tracks-low; + + trips { + mapss_trip: mapss-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cx_vdd_cdev { + trip = <&mapss_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + + mx_vdd_cdev { + trip = <&mapss_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + + modem_vdd_cdev { + trip = <&mapss_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + + adsp_vdd_cdev { + trip = <&mapss_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + }; + }; + + camera-lowc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&tsens0 3>; + wake-capable-sensor; + tracks-low; + + trips { + camera_cap_trip: camera-cap-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + lmh_cpu_cdev { + trip = <&camera_cap_trip>; + cooling-device = <&lmh_cpu_vdd 1 1>; + }; + }; + }; + + camera-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 3>; + wake-capable-sensor; + tracks-low; + + trips { + camera_trip: camera-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cx_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + + mx_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + + modem_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + + adsp_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + }; + }; + + quiet-therm-step { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM2_100K_PU>; + wake-capable-sensor; + status = "disabled"; + + trips { + skin_batt_trip0: batt-trip0 { + temperature = <39000>; + hysteresis = <2000>; + type = "passive"; + }; + + skin_modem_trip0: modem-trip0 { + temperature = <40000>; + hysteresis = <4000>; + type = "passive"; + }; + + skin_gold_trip: gold-trip { + temperature = <40000>; + hysteresis = <0>; + type = "passive"; + }; + + skin_batt_trip1: batt-trip1 { + temperature = <41000>; + hysteresis = <2000>; + type = "passive"; + }; + + skin_silver_trip: silver-trip { + temperature = <41000>; + hysteresis = <0>; + type = "passive"; + }; + + skin_modem_trip1: modem-trip1 { + temperature = <42000>; + hysteresis = <4000>; + type = "passive"; + }; + + skin_modem_trip2: modem-trip2 { + temperature = <43000>; + hysteresis = <4000>; + type = "passive"; + }; + + skin_batt_trip2: batt-trip2 { + temperature = <43000>; + hysteresis = <2000>; + type = "passive"; + }; + + skin_gpu_trip: gpu-trip { + temperature = <43000>; + hysteresis = <0>; + type = "passive"; + }; + + skin_batt_trip3: batt-trip3 { + temperature = <45000>; + hysteresis = <2000>; + type = "passive"; + }; + + skin_modem_trip3: modem-trip3 { + temperature = <50000>; + hysteresis = <5000>; + type = "passive"; + }; + + skin_hvx_trip: hvx-trip { + temperature = <52000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + gold_cdev { + trip = <&skin_gold_trip>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-4)>; + }; + + silver_cdev { + trip = <&skin_silver_trip>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-5)>; + }; + + gpu_cdev { + trip = <&skin_gpu_trip>; + }; + + hvx_cdev { + trip = <&skin_hvx_trip>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + mdm_cdev0 { + trip = <&skin_modem_trip0>; + cooling-device = <&modem_proc 1 1>; + }; + + mdm_cdev1 { + trip = <&skin_modem_trip1>; + cooling-device = <&modem_pa 1 1>; + }; + + mdm_cdev2 { + trip = <&skin_modem_trip2>; + cooling-device = <&modem_pa 2 2>; + }; + + mdm_cdev3 { + trip = <&skin_modem_trip3>; + cooling-device = <&modem_pa 3 3>; + }; + + mdm_cdev4 { + trip = <&skin_modem_trip3>; + cooling-device = <&modem_proc 3 3>; + }; + + batt_cdev1 { + trip = <&skin_batt_trip0>; + }; + + batt_cdev2 { + trip = <&skin_batt_trip1>; + }; + + batt_cdev3 { + trip = <&skin_batt_trip2>; + }; + + batt_cdev4 { + trip = <&skin_batt_trip3>; + }; + }; + }; +}; diff --git a/qcom/khaje-atp-overlay.dts b/qcom/khaje-atp-overlay.dts new file mode 100644 index 00000000..bc5789fc --- /dev/null +++ b/qcom/khaje-atp-overlay.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +#include +#include "khaje-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khaje ATP"; + compatible = "qcom,khaje-atp", "qcom,khaje", "qcom,atp"; + qcom,msm-id = <518 0x10000>; + qcom,board-id = <33 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khaje-atp.dts b/qcom/khaje-atp.dts new file mode 100644 index 00000000..fc94ce2e --- /dev/null +++ b/qcom/khaje-atp.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "khaje.dtsi" +#include "khaje-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khaje ATP"; + compatible = "qcom,khaje-atp", "qcom,khaje", "qcom,atp"; + qcom,board-id = <33 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khaje-atp.dtsi b/qcom/khaje-atp.dtsi new file mode 100644 index 00000000..dd13520f --- /dev/null +++ b/qcom/khaje-atp.dtsi @@ -0,0 +1,280 @@ +#include +#include +#include +#include "khaje-pm7250b.dtsi" + +&pm6125_gpios { + eldo9_pin { + usb_eldo9:gpio@c000 { + pins = "gpio1"; + function = "normal"; + qcom,drive-strength = <2>; + power-source = <0>; + bias-disable; + output-high; + }; + }; +}; + +&soc { + vdda_usb_ss_dp_core: vdda_usb_ss_dp_core { + compatible = "regulator-fixed"; + regulator-name = "vdd_supply"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + enable-active-high; + gpio = <&pm6125_gpios 1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_eldo9>; + }; +}; + +&sdhc_1 { + vdd-supply = <&L24A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L11A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on + &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off + &sdc1_rclk_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&L22A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L5A>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + vdd-io-bias-supply = <&L7A>; + qcom,vdd-io-bias-voltage-level = <1256000 1256000>; + qcom,vdd-io-bias-current-level = <0 6000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4"; + + vdda-phy-supply = <&L4A>; /* 0.9v */ + vdda-pll-supply = <&L18A>; /* 1.8v */ + vdda-phy-max-microamp = <85700>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&L24A>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&L11A>; + vccq2-voltage-level = <1800000 1800000>; + vcc-max-microamp = <800000>; + vccq2-max-microamp = <800000>; + vccq2-pwr-collapse-sup; + + qcom,vddp-ref-clk-supply = <&L18A>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1232000>; + qcom,vddp-ref-clk-max-uV = <1232000>; + + status = "ok"; +}; + +&usb_qmp_dp_phy { + vdd-supply = <&vdda_usb_ss_dp_core>; +}; + +&pm6125_vadc { + pinctrl-0 = <&camera_therm_default &emmc_therm_default &rf_pa1_therm_default>; + + rf_pa1_therm { + reg = ; + label = "rf_pa1_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6125_adc_tm { + io-channels = <&pm6125_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm6125_vadc ADC5_AMUX_THM2_100K_PU>, + <&pm6125_vadc ADC5_XO_THERM_100K_PU>, + <&pm6125_vadc ADC5_GPIO4_100K_PU>; + + rf_pa1_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + rf-pa1-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC5_GPIO4_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&pm6125_gpios { + + rf_pa1_therm { + rf_pa1_therm_default: rf_pa1_therm_default { + pins = "gpio7"; + bias-high-impedance; + }; + }; + + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio5"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + linux,can-disable; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; +}; + +&pm7250b_charger { + status = "ok"; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage"; + qcom,batteryless-platform; + qcom,sec-charger-config = <0>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,suspend-input-on-debug-batt; +}; + +&pm7250b_qg { + status = "ok"; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>; + io-channel-names = "batt-therm", + "batt-id"; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; +}; + +&pm8008_8 { + status = "disabled"; +}; + +&pm8008_9 { + status = "disabled"; +}; + +&pm6125_pwm { + status = "okay"; +}; + +&qupv3_se2_i2c { + status = "okay"; + + novatek@62 { + reg = <0x62>; + status = "ok"; + + interrupt-parent = <&tlmm>; + interrupts = <80 0x2008>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + + novatek,reset-gpio = <&tlmm 86 0x00>; + novatek,irq-gpio = <&tlmm 80 0x2008>; + + }; +}; + +&pm7250b_charger { + dpdm-supply = <&usb2_phy0>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L15A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; +}; diff --git a/qcom/khaje-dma-heaps.dtsi b/qcom/khaje-dma-heaps.dtsi new file mode 100644 index 00000000..7b071d2d --- /dev/null +++ b/qcom/khaje-dma-heaps.dtsi @@ -0,0 +1,38 @@ +#include + +&soc { + qcom,dma-heaps { + compatible = "qcom,dma-heaps"; + + qcom,qseecom { + qcom,dma-heap-name = "qcom,qseecom"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_mem>; + }; + + qcom,qseecom_ta { + qcom,dma-heap-name = "qcom,qseecom-ta"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_ta_mem>; + }; + + qcom,secure_cdsp { + qcom,dma-heap-name = "qcom,secure-cdsp"; + qcom,dma-heap-type = ; + memory-region = <&cdsp_sec_mem>; + qcom,token = <0x20000000>; + }; + + qcom,secure_display { + qcom,dma-heap-name = "qcom,secure-display"; + qcom,dma-heap-type = ; + memory-region = <&secure_display_memory>; + }; + + qcom,user_contig { + qcom,dma-heap-name = "qcom,user-contig"; + qcom,dma-heap-type = ; + memory-region = <&user_contig_mem>; + }; + }; +}; diff --git a/qcom/khaje-idp-nopmi-overlay.dts b/qcom/khaje-idp-nopmi-overlay.dts new file mode 100644 index 00000000..566b24f0 --- /dev/null +++ b/qcom/khaje-idp-nopmi-overlay.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +#include +#include "khaje-idp-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJE IDP nopmi"; + compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; + qcom,msm-id = <518 0x10000>; + qcom,board-id = <0x10022 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/khaje-idp-nopmi.dts b/qcom/khaje-idp-nopmi.dts new file mode 100644 index 00000000..31d8418b --- /dev/null +++ b/qcom/khaje-idp-nopmi.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "khaje.dtsi" +#include "khaje-idp-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJE IDP nopmi"; + compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; + qcom,board-id = <0x10022 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/khaje-idp-nopmi.dtsi b/qcom/khaje-idp-nopmi.dtsi new file mode 100644 index 00000000..c2f9a636 --- /dev/null +++ b/qcom/khaje-idp-nopmi.dtsi @@ -0,0 +1,18 @@ +#include "khaje-idp.dtsi" + +&qupv3_se2_i2c { + synaptics_tcm@20 { + status = "disabled"; + }; + + novatek@62 { + status = "disabled"; + }; +}; + +&usb0 { + /delete-property/ extcon; + dwc3@4e00000 { + dr_mode = "peripheral"; + }; +}; diff --git a/qcom/khaje-idp-overlay.dts b/qcom/khaje-idp-overlay.dts new file mode 100644 index 00000000..dea903c5 --- /dev/null +++ b/qcom/khaje-idp-overlay.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +#include +#include "khaje-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khaje IDP"; + compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; + qcom,msm-id = <518 0x10000>; + qcom,board-id = <0x10022 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khaje-idp-pm7250b.dtsi b/qcom/khaje-idp-pm7250b.dtsi new file mode 100644 index 00000000..3a6abb86 --- /dev/null +++ b/qcom/khaje-idp-pm7250b.dtsi @@ -0,0 +1,116 @@ +#include "khaje-pm7250b.dtsi" +#include "khaje-thermal-pm7250b-overlay.dtsi" +#include + +&soc { + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + }; +}; + +&pm7250b_gpios { + pm7250b_smb_int_default: pm7250b_smb_int_default { + pins = "gpio6"; + function = "gpio"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; +}; + +&qupv3_se1_i2c { + status = "ok"; + #include "smb1355.dtsi" +}; + +&smb1355 { + pinctrl-names = "default"; + pinctrl-0 = <&pm7250b_smb_int_default>; + status = "ok"; +}; + +&smb1355_charger { + qcom,parallel-mode = <1>; + qcom,hw-die-temp-mitigation; + status = "ok"; +}; + +&pm7250b_charger { + status = "ok"; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp"; + qcom,battery-data = <&mtp_batterydata>; + qcom,sec-charger-config = <2>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,en-skin-therm-mitigation; + qcom,hvdcp3-standalone-config; +}; + +&pm7250b_qg { + status = "ok"; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>; + io-channel-names = "batt-therm", + "batt-id"; + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3500>; + qcom,bass-enable; + qcom,vbatt-cutoff-mv = <3400>; + qcom,vbatt-low-mv = <3500>; + qcom,vbatt-low-cold-mv = <3800>; + qcom,vbatt-empty-mv = <3200>; + qcom,vbatt-empty-cold-mv = <3100>; +}; + +&pm7250b_charger { + dpdm-supply = <&usb2_phy0>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L15A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; +}; diff --git a/qcom/khaje-idp.dts b/qcom/khaje-idp.dts new file mode 100644 index 00000000..3787ab3d --- /dev/null +++ b/qcom/khaje-idp.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "khaje.dtsi" +#include "khaje-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJE IDP"; + compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; + qcom,board-id = <0x10022 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khaje-idp.dtsi b/qcom/khaje-idp.dtsi new file mode 100644 index 00000000..8d01e465 --- /dev/null +++ b/qcom/khaje-idp.dtsi @@ -0,0 +1,304 @@ +#include +#include +#include +#include "bengal-thermal-overlay.dtsi" + +&qupv3_se4_2uart { + status = "ok"; +}; + +&pm6125_vadc { + pinctrl-0 = <&camera_therm_default &emmc_therm_default &rf_pa1_therm_default>; + + rf_pa1_therm { + reg = ; + label = "rf_pa1_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6125_adc_tm { + io-channels = <&pm6125_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm6125_vadc ADC5_AMUX_THM2_100K_PU>, + <&pm6125_vadc ADC5_XO_THERM_100K_PU>, + <&pm6125_vadc ADC5_GPIO4_100K_PU>; + + rf_pa1_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + rf-pa1-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC5_GPIO4_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&pm6125_gpios { + + rf_pa1_therm { + rf_pa1_therm_default: rf_pa1_therm_default { + pins = "gpio7"; + bias-high-impedance; + }; + }; + + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio5"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + eldo9_pin { + usb_eldo9:gpio@c000 { + pins = "gpio1"; + function = "normal"; + qcom,drive-strength = <2>; + power-source = <0>; + bias-disable; + output-high; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + linux,can-disable; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; + + vdda_usb_ss_dp_core: vdda_usb_ss_dp_core { + compatible = "regulator-fixed"; + regulator-name = "vdd_supply"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + enable-active-high; + gpio = <&pm6125_gpios 1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_eldo9>; + }; +}; + +&usb_qmp_dp_phy { + vdd-supply = <&vdda_usb_ss_dp_core>; +}; + +&qupv3_se1_i2c { + awinic@64 { + compatible = "awinic,aw2016_led"; + reg = <0x64>; + + awinic,red { + awinic,name = "red"; + awinic,id = <0>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,green { + awinic,name = "green"; + awinic,id = <1>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,blue { + awinic,name = "blue"; + awinic,id = <2>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + }; +}; + +&qupv3_se1_i2c { + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 70 0x00>; + qcom,nq-ven = <&tlmm 69 0x00>; + qcom,nq-firm = <&tlmm 31 0x00>; + qcom,nq-clkreq = <&tlmm 71 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <70 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + +&sdhc_1 { + vdd-supply = <&L24A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L11A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on + &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off + &sdc1_rclk_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&L22A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L5A>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + vdd-io-bias-supply = <&L7A>; + qcom,vdd-io-bias-voltage-level = <1256000 1256000>; + qcom,vdd-io-bias-current-level = <0 6000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4"; + + vdda-phy-supply = <&L4A>; /* 0.9v */ + vdda-pll-supply = <&L18A>; /* 1.8v */ + vdda-phy-max-microamp = <85700>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&L24A>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&L11A>; + vccq2-voltage-level = <1800000 1800000>; + vcc-max-microamp = <800000>; + vccq2-max-microamp = <800000>; + vccq2-pwr-collapse-sup; + + qcom,vddp-ref-clk-supply = <&L18A>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1232000>; + qcom,vddp-ref-clk-max-uV = <1232000>; + + status = "ok"; +}; + +&pm6125_pwm { + status = "ok"; +}; + +&qupv3_se2_i2c { + status = "okay"; + qcom,i2c-touch-active="synaptics,tcm-i2c"; + + synaptics_tcm@20 { + compatible = "synaptics,tcm-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <80 0x2008>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + synaptics,irq-gpio = <&tlmm 80 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&tlmm 86 0x00>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,power-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x20>; + synaptics,extend_report; + synaptics,firmware-name = "synaptics_firmware_k.img"; + + }; + + novatek@62 { + reg = <0x62>; + status = "ok"; + + interrupt-parent = <&tlmm>; + interrupts = <80 0x2008>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + + novatek,reset-gpio = <&tlmm 86 0x00>; + novatek,irq-gpio = <&tlmm 80 0x2008>; + + }; + +}; diff --git a/qcom/khaje-idps-display-90hz-overlay.dts b/qcom/khaje-idps-display-90hz-overlay.dts new file mode 100644 index 00000000..02711ed2 --- /dev/null +++ b/qcom/khaje-idps-display-90hz-overlay.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include +#include "khaje-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" +#include "khaje-idps-display-90hz.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJE IDPS + 90Hz"; + compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; + qcom,msm-id = <518 0x10000>; + qcom,board-id = <0x10122 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khaje-idps-display-90hz.dts b/qcom/khaje-idps-display-90hz.dts new file mode 100644 index 00000000..a9fc4d48 --- /dev/null +++ b/qcom/khaje-idps-display-90hz.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "khaje.dtsi" +#include "khaje-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" +#include "khaje-idps-display-90hz.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJE IDPS + 90Hz"; + compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; + qcom,board-id = <0x10122 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khaje-idps-display-90hz.dtsi b/qcom/khaje-idps-display-90hz.dtsi new file mode 100644 index 00000000..dd619006 --- /dev/null +++ b/qcom/khaje-idps-display-90hz.dtsi @@ -0,0 +1,3 @@ +&soc { +}; + diff --git a/qcom/khaje-pinctrl.dtsi b/qcom/khaje-pinctrl.dtsi new file mode 100644 index 00000000..5c85f5f3 --- /dev/null +++ b/qcom/khaje-pinctrl.dtsi @@ -0,0 +1,140 @@ +#include "bengal-pinctrl.dtsi" + +&tlmm { + compatible = "qcom,khaje-pinctrl"; + + cam_flash_torch_active: cam_flash_torch_active { + /* TORCH */ + mux { + pins = "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio85"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_flash_torch_suspend: cam_flash_torch_suspend { + /* TORCH */ + mux { + pins = "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio85"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_flash_tx_active: cam_flash_tx_active { + /* TX */ + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_flash_tx_suspend: cam_flash_tx_suspend { + /* TX */ + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + nfc { + nfc_clk_req_active { + /* active state */ + mux { + /* GPIO 71: NFC CLOCK REQUEST */ + pins = "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio71"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend { + /* sleep state */ + mux { + /* GPIO 71: NFC CLOCK REQUEST */ + pins = "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio71"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + pmx_ts_reset_active { + ts_reset_active: ts_reset_active { + mux { + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio80", "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio80", "gpio86"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; +}; diff --git a/qcom/khaje-pm7250b.dtsi b/qcom/khaje-pm7250b.dtsi new file mode 100644 index 00000000..402e987e --- /dev/null +++ b/qcom/khaje-pm7250b.dtsi @@ -0,0 +1,93 @@ +#include +#include +#include "pm7250b.dtsi" + +&pm7250b_clkdiv { + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; +}; + +&pm7250b_vadc { + charger_skin_therm@4d { + reg = ; + label = "charger_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + conn_therm@4f { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm7250b_adc_tm { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>; + + /* Channel nodes */ + charger_skin_therm@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + conn_therm@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + charger-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&pm7250b_gpios { + disp_lcd_bias_en { + disp_lcd_bias_en_default: disp_lcd_bias_en_default { + pins = "gpio5"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + qcom,drive-strength = <2>; + }; + }; +}; + +&pm7250b_pon { + qcom,log-kpd-event; +}; diff --git a/qcom/khaje-qrd-hvdcp3p5-overlay.dts b/qcom/khaje-qrd-hvdcp3p5-overlay.dts new file mode 100644 index 00000000..a5fb87eb --- /dev/null +++ b/qcom/khaje-qrd-hvdcp3p5-overlay.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include +#include "khaje-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" +#include "khaje-qrd-hvdcp3p5.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khaje QRD HVDCP3P5"; + compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd"; + qcom,msm-id = <518 0x10000>; + qcom,board-id = <0x1010B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khaje-qrd-hvdcp3p5.dts b/qcom/khaje-qrd-hvdcp3p5.dts new file mode 100644 index 00000000..7b4d4935 --- /dev/null +++ b/qcom/khaje-qrd-hvdcp3p5.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "khaje.dtsi" +#include "khaje-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" +#include "khaje-qrd-hvdcp3p5.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJE QRD HVDCP3P5"; + compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd"; + qcom,board-id = <0x1010B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khaje-qrd-hvdcp3p5.dtsi b/qcom/khaje-qrd-hvdcp3p5.dtsi new file mode 100644 index 00000000..f87a199d --- /dev/null +++ b/qcom/khaje-qrd-hvdcp3p5.dtsi @@ -0,0 +1,20 @@ +#include + +&pm7250b_gpios { + pm7250b_smb_int_default: pm7250b_smb_int_default { + pins = "gpio6"; + function = "gpio"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; +}; + +&smb1394 { + qcom,enable-toggle-stat; + pinctrl-names = "default"; + pinctrl-0 = <&pm7250b_smb_int_default>; + interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&spmi_bus>; +}; diff --git a/qcom/khaje-qrd-nopmi-overlay.dts b/qcom/khaje-qrd-nopmi-overlay.dts new file mode 100644 index 00000000..eab93663 --- /dev/null +++ b/qcom/khaje-qrd-nopmi-overlay.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +#include +#include "khaje-qrd-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJE QRD nopmi overlay"; + compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd"; + qcom,msm-id = <518 0x10000>; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/khaje-qrd-nopmi.dts b/qcom/khaje-qrd-nopmi.dts new file mode 100644 index 00000000..f36f81e8 --- /dev/null +++ b/qcom/khaje-qrd-nopmi.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "khaje.dtsi" +#include "khaje-qrd-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJE QRD nopmi"; + compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/khaje-qrd-nopmi.dtsi b/qcom/khaje-qrd-nopmi.dtsi new file mode 100644 index 00000000..14f166cd --- /dev/null +++ b/qcom/khaje-qrd-nopmi.dtsi @@ -0,0 +1,22 @@ +#include "khaje-qrd.dtsi" + +&qupv3_se2_i2c { + synaptics_tcm@20 { + status = "disabled"; + }; + + novatek@62 { + status = "disabled"; + }; + + focaltech@38 { + status = "disabled"; + }; +}; + +&usb0 { + /delete-property/ extcon; + dwc3@4e00000 { + dr_mode = "peripheral"; + }; +}; diff --git a/qcom/khaje-qrd-nowcd9375-overlay.dts b/qcom/khaje-qrd-nowcd9375-overlay.dts new file mode 100644 index 00000000..17dcc66b --- /dev/null +++ b/qcom/khaje-qrd-nowcd9375-overlay.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include +#include "khaje-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" +#include "khaje-qrd-nowcd9375.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khaje QRD NOWCD9375"; + compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd"; + qcom,msm-id = <518 0x10000>; + qcom,board-id = <0x2010B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khaje-qrd-nowcd9375.dts b/qcom/khaje-qrd-nowcd9375.dts new file mode 100644 index 00000000..891a0705 --- /dev/null +++ b/qcom/khaje-qrd-nowcd9375.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "khaje.dtsi" +#include "khaje-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" +#include "khaje-qrd-nowcd9375.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJE QRD NOWCD9375"; + compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd"; + qcom,board-id = <0x2010B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khaje-qrd-nowcd9375.dtsi b/qcom/khaje-qrd-nowcd9375.dtsi new file mode 100644 index 00000000..ff96a6ad --- /dev/null +++ b/qcom/khaje-qrd-nowcd9375.dtsi @@ -0,0 +1 @@ +#include "khaje-qrd-hvdcp3p5.dtsi" diff --git a/qcom/khaje-qrd-overlay.dts b/qcom/khaje-qrd-overlay.dts new file mode 100644 index 00000000..4cdbe3dc --- /dev/null +++ b/qcom/khaje-qrd-overlay.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +#include +#include "khaje-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khaje QRD"; + compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd"; + qcom,msm-id = <518 0x10000>; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khaje-qrd-pm7250b.dtsi b/qcom/khaje-qrd-pm7250b.dtsi new file mode 100644 index 00000000..4d0114ab --- /dev/null +++ b/qcom/khaje-qrd-pm7250b.dtsi @@ -0,0 +1,162 @@ +#include "khaje-pm7250b.dtsi" +#include "khaje-thermal-pm7250b-overlay.dtsi" + +&soc { + qrd_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-atl466271_3300mAh.dtsi" + }; +}; + +&tlmm { + smb_int_default: smb_int_default { + mux { + pins = "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio105"; + bias-pull-up; + input-enable; + }; + }; +}; + +&qupv3_se1_i2c { + status = "ok"; + #include "smb1394.dtsi" +}; + +&smb1394 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_int_default>; + interrupt-parent = <&tlmm>; + interrupt-names = "smb1394"; + interrupts = <105 IRQ_TYPE_LEVEL_LOW>; + status = "ok"; +}; + +&smb1394_div2_cp_primary { + io-channels = <&pm7250b_vadc ADC5_AMUX_THM2>; + io-channel-names = "die_temp"; + qcom,parallel-input-mode = <1>; + qcom,parallel-output-mode = <2>; + status = "ok"; +}; + +&pm7250b_vadc { + smb1390_therm@e { + qcom,scale-fn-type = ; + }; +}; + +&pm7250b_charger { + status = "ok"; + io-channels = <&pm7250b_vadc ADC5_USB_IN_V_16>, + <&pm7250b_vadc ADC5_USB_IN_I>, + <&pm7250b_vadc ADC5_CHG_TEMP>, + <&pm7250b_vadc ADC5_DIE_TEMP>, + <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_SBUx>, + <&pm7250b_vadc ADC5_VPH_PWR>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage", + "skin_temp"; + qcom,battery-data = <&qrd_batterydata>; + qcom,sec-charger-config = <1>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,smb-internal-pull-kohm = <0>; + qcom,thermal-mitigation = <8000000 7500000 7000000 6500000 6000000 5500000 + 5000000 4500000 4000000 3500000 3000000 2500000 2000000 1500000 + 1000000 500000>; +}; + +&pm7250b_qg { + status = "ok"; + io-channels = <&pm7250b_vadc ADC5_BAT_THERM_100K_PU>, + <&pm7250b_vadc ADC5_BAT_ID_100K_PU>; + io-channel-names = "batt-therm", + "batt-id"; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3500>; + qcom,bass-enable; + qcom,vbatt-cutoff-mv = <3400>; + qcom,vbatt-low-mv = <3500>; + qcom,vbatt-low-cold-mv = <3800>; + qcom,vbatt-empty-mv = <3200>; + qcom,vbatt-empty-cold-mv = <3100>; + qcom,use-cp-iin-sns; +}; + +&pm7250b_charger { + dpdm-supply = <&usb2_phy0>; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; +}; + +&pm7250b_pdphy { + vdd-pdphy-supply = <&L15A>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; +}; + +&usb0 { + extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>; +}; + +&thermal_zones { + quiet-thermal-step { + cooling-maps { + quiet_batt_cdev1 { + trip = <&quiet_batt_trip0>; + cooling-device = <&pm7250b_charger 8 8>; + }; + + quiet_batt_cdev2 { + trip = <&quiet_batt_trip1>; + cooling-device = <&pm7250b_charger 12 12>; + }; + + quiet_batt_cdev3 { + trip = <&quiet_batt_trip2>; + cooling-device = <&pm7250b_charger 14 14>; + }; + + quiet_batt_cdev4 { + trip = <&quiet_batt_trip3>; + cooling-device = <&pm7250b_charger 16 16>; + }; + + quiet_batt_cdev5 { + trip = <&quiet_batt_trip4>; + cooling-device = <&pm7250b_charger 18 18>; + }; + }; + }; +}; diff --git a/qcom/khaje-qrd.dts b/qcom/khaje-qrd.dts new file mode 100644 index 00000000..df4c7c15 --- /dev/null +++ b/qcom/khaje-qrd.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "khaje.dtsi" +#include "khaje-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJE QRD"; + compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khaje-qrd.dtsi b/qcom/khaje-qrd.dtsi new file mode 100644 index 00000000..783b52d2 --- /dev/null +++ b/qcom/khaje-qrd.dtsi @@ -0,0 +1,435 @@ +#include +#include +#include +#include "bengal-thermal-overlay.dtsi" + +&pm6125_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio5"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + eldo9_pin { + usb_eldo9:gpio@c000 { + pins = "gpio1"; + function = "normal"; + qcom,drive-strength = <2>; + power-source = <0>; + bias-disable; + output-high; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + linux,can-disable; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; + + vdda_usb_ss_dp_core: vdda_usb_ss_dp_core { + compatible = "regulator-fixed"; + regulator-name = "vdd_supply"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + enable-active-high; + gpio = <&pm6125_gpios 1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_eldo9>; + }; +}; + +&usb_qmp_dp_phy { + vdd-supply = <&vdda_usb_ss_dp_core>; +}; + +&qupv3_se1_i2c { + awinic@64 { + compatible = "awinic,aw2016_led"; + reg = <0x64>; + + awinic,red { + awinic,name = "red"; + awinic,id = <0>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,green { + awinic,name = "green"; + awinic,id = <1>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,blue { + awinic,name = "blue"; + awinic,id = <2>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + }; +}; + +&qupv3_se1_i2c { + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 70 0x00>; + qcom,nq-ven = <&tlmm 69 0x00>; + qcom,nq-firm = <&tlmm 31 0x00>; + qcom,nq-clkreq = <&tlmm 71 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <70 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + +&sdhc_1 { + vdd-supply = <&L24A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L11A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on + &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off + &sdc1_rclk_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&L22A>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L5A>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + vdd-io-bias-supply = <&L7A>; + qcom,vdd-io-bias-voltage-level = <1256000 1256000>; + qcom,vdd-io-bias-current-level = <0 6000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4"; + + vdda-phy-supply = <&L4A>; /* 0.9v */ + vdda-pll-supply = <&L18A>; /* 1.8v */ + vdda-phy-max-microamp = <85700>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&L24A>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&L11A>; + vccq2-voltage-level = <1800000 1800000>; + vcc-max-microamp = <800000>; + vccq2-max-microamp = <800000>; + vccq2-pwr-collapse-sup; + + qcom,vddp-ref-clk-supply = <&L18A>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1232000>; + qcom,vddp-ref-clk-max-uV = <1232000>; + + status = "ok"; +}; + +&pm6125_pwm { + status = "ok"; +}; + +&qupv3_se2_i2c { + status = "okay"; + qcom,i2c-touch-active="synaptics,tcm-i2c"; + + synaptics_tcm@20 { + compatible = "synaptics,tcm-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <80 0x2008>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + synaptics,irq-gpio = <&tlmm 80 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&tlmm 86 0x00>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,power-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x20>; + synaptics,extend_report; + synaptics,firmware-name = "synaptics_firmware_k.img"; + }; +}; + +&thermal_zones { + quiet-thermal-step { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM2_100K_PU>; + wake-capable-sensor; + + trips { + quiet_batt_trip0: batt-trip0 { + temperature = <41000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_modem_trip0: modem-trip0 { + temperature = <42000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_batt_trip1: batt-trip1 { + temperature = <43000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_batt_trip2: batt-trip2 { + temperature = <45000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_gold_trip: gold-trip { + temperature = <47000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_batt_trip3: batt-trip3 { + temperature = <47000>; + hysteresis = <2000>; + type = "passive"; + }; + + quiet_batt_trip4: batt-trip4 { + temperature = <48000>; + hysteresis = <1000>; + type = "passive"; + }; + + quiet_gpu_trip: gpu-trip { + temperature = <48000>; + hysteresis = <4000>; + type = "passive"; + }; + + quiet_silver_trip: silver-trip { + temperature = <50000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_hvx_trip: hvx-trip { + temperature = <52000>; + hysteresis = <4000>; + type = "passive"; + }; + + quiet_modem_trip1: modem-trip1 { + temperature = <60000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + gold_cdev { + trip = <&quiet_gold_trip>; + /* limit to 1766400khz */ + cooling-device = <&CPU4 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-4)>; + }; + + silver_cdev { + trip = <&quiet_silver_trip>; + /* limit to 1516800khz */ + cooling-device = <&CPU0 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-4)>; + }; + + gpu_cdev { + trip = <&quiet_gpu_trip>; + }; + + hvx_cdev { + trip = <&quiet_hvx_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + mdm_cdev0 { + trip = <&quiet_modem_trip0>; + cooling-device = <&modem_proc 1 1>; + }; + + mdm_cdev1 { + trip = <&quiet_modem_trip1>; + cooling-device = <&modem_proc 3 3>; + }; + }; + }; + + pa-therm0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM1_100K_PU>; + wake-capable-sensor; + + trips { + pa_therm0_trip0: pa-therm0-trip0 { + temperature = <52000>; + hysteresis = <2000>; + type = "passive"; + }; + + pa_therm0_trip1: pa-therm0-trip1 { + temperature = <54000>; + hysteresis = <2000>; + type = "passive"; + }; + + pa_therm0_trip2: pa-therm0-trip2 { + temperature = <60000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + modem_cdev0 { + trip = <&pa_therm0_trip0>; + cooling-device = <&modem_pa 1 1>; + }; + + modem_cdev1 { + trip = <&pa_therm0_trip1>; + cooling-device = <&modem_pa 2 2>; + }; + + modem_cdev2 { + trip = <&pa_therm0_trip2>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; +}; + +&tlmm { + fpc_reset_int: fpc_reset_int { + fpc_reset_low: reset_low { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + fpc_reset_high: reset_high { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + fpc_int_low: int_low { + mux { + pins = "gpio97"; + function = "gpio"; + }; + + config { + pins = "gpio97"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; +}; diff --git a/qcom/khaje-regulator.dtsi b/qcom/khaje-regulator.dtsi new file mode 100644 index 00000000..51508ac7 --- /dev/null +++ b/qcom/khaje-regulator.dtsi @@ -0,0 +1,152 @@ +#include "bengal-regulator.dtsi" + +&S6A { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1419000>; + qcom,init-voltage = <1352000>; +}; + +&S7A { + regulator-min-microvolt = <1569000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <2040000>; +}; + +&S8A { + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1170000>; + qcom,init-voltage = <1128000>; +}; + +&L1A { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,init-voltage = <1000000>; +}; + +&L4A { + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <880000>; +}; + +&L5A { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3050000>; + qcom,init-voltage = <2960000>; +}; + +&L6A { + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + qcom,init-voltage = <624000>; +}; + +&L7A { + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1256000>; +}; + +&L8A { + qcom,init-voltage = <704000>; +}; + +&L9A { + regulator-min-microvolt = <1504000>; + qcom,init-voltage = <1800000>; +}; + +&L10A { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1800000>; +}; + +&L11A { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1800000>; +}; + +&L12A { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1800000>; +}; + +&L13A { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1800000>; +}; + +&L14A { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1700000>; +}; + +&L15A { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <3080000>; +}; + +&L16A { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1700000>; +}; + +&L17A { + regulator-min-microvolt = <1220000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1220000>; +}; + +&L18A { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1232000>; +}; + +&L19A { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; +}; + +&L20A { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; +}; + +&L21A { + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <1600000>; +}; + +&L22A { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <2960000>; +}; + +&L24A { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2960000>; +}; + +&soc { + refgen: refgen-regulator@1600000 { + compatible = "qcom,refgen-kona-regulator"; + reg = <0x1600000 0x84>; + regulator-name = "refgen"; + regulator-enable-ramp-delay = <5>; + proxy-supply = <&refgen>; + qcom,proxy-consumer-enable; + }; +}; diff --git a/qcom/khaje-thermal-pm7250b-overlay.dtsi b/qcom/khaje-thermal-pm7250b-overlay.dtsi new file mode 100644 index 00000000..c26053dc --- /dev/null +++ b/qcom/khaje-thermal-pm7250b-overlay.dtsi @@ -0,0 +1,112 @@ +#include + +&thermal_zones { + pm7250b-tz { + cooling-maps { + trip0_bat { + trip = <&pm7250b_trip0>; + cooling-device = + <&pm7250b_charger (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + + trip1_bat { + trip = <&pm7250b_trip1>; + cooling-device = + <&pm7250b_charger THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + soc { + cooling-maps { + soc_cpu4 { + trip = <&soc_trip>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + soc_cpu5 { + trip = <&soc_trip>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + soc_cpu6 { + trip = <&soc_trip>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + soc_cpu7 { + trip = <&soc_trip>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pm7250b-bcl-lvl0 { + cooling-maps { + lbat0_cpufreq4 { + trip = <&b_bcl_lvl0>; + cooling-device = + <&CPU4 (THERMAL_MAX_LIMIT-4) + (THERMAL_MAX_LIMIT-4)>; + }; + + lbat0_cpu6 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + lbat0_cpu7 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu7_isolate 1 1>; + }; + + lbat0_gpu { + trip = <&b_bcl_lvl0>; + }; + + lbat0_cdsp { + trip = <&b_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; + }; + }; + + pm7250b-bcl-lvl1 { + cooling-maps { + lbat1_cpu4 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + lbat1_cpu5 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + lbat1_gpu { + trip = <&b_bcl_lvl1>; + }; + + lbat1_cdsp { + trip = <&b_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; + }; + }; + + pm7250b-bcl-lvl2 { + cooling-maps { + lbat2_gpu { + trip = <&b_bcl_lvl2>; + }; + + lbat2_cdsp { + trip = <&b_bcl_lvl2>; + cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; +}; diff --git a/qcom/khaje-usb.dtsi b/qcom/khaje-usb.dtsi new file mode 100644 index 00000000..d1b77619 --- /dev/null +++ b/qcom/khaje-usb.dtsi @@ -0,0 +1,328 @@ +#include +#include +&soc { + /* Primary USB port related controller */ + usb0: ssusb@4e00000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x4e00000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x120 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x50000000 0x60000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = , + , + , + ; + interrupt-names = "pwr_event_irq", "ss_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq"; + + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "xo", "sleep_clk", "utmi_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + dpdm-supply = <&usb2_phy0>; + + qcom,core-clk-rate = <133333333>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + qcom,gsi-disable-io-coherency; + + dwc3@4e00000 { + compatible = "snps,dwc3"; + reg = <0x4e00000 0xe000>; + interrupt-parent = <&intc>; + interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>; + tx-fifo-resize; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3-u1u2-disable; + snps,usb3_lpm_capable; + usb-core-id = <0>; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + + qcom,usbbam@0x04f04000 { + compatible = "qcom,usb-bam-msm"; + reg = <0x04f04000 0x17000>; + interrupts = ; + + qcom,usb-bam-fifo-baseaddr = <0xc121000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x08064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@1613000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x1613000 0x110>, + <0x1612000 0x4>; + reg-names = "hsusb_phy_base", + "eud_enable_reg"; + + vdd-supply = <&L4A>; + vdda18-supply = <&L12A>; + vdda33-supply = <&L15A>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_AHB2PHY_USB_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = + <0xa6 0x6c>, /* override_x0 */ + <0x85 0x70>, /* override_x1 */ + <0x16 0x74>; /* override_x2 */ + }; + + /* Primary USB port related QMP USB PHY */ + usb_qmp_dp_phy: ssphy@1615000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x01615000 0x3000>; + reg-names = "qmp_phy_base"; + + core-supply = <&L18A>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,core-voltage-level = <0 1232000 1260000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_AHB2PHY_USB_CLK>; + + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "com_aux_clk","cfg_ahb_clk"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* */ + ; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x1cf 0x0>; + qcom,iommu-dma = "disabled"; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + }; +}; diff --git a/qcom/khaje.dts b/qcom/khaje.dts new file mode 100644 index 00000000..b522b78f --- /dev/null +++ b/qcom/khaje.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "khaje.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khaje SoC"; + compatible = "qcom,khaje"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi new file mode 100644 index 00000000..b5cc577e --- /dev/null +++ b/qcom/khaje.dtsi @@ -0,0 +1,3758 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. Khaje SoC"; + compatible = "qcom,khaje"; + qcom,msm-id = <518 0x10000>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x1 0x40000000 0x0 0x40000000>, + <0x1 0xc0000000 0x0 0x80000000>, + <0x2 0xc0000000 0x1 0x40000000>; + granule = <512>; + }; + + aliases { + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + serial0 = &qupv3_se4_2uart; + hsuart0 = &qupv3_se3_4uart; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 7>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 7>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + + L1_I_1: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_1: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 7>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + + L1_I_2: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_2: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 7>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + + L1_I_3: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_3: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1 7>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + }; + + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1 7>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + + L1_I_101: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_101: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x102>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1 7>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + + L1_I_102: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_102: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x103>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1 7>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + + L1_I_103: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_103: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + firmware: firmware { + qcom_scm { + compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; + }; + + android { + compatible = "android,firmware"; + vbmeta { + compatible="android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo,recovery"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp_region@45700000 { + no-map; + reg = <0x0 0x45700000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_region@45e00000 { + no-map; + reg = <0x0 0x45e00000 0x0 0x140000>; + }; + + sec_apps_mem: sec_apps_region@45fff000 { + no-map; + reg = <0x0 0x45fff000 0x0 0x1000>; + }; + + smem_mem: smem_region@46000000 { + no-map; + reg = <0x0 0x46000000 0x0 0x200000>; + }; + + removed_mem: removed_region@60000000 { + no-map; + reg = <0x0 0x60000000 0x0 0x3900000>; + }; + + pil_modem_mem: modem_region@4ab00000 { + no-map; + reg = <0x0 0x4ab00000 0x0 0x6900000>; + }; + + pil_video_mem: pil_video_region@51400000 { + no-map; + reg = <0x0 0x51400000 0x0 0x500000>; + }; + + wlan_msa_mem: wlan_msa_region@51900000 { + no-map; + reg = <0x0 0x51900000 0x0 0x100000>; + }; + + pil_cdsp_mem: cdsp_regions@51a00000 { + no-map; + reg = <0x0 0x51a00000 0x0 0x1e00000>; + }; + + pil_adsp_mem: pil_adsp_region@53800000 { + no-map; + reg = <0x0 0x53800000 0x0 0x1e00000>; + }; + + pil_ipa_fw_mem: ipa_fw_region@55600000 { + no-map; + reg = <0x0 0x55600000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi_region@55610000 { + no-map; + reg = <0x0 0x55610000 0x0 0x5000>; + }; + + pil_gpu_mem: gpu_region@55615000 { + no-map; + reg = <0x0 0x55615000 0x0 0x2000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + cdsp_sec_mem: cdsp_sec_regions@46200000 { + no-map; + reg = <0x0 0x46200000 0x0 0x1e00000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x5c00000>; + }; + + cont_splash_memory: cont_splash_region@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + label = "cont_splash_region"; + }; + + disp_rdump_memory: disp_rdump_region@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + label = "disp_rdump_region"; + }; + + dfps_data_memory: dfps_data_region@5cf00000 { + reg = <0x0 0x5cf00000 0x0 0x0100000>; + label = "dfps_data_region"; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + system_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + }; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; + }; + + soc: soc { }; +}; + +#include "bengal-coresight.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0xf200000 0x10000>, /* GICD */ + <0xf300000 0x100000>; /* GICR * 8 */ + interrupts = <1 9 4>; + }; + + jtag_mm0: jtagmm@9040000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9040000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + }; + + jtag_mm1: jtagmm@9140000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9140000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU1>; + }; + + jtag_mm2: jtagmm@9240000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9240000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU2>; + }; + + jtag_mm3: jtagmm@9340000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9340000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU3>; + }; + + jtag_mm4: jtagmm@9440000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9440000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU4>; + }; + + jtag_mm5: jtagmm@9540000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9540000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU5>; + }; + + jtag_mm6: jtagmm@9640000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9640000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU6>; + }; + + jtag_mm7: jtagmm@9740000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9740000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU7>; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <2>; + label = "modem"; + }; + + mem_client_3_size: qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + qcom,client-id = <1>; + qcom,allocate-on-request; + label = "modem"; + }; + }; + + slim_aud: slim@a5c0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0xa5c0000 0x2c000>, + <0xa584000 0x20000>, <0xa66e000 0x2000>; + reg-names = "slimbus_physical", + "slimbus_bam_physical", "slimbus_lpass_mem"; + interrupts = , + ; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x0>; + qcom,ea-pc = <0x3b0>; + status = "ok"; + + /* Slimbus Slave DT for WCN3990 */ + btfmslim_codec: wcn3990 { + elemental-addr = [00 01 20 02 17 02]; + qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; + qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; + }; + }; + + wakegic: wake-gic { + interrupts-extended = <&wakegic GIC_SPI 197 + IRQ_TYPE_EDGE_RISING>; + reg = <0x45f01b8 0x1000>, + <0xf011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + qcom,num-mpm-irqs = <96>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + }; + + wakegpio: wake-gpio { + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-sw-ctrl-gpio = <&tlmm 87 0>; /* SW_CTRL */ + qca,bt-vdd-io-supply = <&L9A>; /* IO */ + qca,bt-vdd-core-supply = <&L17A>; /* RFA */ + qca,bt-vdd-pa-supply = <&L23A>; /* CH0 */ + qca,bt-vdd-xtal-supply = <&L16A>; /* XO */ + + qca,bt-vdd-io-voltage-level = <1700000 1900000>; + qca,bt-vdd-core-voltage-level = <1304000 1304000>; + qca,bt-vdd-pa-voltage-level = <3000000 3312000>; + qca,bt-vdd-xtal-voltage-level = <1700000 1900000>; + + qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 1 0xf08>, + <1 2 0xf08>, + <1 3 0xf08>, + <1 0 0xf08>; + clock-frequency = <19200000>; + }; + + dcc: dcc_v2@1be2000 { + compatible = "qcom,dcc-v2"; + reg = <0x1be2000 0x1000>, + <0x1bee000 0x2000>; + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0x2000>; + + link_list1 { + qcom,curr-link-list = <3>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + link_list2 { + qcom,curr-link-list = <2>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + + }; + + timer@f120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf120000 0x1000>; + clock-frequency = <19200000>; + + frame@f121000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xf121000 0x1000>, + <0xf122000 0x1000>; + }; + + frame@f123000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xf123000 0x1000>; + status = "disabled"; + }; + + frame@f124000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xf124000 0x1000>; + status = "disabled"; + }; + + frame@f125000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xf125000 0x1000>; + status = "disabled"; + }; + + frame@f126000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xf126000 0x1000>; + status = "disabled"; + }; + + frame@f127000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xf127000 0x1000>; + status = "disabled"; + }; + + frame@f128000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xf128000 0x1000>; + status = "disabled"; + }; + }; + + arm64_cpu_erp { + compatible = "arm,arm64-cpu-erp"; + interrupt-names = "pri-dbe-irq", + "sec-dbe-irq", + "pri-ext-irq", + "sec-ext-irq"; + interrupts = <0 43 4>, + <0 44 4>, + <0 41 4>, + <0 42 4>; + poll-delay-ms = <5000>; + }; + + qcom,msm-imem@c125000 { + compatible = "qcom,msm-imem"; + reg = <0xc125000 0x1000>; + ranges = <0x0 0xc125000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + restart@440b000 { + compatible = "qcom,pshold"; + reg = <0x440b000 0x4>, + <0x03d3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + qcom_seecom: qseecom@61800000 { + compatible = "qcom,qseecom"; + reg = <0x61800000 0x2100000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,fde-key-size; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,ce-opp-freq = <192000000>; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_smcinvoke: smcinvoke@61800000 { + compatible = "qcom,smcinvoke"; + reg = <0x61800000 0x2100000>; + reg-names = "secapp-region"; + }; + + qcom_rng: qrng@1b53000 { + compatible = "qcom,msm-rng"; + reg = <0x1b53000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "iface_clk"; + }; + + qcom_tzlog: tz-log@c125720 { + compatible = "qcom,tz-log"; + reg = <0xc125720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + + qcom_cedev: qcedev@1b20000 { + compatible = "qcom,qcedev"; + reg = <0x1b20000 0x20000>, + <0x1b04000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <3>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,ce-opp-freq = <192000000>; + qcom,smmu-s1-enable; + iommus = <&apps_smmu 0x0086 0x0011>, + <&apps_smmu 0x0096 0x0011>; + qcom,iommu-dma = "atomic"; + + qcom_cedev_ns_cb { + compatible = "qcom,qcedev,context-bank"; + label = "ns_context"; + iommus = <&apps_smmu 0x92 0>, + <&apps_smmu 0x98 0x1>, + <&apps_smmu 0x9F 0>; + qcom,iommu-dma-addr-pool = <0x70000000 0X10000000>; + }; + + qcom_cedev_s_cb { + compatible = "qcom,qcedev,context-bank"; + label = "secure_context"; + iommus = <&apps_smmu 0x93 0>, + <&apps_smmu 0x9C 0x1>, + <&apps_smmu 0x9E 0>; + qcom,iommu-dma-addr-pool = <0x70000000 0X10000000>; + qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */ + qcom,secure-context-bank; + }; + }; + + qcom_crypto: qcrypto@1b20000 { + compatible = "qcom,qcrypto"; + reg = <0x1b20000 0x20000>, + <0x1b04000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-aead-algo; + qcom,use-sw-hmac-algo; + qcom,smmu-s1-enable; + iommus = <&apps_smmu 0x0084 0x0011>, + <&apps_smmu 0x0094 0x0011>; + qcom,iommu-dma = "atomic"; + }; + + qcom,mpm2-sleep-counter@4403000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x4403000 0x1000>; + clock-frequency = <32768>; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = <1 6 4>; + }; + + eud: qcom,msm-eud@1610000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupts = ; + reg = <0x1610000 0x2000>, + <0x1612000 0x1000>, + <0x3E5018 0x4>; + reg-names = "eud_base", "eud_mode_mgr2", + "eud_tcsr_check_reg"; + qcom,secure-eud-en; + qcom,eud-tcsr-check-enable; + qcom,eud-clock-vote-req; + clocks = <&gcc GCC_AHB2PHY_USB_CLK>; + clock-names = "eud_ahb2phy_clk"; + status = "ok"; + }; + + qcom,msm-gladiator-v2@f100000 { + compatible = "qcom,msm-gladiator-v2"; + reg = <0xf100000 0xdc00>; + reg-names = "gladiator_base"; + interrupts = ; + clock-names = "atb_clk"; + clocks = <&rpmcc RPM_QDSS_CLK>; + }; + + wdog: qcom,wdt@f017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf017000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + interrupts = ; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + qcom,chd_silver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x0f1880b0 0x0f1980b0 + 0x0f1a80b0 0x0f1b80b0>; + qcom,config-arr = <0x0f1880b8 0x0f1980b8 + 0x0f1a80b8 0x0f1b80b8>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x0f0880b0 0x0f0980b0 + 0x0f0a80b0 0x0f0b80b0>; + qcom,config-arr = <0x0f0880b8 0x0f0980b8 + 0x0f0a80b8 0x0f0b80b8>; + }; + + qcom,ghd { + compatible = "qcom,gladiator-hang-detect"; + qcom,threshold-arr = <0x0f1d141c 0x0f1d1420 + 0x0f1d1424 0x0f1d1428 + 0x0f1d142c 0x0f1d1430>; + qcom,config-reg = <0x0f1d1434>; + }; + + lpass_pas:remoteproc-lpass@ab00000 { + reg = <0xab00000 0x00100>; + + cx-supply = <&L3A_LEVEL>; + reg-names = "cx", "mx"; + qcom,vdd_lpi_cx-uV-uA = ; + mx-supply = <&L2A_LEVEL>; + mx-uV-uA = ; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + memory-region = <&pil_adsp_mem>; + + /* Inputs from lpass */ + interrupts-extended = <&intc 0 282 1>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink_edge: glink-edge { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apcs_glb 8>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + }; + }; + + turing_pas: remoteproc-turing@b300000 { + reg = <0xb300000 0x100000>; + + cx-supply = <&VDD_CX_LEVEL>; + reg-names = "vdd_cx"; + cx-uV-uA = ; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + memory-region = <&pil_cdsp_mem>; + + /* Inputs from turing */ + interrupts-extended = <&intc 0 265 1>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&apcs_glb 28>; + mbox-names = "cdsp_smem"; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <100>; + qcom,qos-maxhold-ms = <20>; + }; + }; + }; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c1_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c2_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c3_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c101_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c102_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c103_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + c_scandump { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0xeb>; + }; + + l1_icache0 { + qcom,dump-size = <0x8900>; + qcom,dump-id = <0x60>; + }; + + l1_icache1 { + qcom,dump-size = <0x8900>; + qcom,dump-id = <0x61>; + }; + + l1_icache2 { + qcom,dump-size = <0x8900>; + qcom,dump-id = <0x62>; + }; + + l1_icache3 { + qcom,dump-size = <0x8900>; + qcom,dump-id = <0x63>; + }; + + l1_icache100 { + qcom,dump-size = <0x11100>; + qcom,dump-id = <0x64>; + }; + + l1_icache101 { + qcom,dump-size = <0x11100>; + qcom,dump-id = <0x65>; + }; + + l1_icache102 { + qcom,dump-size = <0x11100>; + qcom,dump-id = <0x66>; + }; + + l1_icache103 { + qcom,dump-size = <0x11100>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x80>; + }; + + l1_dcache1 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x81>; + }; + + l1_dcache2 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x82>; + }; + + l1_dcache3 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x83>; + }; + + l1_dcache100 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x84>; + }; + + l1_dcache101 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x85>; + }; + + l1_dcache102 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x86>; + }; + + l1_dcache103 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x87>; + }; + + l2_tlb0 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x120>; + }; + + l2_tlb1 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x121>; + }; + + l2_tlb2 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x122>; + }; + + l2_tlb3 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x123>; + }; + + l2_tlb100 { + qcom,dump-size = <0x4900>; + qcom,dump-id = <0x124>; + }; + + l2_tlb101 { + qcom,dump-size = <0x4900>; + qcom,dump-id = <0x125>; + }; + + l2_tlb102 { + qcom,dump-size = <0x4900>; + qcom,dump-id = <0x126>; + }; + + l2_tlb103 { + qcom,dump-size = <0x4900>; + qcom,dump-id = <0x127>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + tmc_etf { + qcom,dump-size = <0x8000>; + qcom,dump-id = <0xf0>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + }; + + sdhc_1: sdhci@4744000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x4744000 0x1000>, <0x4745000 0x1000>, + <0x4748000 0x8000>; + reg-names = "hc_mem", "cqhci_mem", "cqhci_ice"; + + interrupts-extended = <&intc GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 19 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "hc_irq", "pwr_irq", "tb_trig_irq"; + + qcom,bus-width = <8>; + qcom,large-address-bus; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 192000000 384000000>; + qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; + + qcom,devfreq,freq-table = <50000000 200000000>; + + qcom,scaling-lower-bus-speed-mode = "DDR52"; + + /* PM QoS */ + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <26 26>; + qcom,pm-qos-cpu-groups = <0x0f 0xf0>; + qcom,pm-qos-cmdq-latency-us = <26 26>, <26 26>; + qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface_clk", "core_clk", "ice_core_clk"; + + qcom,ice-clk-rates = <300000000 100000000>; + + /* Add support for gcc hw reset */ + resets = <&gcc GCC_SDCC1_BCR>; + reset-names = "core_reset"; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x2C010800 0x80040868>; + qcom,nonremovable; + status = "disabled"; + }; + + sdhc_2: sdhci@4784000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x4784000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + qcom,large-address-bus; + + qcom,clk-rates = <400000 20000000 25000000 + 50000000 100000000 202000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", + "SDR104"; + + qcom,devfreq,freq-table = <50000000 202000000>; + + + /* PM QoS */ + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <26 26>; + qcom,pm-qos-cpu-groups = <0x0f 0xf0>; + qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>; + + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; + qcom,vbias-skip-wa; + + status = "disabled"; + }; + + ufsphy_mem: ufsphy_mem@4807000 { + reg = <0x4807000 0xe00>; /* PHY regs */ + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + status = "disabled"; + }; + + ufshc_mem: ufshc@4804000 { + compatible = "qcom,ufshc"; + reg = <0x4804000 0x3000>, <0x4810000 0x8000>; + reg-names = "ufs_mem", "ufs_ice"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + spm-level = <5>; + #reset-cells = <1>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <22>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <123 512 0 0>, <1 757 0 0>, /* No vote */ + <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */ + <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */ + <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */ + <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */ + <123 512 1844 0>, <1 757 1000 0>, /* PWM G1 L2 */ + <123 512 3688 0>, <1 757 1000 0>, /* PWM G2 L2 */ + <123 512 7376 0>, <1 757 1000 0>, /* PWM G3 L2 */ + <123 512 14752 0>, <1 757 1000 0>, /* PWM G4 L2 */ + <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */ + <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */ + <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */ + <123 512 255591 0>, <1 757 1000 0>, /* HS G1 RA L2 */ + <123 512 511181 0>, <1 757 1000 0>, /* HS G2 RA L2 */ + <123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */ + <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */ + <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */ + <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */ + <123 512 298189 0>, <1 757 1000 0>, /* HS G1 RB L2 */ + <123 512 596378 0>, <1 757 1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */ + <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", + "MAX"; + + /* PM QoS */ + qcom,pm-qos-cpu-groups = <0x0f 0xf0>; + qcom,pm-qos-cpu-group-latency-us = <26 26>; + qcom,pm-qos-default-cpu = <0>; + + pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; + pinctrl-0 = <&ufs_dev_reset_assert>; + pinctrl-1 = <&ufs_dev_reset_deassert>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "core_reset"; + non-removable; + + status = "disabled"; + + }; + + thermal_zones: thermal-zones {}; + + tsens0:tsens@c222000 { + compatible = "qcom,tsens24xx"; + reg = <0x04410000 0x8>, + <0x04411000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = , + ; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + tsens-reinit-wa; + #thermal-sensor-cells = <1>; + }; + + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + + ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_rx_symbol_0_clk"; + #clock-cells = <0>; + }; + + ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_rx_symbol_1_clk"; + #clock-cells = <0>; + }; + + ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_tx_symbol_0_clk"; + #clock-cells = <0>; + }; + + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <0>; + }; + }; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-khaje"; + #clock-cells = <1>; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x200000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,guard-memory; + qcom,vm-nav-path; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,khaje-gcc", "syscon"; + reg = <0x1400000 0x1f0000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@5f00000 { + compatible = "qcom,khaje-dispcc", "syscon"; + reg = <0x05f00000 0x20000>; + reg-names = "cc_base"; + clock-names = "cfg_ahb_clk"; + clocks = <&gcc GCC_DISP_AHB_CLK>; + vdd_cx-supply = <&VDD_CX_LEVEL>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@5990000 { + compatible = "qcom,khaje-gpucc", "syscon"; + reg = <0x5990000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mccc_debug: syscon@447d200 { + compatible = "syscon"; + reg = <0x447d200 0x100>; + }; + + cpucc_debug: syscon@f11101c { + compatible = "syscon"; + reg = <0xf11101c 0x4>; + }; + + debugcc: clock-controller@0 { + compatible = "qcom,khaje-debugcc"; + qcom,gcc = <&gcc>; + qcom,dispcc = <&dispcc>; + qcom,gpucc = <&gpucc>; + qcom,mccc = <&mccc_debug>; + qcom,cpucc = <&cpucc_debug>; + clock-names = "xo_clk_src"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + #clock-cells = <1>; + }; + + cpufreq_hw: qcom,cpufreq-hw { + compatible = "qcom,cpufreq-hw"; + reg = <0xf521000 0x1000>, <0xf523000 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + qcom,no-accumulative-counter; + qcom,max-lut-entries = <12>; + #freq-domain-cells = <2>; + }; + + qcom,cpufreq-hw-debug@0f521000 { + compatible = "qcom,cpufreq-hw-debug"; + reg = <0x0f521000 0x800>; + reg-names = "domain-top"; + qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>; + }; + + tcsr_mutex_block: syscon@00340000 { + compatible = "syscon"; + reg = <0x340000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + rpm_msg_ram: memory@045f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x45f0000 0x7000>; + }; + + apcs_glb: mailbox@0f111000 { + compatible = "qcom,bengal-apcs-hmss-global"; + reg = <0xF111000 0x1000>; + + #mbox-cells = <1>; + }; + + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + restrict-access; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,rpc-latency-us = <611>; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C01 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C02 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C03 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C04 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C05 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C06 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x0C09 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C3 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C4 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C5 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb13 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C6 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb14 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C7 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,glink { + compatible = "qcom,glink"; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + + + tcsr: syscon@0x003C0000 { + compatible = "syscon"; + reg = <0x003C0000 0x40000>; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + mboxes = <&apcs_glb 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + mboxes = <&apcs_glb 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + mboxes = <&apcs_glb 30>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + qfprom: qfprom@1b40000 { + compatible = "qcom,qfprom"; + reg = <0x1b40000 0x7000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + + stm_debug_fuse: stm@20f0 { + reg = <0x20f0 0x4>; + }; + + feat_conf5: feat_conf5@6018 { + reg = <0x6018 0x4>; + }; + + feat_conf10: feat_conf10@602c { + reg = <0x602c 0x4>; + }; + + adsp_variant: adsp_variant@6011 { + reg = <0x6011 0x1>; + bits = <3 1>; + }; + + gpu_speed_bin: gpu_speed_bin@6006 { + reg = <0x6006 0x2>; + bits = <5 8>; + }; + + gpu_gaming_bin: gpu_gaming_bin@602d { + reg = <0x602d 0x1>; + bits = <5 1>; + }; + + feat_conf11: feat_conf11@6030 { + reg = <0x6030 0x1>; + bits = <0 8>; + }; + }; + + spmi_bus: qcom,spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x1c40000 0x1100>, + <0x1e00000 0x2000000>, + <0x3e00000 0x100000>, + <0x3f00000 0xa0000>, + <0x1c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + cx_ipeak_lm: cx_ipeak@3ed000 { + compatible = "qcom,cx-ipeak-v2"; + reg = <0x3ed000 0xe008>; + }; + + modem_pas: remoteproc-mss@6080000 { + reg = <0x6080000 0x100>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + reg-names = "vdd_cx"; + + memory-region = <&pil_modem_mem>; + + /* Inputs from mss */ + interrupts-extended = <&intc 0 307 1>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + glink-edge { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&apcs_glb 12>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 2>; + }; + }; + }; + + qcom_pmu: qcom,pmu { + compatible = "qcom,pmu"; + qcom,pmu-events-tbl = + < 0x0008 0xFF 0xFF 0xFF >, + < 0x0011 0xFF 0xFF 0xFF >, + < 0x0017 0xFF 0xFF 0xFF >; + }; + + ddr_freq_table: ddr-freq-table { + qcom,freq-tbl = + < 200000 >, + < 547000 >, + < 768000 >, + < 1017000 >, + < 1555000 >, + < 1804000 >, + < 2092000 >; + }; + + qcom_dcvs: qcom,dcvs { + compatible = "qcom,dcvs"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qcom_ddr_dcvs_hw: ddr { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <0>; + qcom,bus-width = <4>; + qcom,freq-tbl = <&ddr_freq_table>; + + ddr_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + }; + }; + }; + + bwmon_ddr: qcom,bwmon-ddr@01b8e200 { + compatible = "qcom,bwmon4"; + reg = <0x01b8e300 0x100>, <0x01b8e200 0x100>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&qcom_ddr_dcvs_hw>; + qcom,count-unit = <0x10000>; + }; + + qcom_memlat: qcom,memlat { + compatible = "qcom,memlat"; + ddr { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_ddr_dcvs_hw>; + qcom,sampling-path = <&ddr_dcvs_sp>; + qcom,miss-ev = <0x17>; + + silver { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,sampling-enabled; + qcom,cpufreq-memfreq-tbl = + < 1190400 547000 >, + < 1516800 768000 >, + < 1804800 1017000>; + }; + + gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,sampling-enabled; + qcom,cpufreq-memfreq-tbl = + < 1056000 547000 >, + < 1344000 1017000 >, + < 1766400 1555000 >, + < 2208000 1804000 >, + < 2803200 2092000 >; + }; + + silver-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,sampling-enabled; + qcom,compute-mon; + qcom,cpufreq-memfreq-tbl = + < 1190400 547000 >, + < 1516800 768000 >, + < 1804800 1017000> ; + }; + + gold-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,sampling-enabled; + qcom,compute-mon; + qcom,cpufreq-memfreq-tbl = + < 1056000 547000 >, + < 1344000 768000 >, + < 1766400 1017000 >, + < 2208000 1804000 >, + < 2803200 2092000 >; + }; + + }; + }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + qcom,ipa-platform-type-msm; + qcom,ipa-advertise-sg-support; + qcom,ipa-napi-enable; + }; + + ipa_hw: qcom,ipa@0x5800000 { + compatible = "qcom,ipa"; + reg = <0x5800000 0x34000>, + <0x5804000 0x28000>; + qcom,pas-id = <0xf>; + qcom,firmware-name = "ipa_fws"; + memory-region = <&pil_ipa_gsi_mem>; + reg-names = "ipa-base", "gsi-base"; + interrupts = , + ; + interrupt-names = "ipa-irq", "gsi-irq"; + qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */ + qcom,ipa-hw-mode = <0>; + qcom,platform-type = <1>; /* MSM platform */ + qcom,ee = <0>; + qcom,use-ipa-tethering-bridge; + qcom,modem-cfg-emb-pipe-flt; + qcom,ipa-wdi2; + qcom,ipa-wdi2_over_gsi; + qcom,ipa-endp-delay-wa; + qcom,ipa-fltrt-not-hashable; + qcom,use-64-bit-dma-mask; + qcom,arm-smmu; + qcom,smmu-fast-map; + qcom,use-ipa-pm; + qcom,skip-ieob-mask-wa; + clocks = <&rpmcc RPM_SMD_IPA_CLK>; + clock-names = "core_clk"; + + qcom,bus-vector-names = + "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; + qcom,throughput-threshold = <310 600 1000>; + qcom,scaling-exceptions = <>; + + /* smp2p information */ + qcom,smp2p_map_ipa_1_out { + compatible = "qcom,smp2p-map-ipa-1-out"; + qcom,smem-states = <&smp2p_ipa_1_out 0>; + qcom,smem-state-names = "ipa-smp2p-out"; + }; + + qcom,smp2p_map_ipa_1_in { + compatible = "qcom,smp2p-map-ipa-1-in"; + interrupts-extended = <&smp2p_ipa_1_in 0 0>; + interrupt-names = "ipa-smp2p-in"; + }; + }; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + iommus = <&apps_smmu 0x0140 0x0>; + qcom,iommu-dma-addr-pool = <0x10000000 0x30000000>; + /* modem tables in IMEM */ + qcom,iommu-dma = "fastmap"; + qcom,additional-mapping = <0x0c123000 0x0c123000 0x2000>; + qcom,iommu-geometry = <0 0xB0000000>; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + iommus = <&apps_smmu 0x0141 0x0>; + /* ipa-uc ram */ + qcom,iommu-dma = "atomic"; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + iommus = <&apps_smmu 0x0142 0x0>; + qcom,iommu-dma-addr-pool = <0x40400000 0x1fc00000>; + }; + + qcom,demux { + compatible = "qcom,demux"; + }; + +tpdm_turing_llm: tpdm@8861000 { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpdm-turing_llm"; + qcom,dummy-source; + + port { + tpdm_turing_llm_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_tpdm_turing_llm>; + }; + }; + }; + + /delete-node/ tpdm@8a58000; + tpdm_west: tpdm@8a58000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8a58000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-west"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_west_out_tpda11: endpoint { + remote-endpoint = + <&tpda11_in_tpdm_west>; + }; + }; + }; + + tpdm_spdm: tpdm@800f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x0800f000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-spdm"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_spdm_out_tpda13: endpoint { + remote-endpoint = + <&tpda13_in_tpdm_spdm>; + }; + }; + }; + + /delete-node/ funnel@8861000; + funnel_turing: funnel@8863000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x8863000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-turing"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_turing_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_funnel_turing>; + source = <&turing_etm0>; + }; + }; + + port@1 { + reg = <1>; + funnel_turing_out_tpda5: endpoint { + remote-endpoint = + <&tpda5_in_funnel_turing>; + }; + }; + + port@2 { + reg = <0>; + funnel_turing_in_tpdm_turing: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_turing_out_funnel_turing>; + }; + }; + + port@3 { + reg = <1>; + funnel_turing_in_tpdm_turing_llm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_turing_llm_out_funnel_turing>; + }; + }; + + port@4 { + reg = <2>; + funnel_turing_in_turing_etm0: endpoint { + slave-mode; + remote-endpoint = + <&turing_etm0_out_funnel_turing>; + }; + }; + }; + }; + + /delete-node/ tpda@8004000; + tpda: tpda@8004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x8004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <65>; + qcom,dsb-elem-size = <0 32>, + <1 32>, + <5 32>, + <11 32>, + <12 32>, + <15 32>; + qcom,cmb-elem-size = <7 32>, + <8 32>, + <10 32>, + <15 64>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpda>; + }; + }; + + port@1 { + reg = <0>; + tpda0_in_tpdm_dl_ct: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dl_ct_out_tpda0>; + }; + }; + + port@2 { + reg = <1>; + tpda1_in_funnel_gpu: endpoint { + slave-mode; + remote-endpoint = + <&funnel_gpu_out_tpda1>; + }; + }; + + port@3 { + reg = <5>; + tpda5_in_funnel_turing: endpoint { + slave-mode; + remote-endpoint = + <&funnel_turing_out_tpda5>; + }; + }; + + port@4 { + reg = <7>; + tpda7_in_tpdm_vsense: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_vsense_out_tpda7>; + }; + }; + + port@5 { + reg = <8>; + tpda8_in_tpdm_dcc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dcc_out_tpda8>; + }; + }; + + port@6 { + reg = <10>; + tpda10_in_tpdm_prng: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_prng_out_tpda10>; + }; + }; + + port@7 { + reg = <11>; + tpda11_in_tpdm_west: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_west_out_tpda11>; + }; + }; + + port@8 { + reg = <12>; + tpda12_in_tpdm_qm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_qm_out_tpda12>; + }; + }; + + port@9 { + reg = <13>; + tpda13_in_tpdm_spdm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_spdm_out_tpda13>; + }; + }; + + port@10 { + reg = <15>; + tpda15_in_tpdm_pimem: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_pimem_out_tpda15>; + }; + }; + + }; + }; + + /delete-node/ cti@8867000; + cti_turing_q6: cti@8862000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8862000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-turing-q6"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; +}; + +#include "bengal-gdsc.dtsi" +#include "khaje-usb.dtsi" +#include "khaje-dma-heaps.dtsi" +#include "pm6125.dtsi" + +&gcc_camss_top_gdsc { + status = "ok"; +}; + +&gcc_ufs_phy_gdsc { + status = "ok"; +}; + +&gcc_usb30_prim_gdsc { + status = "ok"; +}; + +&gcc_vcodec0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&gcc_venus_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc { + status = "ok"; +}; + +&mdss_core_gdsc { + reg = <0x5f01004 0x4>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&gpu_cx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_gx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +#include "msm-arm-smmu-bengal.dtsi" +#include "pm6125-rpm-regulator.dtsi" +#include "khaje-regulator.dtsi" +#include "khaje-pinctrl.dtsi" +#include "bengal-qupv3.dtsi" + +&qupv3_se1_i2c { + status = "ok"; + #include "pm8008.dtsi" +}; + +&pm8008_regulators { + /delete-property/ qcom,enable-ocp-broadcast; +}; + +&pm8008_8 { + /* PM8008 IRQ STAT */ + interrupt-parent = <&tlmm>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8008_active &pm8008_interrupt>; +}; + +&pm8008_regulators { + vdd_l1_l2-supply = <&S6A>; + vdd_l7-supply = <&S7A>; +}; + +&L1P { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + qcom,min-dropout-voltage = <56000>; +}; + +&L2P { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,min-dropout-voltage = <88000>; +}; + +&L3P { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,min-dropout-voltage = <96000>; +}; + +&L4P { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,min-dropout-voltage = <136000>; +}; + +&L5P { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,min-dropout-voltage = <240000>; +}; + +&L6P { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,min-dropout-voltage = <168000>; +}; + +&L7P { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1800000>; + qcom,min-dropout-voltage = <112000>; +}; + +&qupv3_se4_2uart { + status = "ok"; +}; + +&qupv3_se3_4uart { + status = "ok"; +}; + +&pm6125_vadc { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_therm_default &emmc_therm_default>; + + pa_therm0 { + reg = ; + label = "pa_therm0"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + camera_flash_therm { + reg = ; + label = "camera_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + emmc_ufs_therm { + reg = ; + label = "emmc_ufs_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6125_gpios { + camera_therm { + camera_therm_default: camera_therm_default { + pins = "gpio3"; + bias-high-impedance; + }; + }; + + emmc_therm { + emmc_therm_default: emmc_therm_default { + pins = "gpio4"; + bias-high-impedance; + }; + }; + +}; + +&spmi_bus { + qcom,pm6125@0 { + pm6125_adc_tm_iio: adc_tm@3400 { + compatible = "qcom,adc-tm5-iio"; + reg = <0x3400 0x100>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + io-channels = <&pm6125_vadc ADC5_GPIO1_100K_PU>, + <&pm6125_vadc ADC5_GPIO2_100K_PU>; + + camera_flash_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + emmc_ufs_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + }; +}; + +&pm6125_adc_tm { + #address-cells = <1>; + #size-cells = <0>; + io-channels = <&pm6125_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm6125_vadc ADC5_AMUX_THM2_100K_PU>, + <&pm6125_vadc ADC5_XO_THERM_100K_PU>; + + /* Channel nodes */ + pa_therm0 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +#include "bengal-thermal.dtsi" +#include "msm-rdbg.dtsi" + +&cxip_cdev { + status = "disabled"; +}; + +&rpm_bus { + rpm_smd_cdev: rpm-smd-cdev { + compatible = "qcom,rpm-smd-cooling-device"; + #cooling-cells = <2>; + }; +}; + +&thermal_zones { + mapss-lowc { + cooling-maps { + rpm_smd_vdd_cdev { + trip = <&mapss_cap_trip>; + cooling-device = <&rpm_smd_cdev 2 2>; + }; + }; + }; + + camera-lowc { + cooling-maps { + rpm_smd_vdd_cdev { + trip = <&camera_cap_trip>; + cooling-device = <&rpm_smd_cdev 2 2>; + }; + }; + }; +}; diff --git a/qcom/msm-arm-smmu-bengal.dtsi b/qcom/msm-arm-smmu-bengal.dtsi new file mode 100644 index 00000000..95e9a117 --- /dev/null +++ b/qcom/msm-arm-smmu-bengal.dtsi @@ -0,0 +1,161 @@ +#include + +&soc { + apps_smmu: apps-smmu@0xc600000 { + status = "okay"; + compatible = "qcom,qsmmu-v500"; + reg = <0xc600000 0x80000>, + <0xc782000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + qcom,active-only; + + qcom,actlr = + /* For rt TBU +3 deep PF */ + <0x400 0x3ff 0x103>, + /* For nrt TBU +3 deep PF */ + <0x800 0x3ff 0x103>; + + anoc_1_tbu: anoc_1_tbu@0xc785000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc785000 0x1000>, + <0xc782200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + + qcom,active-only; + qcom,iova-width = <36>; + }; + + mm_rt_tbu: mm_rt_tbu@0xc789000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc789000 0x1000>, + <0xc782208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc>; + + qcom,active-only; + qcom,iova-width = <36>; + + }; + + mm_nrt_tbu: mm_nrt_tbu@0xc78d000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc78d000 0x1000>, + <0xc782210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc>; + + qcom,active-only; + qcom,iova-width = <32>; + + }; + + cdsp_tbu: cdsp_tbu@0xc791000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc791000 0x1000>, + <0xc782218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_turing_mmu_tbu0_gdsc>; + + qcom,active-only; + qcom,iova-width = <32>; + }; + }; + + dma_dev { + compatible = "qcom,iommu-dma"; + memory-region = <&system_cma>; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + qcom,iommu-dma = "disabled"; + iommus = <&apps_smmu 0x1e0 0>; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + qcom,iommu-dma = "disabled"; + iommus = <&apps_smmu 0x1e1 0>; + dma-coherent; + }; +}; diff --git a/qcom/pm6125-rpm-regulator.dtsi b/qcom/pm6125-rpm-regulator.dtsi new file mode 100644 index 00000000..b699d861 --- /dev/null +++ b/qcom/pm6125-rpm-regulator.dtsi @@ -0,0 +1,509 @@ +&rpm_bus { + /* VDD_APC supply */ + rpm-regulator-smpa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwmx"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + /* VDD_CX */ + rpm-regulator-smpa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwcx"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + /* VDD_MX */ + rpm-regulator-smpa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwmx"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <6>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <7>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <8>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + /* VDD_WCSS_CX */ + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa11 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l11 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l11"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa13 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l13 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l13"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa14 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l14 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l14"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa15 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l15 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l15"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa16 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <16>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l16 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l16"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa17 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l17 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l17"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa18 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <18>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l18 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l18"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa19 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <19>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l19 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l19"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa20 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <20>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l20 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l20"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa21 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <21>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l21 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l21"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa22 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <22>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l22 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l22"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa23 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <23>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l23 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l23"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa24 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <24>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l24 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l24"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/pm6125.dtsi b/qcom/pm6125.dtsi new file mode 100644 index 00000000..13483ad3 --- /dev/null +++ b/qcom/pm6125.dtsi @@ -0,0 +1,196 @@ +#include +#include +#include +#include +#include + +&spmi_bus { + qcom,pm6125@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 0x0>; + #address-cells = <2>; + #size-cells = <0>; + + pm6125_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + qcom,pon-dbc-delay = <15625>; + qcom,kpdpwr-sw-debounce; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up = <1>; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + qcom,pull-up = <1>; + linux,code = ; + }; + }; + + pm6125_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-vdd-reference = <1875>; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel nodes */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + }; + + pm6125_adc_tm: adc_tm@3500 { + compatible = "qcom,adc-tm5"; + reg = <0x3500 0x100>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "thr-int-en"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + }; + + pm6125_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pm6125_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00 0x100>; + #clock-cells = <1>; + qcom,num-clkdivs = <1>; + clock-output-names = "pm6125_div_clk1"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + assigned-clocks = <&pm6125_clkdiv 1>; + assigned-clock-rates = <9600000>; + }; + + pm6125_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0x900>; + interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, + <0x0 0xc1 0 IRQ_TYPE_NONE>, + <0x0 0xc2 0 IRQ_TYPE_NONE>, + <0x0 0xc3 0 IRQ_TYPE_NONE>, + <0x0 0xc4 0 IRQ_TYPE_NONE>, + <0x0 0xc5 0 IRQ_TYPE_NONE>, + <0x0 0xc6 0 IRQ_TYPE_NONE>, + <0x0 0xc7 0 IRQ_TYPE_NONE>, + <0x0 0xc8 0 IRQ_TYPE_NONE>; + interrupt-names = "pm6125_gpio1", "pm6125_gpio2", + "pm6125_gpio3", "pm6125_gpio4", + "pm6125_gpio5", "pm6125_gpio6", + "pm6125_gpio7", "pm6125_gpio8", + "pm6125_gpio9"; + gpio-controller; + #gpio-cells = <2>; + }; + + pm6125_rtc: qcom,pm6125_rtc { + compatible = "qcom,pm8941-rtc"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + + qcom,pm6125@1 { + compatible ="qcom,spmi-pmic"; + reg = <0x1 0x0>; + #address-cells = <2>; + #size-cells = <0>; + + pm6125_pwm: qcom,pwms@b300 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xb300 0x100>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; + #pwm-cells = <2>; + }; + }; +}; + +&thermal_zones { + pm6125-tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6125_tz>; + wake-capable-sensor; + + trips { + pm6125_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm6125_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/pm7250b.dtsi b/qcom/pm7250b.dtsi new file mode 100644 index 00000000..118a5d1f --- /dev/null +++ b/qcom/pm7250b.dtsi @@ -0,0 +1,641 @@ +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm7250b@2 { + compatible = "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm7250b_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + pm7250b_pon: qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + }; + + pm7250b_charger: qcom,qpnp-smb5 { + compatible = "qcom,qpnp-smb5"; + #address-cells = <1>; + #size-cells = <1>; + #cooling-cells = <2>; + + qcom,thermal-mitigation = <5400000 4500000 4000000 + 3500000 3000000 2500000 2000000 1500000 + 1000000 500000>; + qcom,pmic-revid = <&pm7250b_revid>; + qcom,hvdcp2-max-icl-ua = <2000000>; + qcom,hvdcp2-12v-max-icl-ua = <1500000>; + + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = + <0x2 0x10 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x4 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "chgr-error", + "chg-state-change", + "step-chg-state-change", + "step-chg-soc-update-fail", + "step-chg-soc-update-req", + "fg-fvcal-qualified", + "vph-alarm", + "vph-drop-prechg"; + }; + + qcom,dcdc@1100 { + reg = <0x1100 0x100>; + interrupts = + <0x2 0x11 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x11 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x11 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x11 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x11 0x7 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "otg-fail", + "otg-oc-disable-sw", + "otg-oc-hiccup", + "bsm-active", + "high-duty-cycle", + "input-current-limiting", + "concurrent-mode-disable", + "switcher-power-ok"; + }; + + qcom,batif@1200 { + reg = <0x1200 0x100>; + interrupts = + <0x2 0x12 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x6 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x7 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "bat-temp", + "bat-ov", + "bat-low", + "bat-therm-or-id-missing", + "bat-terminal-missing", + "buck-oc", + "vph-ov"; + }; + + qcom,usb@1300 { + reg = <0x1300 0x100>; + interrupts = + <0x2 0x13 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x13 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "usbin-collapse", + "usbin-vashdn", + "usbin-uv", + "usbin-ov", + "usbin-plugin", + "usbin-revi-change", + "usbin-src-change", + "usbin-icl-change"; + }; + + qcom,dc@1400 { + reg = <0x1400 0x100>; + interrupts = + <0x2 0x14 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x14 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dcin-vashdn", + "dcin-uv", + "dcin-ov", + "dcin-plugin", + "dcin-revi", + "dcin-pon", + "dcin-en"; + }; + + qcom,typec@1500 { + reg = <0x1500 0x100>; + interrupts = + <0x2 0x15 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x4 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "typec-or-rid-detect-change", + "typec-vpd-detect", + "typec-cc-state-change", + "typec-vconn-oc", + "typec-vbus-change", + "typec-attach-detach", + "typec-legacy-cable-detect", + "typec-try-snk-src-detect"; + }; + + qcom,misc@1600 { + reg = <0x1600 0x100>; + interrupts = + <0x2 0x16 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog-snarl", + "wdog-bark", + "aicl-fail", + "aicl-done", + "smb-en", + "imp-trigger", + "temp-change", + "temp-change-smb"; + }; + + qcom,chg-sdam@b000 { + reg = <0xb000 0x100>; + }; + }; + + pm7250b_pdphy: qcom,usb-pdphy@1700 { + compatible = "qcom,qpnp-pdphy"; + reg = <0x1700 0x100>; + interrupts = <0x2 0x17 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x4 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "sig-tx", + "sig-rx", + "msg-tx", + "msg-rx", + "msg-tx-failed", + "msg-tx-discarded", + "msg-rx-discarded", + "fr-swap"; + + qcom,default-sink-caps = <5000 3000>, /* 5V @ 3A */ + <9000 3000>, /* 9V @ 3A */ + <12000 2250>; /* 12V @ 2.25A */ + }; + + pm7250b_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm7250b_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pm7250b_qg: qpnp,qg { + compatible = "qcom,qpnp-qg"; + #address-cells = <1>; + #size-cells = <1>; + + qcom,vbatt-cutoff-mv = <3200>; + qcom,vbatt-low-mv = <3300>; + qcom,vbatt-low-cold-mv = <3700>; + qcom,vbatt-empty-mv = <3000>; + qcom,vbatt-empty-cold-mv = <3000>; + qcom,s3-entry-fifo-length = <2>; + + qcom,pmic-revid = <&pm7250b_revid>; + + qcom,qgauge@4800 { + status = "okay"; + reg = <0x4800 0x100>; + interrupts = + <0x2 0x48 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x48 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x48 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x48 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x48 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "qg-batt-missing", + "qg-vbat-low", + "qg-vbat-empty", + "qg-fifo-done", + "qg-good-ocv"; + }; + + qcom,qg-sdam@b100 { + status = "okay"; + reg = <0xb100 0x100>; + }; + }; + + pm7250b_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00 0x100>; + #clock-cells = <1>; + qcom,num-clkdivs = <1>; + clock-output-names = "pm7250b_div_clk1"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + assigned-clocks = <&pm7250b_clkdiv 1>; + assigned-clock-rates = <19200000>; + }; + + pm7250b_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0xc00>; + interrupts = <0x2 0xc0 0x0 IRQ_TYPE_NONE>, + <0x2 0xc1 0x0 IRQ_TYPE_NONE>, + <0x2 0xc2 0x0 IRQ_TYPE_NONE>, + <0x2 0xc3 0x0 IRQ_TYPE_NONE>, + <0x2 0xc4 0x0 IRQ_TYPE_NONE>, + <0x2 0xc5 0x0 IRQ_TYPE_NONE>, + <0x2 0xc6 0x0 IRQ_TYPE_NONE>, + <0x2 0xc7 0x0 IRQ_TYPE_NONE>, + <0x2 0xc8 0x0 IRQ_TYPE_NONE>, + <0x2 0xc9 0x0 IRQ_TYPE_NONE>, + <0x2 0xca 0x0 IRQ_TYPE_NONE>, + <0x2 0xcb 0x0 IRQ_TYPE_NONE>; + interrupt-names = "pm7250b_gpio1", "pm7250b_gpio2", + "pm7250b_gpio3", "pm7250b_gpio4", + "pm7250b_gpio5", "pm7250b_gpio6", + "pm7250b_gpio7", "pm7250b_gpio8", + "pm7250b_gpio9", "pm7250b_gpio10", + "pm7250b_gpio11", "pm7250b_gpio12"; + gpio-controller; + #gpio-cells = <2>; + }; + + pm7250b_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100 0x100>; + reg-names = "adc5-usr-base"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-vdd-reference = <1875>; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + ref_gnd@0 { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25@1 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp@2 { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr@83 { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vbat_sns@84 { + reg = ; + label = "vbat_sns"; + qcom,pre-scaling = <1 3>; + }; + + usb_in_i_uv@7 { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16@8 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; + + chg_temp@9 { + reg = ; + label = "chg_temp"; + qcom,pre-scaling = <1 1>; + }; + + bat_therm@4a { + reg = ; + label = "bat_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_30k@2a { + reg = ; + label = "bat_therm_30k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_400k@6a { + reg = ; + label = "bat_therm_400k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_id@4b { + reg = ; + label = "bat_id"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + smb1390_therm@e { + reg = ; + label = "smb1390_therm"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + chg_sbux@99 { + reg = ; + label = "chg_sbux"; + qcom,pre-scaling = <1 3>; + }; + + mid_chg_div6@1e { + reg = ; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; + + v_i_int_ext@b0 { + reg = ; + label = "v_i_int_vbat_vdata"; + qcom,pre-scaling = <1 1>; + }; + + v_i_parallel@b0 { + reg = ; + label = "v_i_parallel_vbat_vdata"; + qcom,pre-scaling = <1 1>; + }; + }; + + pm7250b_adc_tm: adc_tm@3500 { + compatible = "qcom,adc-tm5"; + reg = <0x3500 0x100>; + interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "thr-int-en"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + }; + + pm7250b_bcl: bcl@1d00 { + compatible = "qcom,bcl-v5"; + reg = <0x1d00 0x100>; + interrupts = <0x2 0x1d 0x0 IRQ_TYPE_NONE>, + <0x2 0x1d 0x1 IRQ_TYPE_NONE>, + <0x2 0x1d 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-lvl0", + "bcl-lvl1", + "bcl-lvl2"; + #thermal-sensor-cells = <1>; + }; + + bcl_soc:bcl-soc { + compatible = "qcom,msm-bcl-soc"; + #thermal-sensor-cells = <0>; + }; + }; + + qcom,pm7250b@3 { + compatible = "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm7250b_vib: qcom,vibrator@5300 { + compatible = "qcom,qpnp-vibrator-ldo"; + reg = <0x5300 0x100>; + qcom,vib-ldo-volt-uv = <3000000>; + qcom,disable-overdrive; + }; + }; +}; + +&thermal_zones { + pm7250b_temp_alarm: pm7250b-tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7250b_tz>; + wake-capable-sensor; + + trips { + pm7250b_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm7250b_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + pm7250b-ibat-lvl0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7250b_bcl 0>; + wake-capable-sensor; + + trips { + ibat_lvl0:ibat-lvl0 { + temperature = <5500>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm7250b-ibat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7250b_bcl 1>; + wake-capable-sensor; + + trips { + ibat_lvl1:ibat-lvl1 { + temperature = <6000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm7250b-vbat-lvl0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&pm7250b_bcl 2>; + wake-capable-sensor; + tracks-low; + + trips { + vbat_lvl0: vbat-lvl0 { + temperature = <3000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm7250b-vbat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&pm7250b_bcl 3>; + wake-capable-sensor; + tracks-low; + + trips { + vbat_lvl1:vbat-lvl1 { + temperature = <2800>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm7250b-vbat-lvl2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&pm7250b_bcl 4>; + wake-capable-sensor; + tracks-low; + + trips { + vbat_lvl2:vbat-lvl2 { + temperature = <2600>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm7250b-bcl-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7250b_bcl 5>; + wake-capable-sensor; + + trips { + b_bcl_lvl0: b-bcl-lvl0 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm7250b-bcl-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7250b_bcl 6>; + wake-capable-sensor; + + trips { + b_bcl_lvl1: b-bcl-lvl1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm7250b-bcl-lvl2 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7250b_bcl 7>; + wake-capable-sensor; + + trips { + b_bcl_lvl2: b-bcl-lvl2 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + soc { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&bcl_soc>; + wake-capable-sensor; + tracks-low; + + trips { + soc_trip:soc-trip { + temperature = <10>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/pm8008.dtsi b/qcom/pm8008.dtsi new file mode 100644 index 00000000..f4fc4e88 --- /dev/null +++ b/qcom/pm8008.dtsi @@ -0,0 +1,127 @@ +#include + +pm8008_8: qcom,pm8008@8 { + compatible = "qcom,i2c-pmic"; + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + + interrupt-names = "pm8008"; + qcom,periph-map = <0x09 0x24 0xc0 0xc1>; + + pm8008_chip: qcom,pm8008-chip@900 { + compatible = "qcom,pm8008-chip"; + reg = <0x900>; + interrupts = <0x09 4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ocp"; + + PM8008_EN: qcom,pm8008-chip-en { + regulator-name = "pm8008-chip-en"; + }; + }; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100>; + }; + + pm8008_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0x200>; + interrupts = <0xc0 0 IRQ_TYPE_EDGE_RISING>, + <0xc1 0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "pm8008_gpio1", "pm8008_gpio2"; + gpio-controller; + #gpio-cells = <2>; + + pm8008_gpio1_active: pm8008_gpio1_active { + pins = "gpio1"; + function = "func1"; + power-source = <1>; + output-enable; + input-disable; + bias-disable; + }; + }; +}; + +pm8008_9: qcom,pm8008@9 { + compatible = "qcom,i2c-pmic"; + reg = <0x9>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8008_gpio1_active>; + + pm8008_regulators: qcom,pm8008-regulator { + compatible = "qcom,pm8008-regulator"; + pm8008_en-supply = <&PM8008_EN>; + qcom,enable-ocp-broadcast; + + L1P: qcom,pm8008-l1@4000 { + reg = <0x4000>; + regulator-name = "pm8008_l1"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1504000>; + qcom,min-dropout-voltage = <225000>; + qcom,hpm-min-load = <0>; + }; + + L2P: qcom,pm8008-l2@4100 { + reg = <0x4100>; + regulator-name = "pm8008_l2"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1504000>; + qcom,min-dropout-voltage = <225000>; + qcom,hpm-min-load = <0>; + }; + + L3P: qcom,pm8008-l3@4200 { + reg = <0x4200>; + regulator-name = "pm8008_l3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <0>; + }; + + L4P: qcom,pm8008-l4@4300 { + reg = <0x4300>; + regulator-name = "pm8008_l4"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <0>; + }; + + L5P: qcom,pm8008-l5@4400 { + reg = <0x4400>; + regulator-name = "pm8008_l5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <0>; + }; + + L6P: qcom,pm8008-l6@4400 { + reg = <0x4500>; + regulator-name = "pm8008_l6"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <0>; + }; + + L7P: qcom,pm8008-l7@4400 { + reg = <0x4600>; + regulator-name = "pm8008_l7"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <0>; + }; + }; +}; diff --git a/qcom/qg-batterydata-alium-3600mah.dtsi b/qcom/qg-batterydata-alium-3600mah.dtsi new file mode 100644 index 00000000..051f6416 --- /dev/null +++ b/qcom/qg-batterydata-alium-3600mah.dtsi @@ -0,0 +1,1035 @@ +qcom,alium_860_89032_0000_3600mAh { + /* Alium_860_89032_0000_3600mAh_averaged_MasterSlave_Jun15th2018 */ + qcom,max-voltage-uv = <4350000>; + qcom,fg-cc-cv-threshold-uv = <4340000>; + qcom,fastchg-current-ma = <5400>; + qcom,batt-id-kohm = <107>; + qcom,battery-beta = <4250>; + qcom,battery-therm-kohm = <100>; + qcom,battery-type = "Alium_860_89032_0000_3600mAh_Jun15th2018"; + qcom,qg-batt-profile-ver = <100>; + + qcom,jeita-fcc-ranges = <0 50 2500000 + 51 400 5400000 + 401 450 2500000>; + qcom,jeita-fv-ranges = <0 50 4250000 + 51 400 4350000 + 401 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 5400000 + 3800001 4300000 3600000 + 4300001 4350000 2500000>; + qcom,ocv-based-step-chg; + + /* COOL = 5 DegC, WARM = 40 DegC */ + qcom,jeita-soft-thresholds = <0x5314 0x25e3>; + /* COLD = 0 DegC, HOT = 45 DegC */ + qcom,jeita-hard-thresholds = <0x58cd 0x20b8>; + /* COOL hys = 8 DegC, WARM hys = 37 DegC */ + qcom,jeita-soft-hys-thresholds = <0x4f5e 0x2943>; + qcom,jeita-soft-fcc-ua = <2500000 2500000>; + qcom,jeita-soft-fv-uv = <4250000 4250000>; + + qcom,fcc1-temp-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-data = <3426 3519 3581 3613 3630>; + }; + + qcom,fcc2-temp-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-data = <3546 3576 3586 3588 3583 3583>; + }; + + qcom,pc-temp-v1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <43078 43267 43365 43394 43399>, + <42839 43052 43147 43186 43196>, + <42609 42823 42920 42964 42981>, + <42392 42591 42693 42738 42759>, + <42186 42370 42469 42513 42535>, + <41983 42159 42248 42289 42310>, + <41776 41953 42032 42066 42085>, + <41565 41745 41820 41847 41863>, + <41376 41534 41607 41630 41645>, + <41226 41338 41393 41412 41426>, + <41086 41189 41206 41205 41212>, + <40873 41057 41063 41032 41014>, + <40523 40858 40918 40878 40833>, + <40155 40509 40680 40678 40639>, + <39917 40145 40325 40390 40407>, + <39757 39925 40039 40116 40180>, + <39638 39781 39894 39960 40010>, + <39541 39669 39779 39850 39877>, + <39455 39579 39646 39699 39715>, + <39364 39489 39487 39469 39489>, + <39266 39366 39306 39235 39257>, + <39165 39210 39096 39058 39072>, + <39060 39042 38900 38912 38919>, + <38955 38854 38767 38784 38785>, + <38859 38675 38671 38668 38668>, + <38773 38551 38581 38562 38562>, + <38692 38462 38490 38466 38462>, + <38619 38394 38403 38377 38369>, + <38552 38343 38327 38296 38283>, + <38491 38301 38257 38222 38203>, + <38439 38261 38195 38156 38132>, + <38392 38224 38142 38097 38067>, + <38348 38190 38095 38043 38010>, + <38306 38161 38052 37989 37952>, + <38265 38135 38015 37938 37895>, + <38223 38102 37976 37886 37836>, + <38181 38066 37935 37830 37771>, + <38128 38020 37890 37771 37701>, + <38054 37950 37823 37699 37623>, + <37964 37850 37727 37613 37538>, + <37862 37740 37617 37512 37439>, + <37739 37617 37494 37390 37318>, + <37601 37487 37361 37256 37185>, + <37448 37354 37221 37119 37052>, + <37327 37238 37120 37019 36955>, + <37241 37161 37057 36960 36898>, + <37209 37134 37035 36943 36881>, + <37182 37113 37018 36927 36865>, + <37146 37086 36991 36896 36829>, + <37036 36976 36855 36724 36634>, + <36712 36636 36510 36372 36278>, + <36253 36181 36056 35916 35819>, + <35673 35600 35476 35330 35231>, + <34889 34811 34685 34533 34429>, + <33644 33573 33450 33289 33175>, + <30000 30000 30000 30000 30000>; + }; + + qcom,pc-temp-v2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <43405 43390 43380 43360 43310 43280>, + <43003 43066 43092 43094 43055 43033>, + <42659 42770 42823 42839 42808 42792>, + <42388 42505 42573 42597 42570 42556>, + <42183 42269 42342 42369 42341 42328>, + <41972 42046 42121 42146 42116 42104>, + <41647 41828 41907 41928 41893 41879>, + <41314 41618 41700 41715 41674 41657>, + <41242 41409 41488 41499 41455 41438>, + <41295 41194 41265 41273 41232 41219>, + <41338 41020 41073 41079 41031 41013>, + <41030 40918 40949 40949 40883 40839>, + <40301 40831 40837 40833 40747 40674>, + <39816 40619 40617 40621 40542 40474>, + <39553 40056 40158 40222 40214 40226>, + <39352 39574 39750 39893 39934 39999>, + <39187 39400 39544 39757 39792 39836>, + <39047 39287 39391 39659 39684 39694>, + <38903 39154 39240 39507 39524 39512>, + <38748 38998 39093 39269 39281 39271>, + <38600 38840 38951 39039 39045 39043>, + <38473 38688 38809 38867 38872 38870>, + <38360 38541 38673 38723 38728 38725>, + <38269 38408 38551 38598 38603 38600>, + <38195 38289 38441 38488 38492 38488>, + <38132 38186 38339 38387 38390 38385>, + <38076 38102 38245 38293 38296 38290>, + <38026 38033 38158 38206 38208 38200>, + <37976 37977 38077 38128 38127 38118>, + <37929 37931 38001 38058 38053 38043>, + <37882 37891 37932 37991 37985 37974>, + <37835 37852 37869 37926 37922 37912>, + <37786 37815 37814 37863 37863 37853>, + <37734 37776 37764 37798 37793 37778>, + <37680 37735 37722 37732 37704 37675>, + <37621 37692 37680 37666 37610 37565>, + <37558 37641 37633 37602 37526 37469>, + <37492 37582 37583 37538 37448 37384>, + <37421 37513 37524 37470 37374 37308>, + <37348 37429 37450 37396 37302 37235>, + <37274 37332 37362 37312 37222 37156>, + <37201 37229 37261 37208 37121 37056>, + <37130 37124 37145 37082 36997 36933>, + <37054 37029 37028 36964 36881 36820>, + <36966 36949 36952 36902 36830 36771>, + <36849 36873 36903 36875 36801 36743>, + <36768 36823 36880 36854 36784 36726>, + <36666 36763 36850 36823 36756 36699>, + <36509 36668 36775 36740 36671 36604>, + <36284 36467 36557 36486 36422 36338>, + <35954 36107 36161 36071 36005 35919>, + <35477 35597 35626 35539 35482 35397>, + <34808 34917 34941 34844 34796 34717>, + <33818 33942 34003 33928 33918 33830>, + <32458 32548 32795 32808 32663 32496>, + <28619 28270 28017 28020 27984 27930>; + }; + + qcom,pc-temp-z1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <14545 13238 12041 11680 11593>, + <14523 13183 12045 11678 11602>, + <14531 13174 12043 11685 11612>, + <14535 13182 12039 11687 11616>, + <14547 13186 12035 11688 11618>, + <14571 13181 12033 11688 11620>, + <14591 13164 12034 11689 11623>, + <14582 13150 12035 11692 11626>, + <14551 13149 12037 11694 11629>, + <14518 13154 12041 11697 11631>, + <14486 13152 12045 11701 11634>, + <14452 13134 12047 11704 11639>, + <14403 13116 12047 11707 11643>, + <14352 13102 12043 11707 11644>, + <14318 13096 12036 11705 11644>, + <14291 13097 12033 11703 11644>, + <14262 13097 12036 11707 11647>, + <14226 13100 12042 11714 11653>, + <14194 13111 12052 11721 11659>, + <14181 13129 12065 11726 11663>, + <14179 13150 12076 11731 11667>, + <14186 13172 12085 11736 11672>, + <14195 13188 12093 11741 11676>, + <14207 13195 12101 11745 11681>, + <14215 13201 12109 11751 11686>, + <14220 13210 12116 11756 11690>, + <14223 13222 12123 11760 11695>, + <14228 13229 12130 11764 11699>, + <14239 13234 12137 11768 11703>, + <14255 13242 12143 11772 11707>, + <14279 13250 12149 11776 11711>, + <14302 13257 12154 11780 11716>, + <14310 13265 12160 11784 11720>, + <14314 13278 12166 11789 11725>, + <14320 13297 12174 11794 11729>, + <14343 13315 12181 11799 11733>, + <14395 13333 12189 11802 11736>, + <14443 13346 12197 11804 11738>, + <14481 13351 12202 11807 11740>, + <14512 13353 12205 11809 11741>, + <14514 13357 12209 11811 11742>, + <14472 13369 12217 11813 11744>, + <14451 13384 12223 11815 11745>, + <14446 13399 12224 11816 11746>, + <14433 13385 12228 11817 11746>, + <14447 13396 12231 11819 11746>, + <14441 13396 12232 11819 11745>, + <14440 13403 12233 11819 11746>, + <14431 13399 12239 11820 11747>, + <14460 13394 12241 11824 11750>, + <14470 13423 12251 11830 11755>, + <14506 13430 12275 11839 11760>, + <14485 13470 12295 11850 11770>, + <14544 13512 12338 11868 11782>, + <14544 13512 12338 11868 11782>, + <14544 13512 12338 11868 11782>; + }; + + qcom,pc-temp-z2-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <11192 9778 10257 10603 10910>, + <10253 10813 10276 10490 10558>, + <9726 10534 10287 10428 10436>, + <9734 10061 10282 10413 10412>, + <9760 9938 10269 10392 10406>, + <9775 9923 10261 10380 10404>, + <9777 9909 10257 10375 10408>, + <9772 9898 10258 10370 10412>, + <9765 9890 10262 10368 10412>, + <9755 9884 10265 10372 10421>, + <9746 9880 10259 10375 10444>, + <9750 9878 10227 10382 10452>, + <9766 9881 10199 10414 10451>, + <9772 9895 10216 10429 10452>, + <9752 9907 10260 10399 10450>, + <9717 9910 10282 10371 10439>, + <9701 9914 10279 10383 10449>, + <9697 9923 10269 10418 10506>, + <9693 9949 10295 10465 10551>, + <9686 9981 10388 10545 10559>, + <9673 10014 10446 10602 10559>, + <9662 10050 10419 10553 10531>, + <9655 10080 10371 10429 10478>, + <9649 10101 10339 10379 10444>, + <9631 10116 10316 10398 10420>, + <9588 10124 10303 10422 10405>, + <9554 10131 10300 10409 10406>, + <9540 10135 10301 10384 10415>, + <9483 10134 10309 10376 10426>, + <9426 10131 10329 10376 10445>, + <9408 10130 10351 10380 10472>, + <9395 10131 10373 10399 10506>, + <9386 10133 10396 10437 10548>, + <9378 10137 10420 10474 10594>, + <9372 10146 10446 10506 10651>, + <9368 10154 10463 10533 10695>, + <9374 10162 10468 10556 10712>, + <9380 10167 10471 10580 10722>, + <9389 10171 10479 10593 10733>, + <9398 10176 10491 10596 10745>, + <9397 10178 10497 10597 10753>, + <9384 10169 10490 10609 10755>, + <9380 10140 10483 10625 10759>, + <9386 9964 10481 10631 10781>, + <9324 9926 10454 10642 10811>, + <9305 9932 10438 10669 10808>, + <9287 9948 10463 10697 10858>, + <9289 9933 10557 10698 10889>, + <9274 9965 10622 10758 10917>, + <9278 9923 10533 10711 10837>, + <9316 9884 10462 10634 10693>, + <9326 9807 10425 10609 10671>, + <9285 9724 10395 10535 10591>, + <9245 9615 10285 10458 10500>, + <9245 9615 10285 10458 10500>, + <9245 9615 10285 10458 10500>; + }; + + qcom,pc-temp-z3-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <19525 19431 19373 19383 19355>, + <19784 19494 19408 19370 19350>, + <19920 19574 19438 19372 19351>, + <19937 19651 19450 19380 19356>, + <19918 19673 19455 19382 19359>, + <19895 19676 19456 19383 19362>, + <19884 19677 19454 19381 19362>, + <19879 19677 19451 19376 19359>, + <19877 19680 19448 19372 19355>, + <19874 19682 19446 19372 19353>, + <19872 19668 19440 19372 19352>, + <19877 19628 19423 19367 19352>, + <19894 19610 19400 19355 19349>, + <19909 19638 19406 19350 19345>, + <19892 19671 19439 19363 19347>, + <19843 19665 19457 19379 19351>, + <19796 19628 19436 19373 19348>, + <19760 19594 19408 19356 19338>, + <19726 19567 19407 19352 19335>, + <19697 19550 19425 19366 19342>, + <19672 19554 19438 19379 19351>, + <19654 19573 19439 19379 19357>, + <19644 19591 19439 19374 19361>, + <19636 19603 19437 19373 19362>, + <19628 19612 19434 19380 19360>, + <19619 19613 19433 19386 19358>, + <19607 19611 19439 19383 19356>, + <19596 19607 19445 19378 19354>, + <19583 19601 19446 19374 19352>, + <19567 19594 19444 19369 19350>, + <19549 19588 19442 19365 19348>, + <19530 19583 19439 19362 19345>, + <19514 19578 19434 19360 19342>, + <19499 19571 19431 19359 19338>, + <19486 19563 19429 19358 19334>, + <19479 19557 19426 19358 19332>, + <19483 19551 19422 19358 19332>, + <19491 19546 19418 19357 19334>, + <19513 19542 19415 19356 19334>, + <19535 19539 19414 19351 19331>, + <19526 19535 19412 19347 19329>, + <19496 19530 19410 19347 19330>, + <19483 19519 19408 19347 19330>, + <19481 19451 19404 19347 19331>, + <19372 19379 19382 19344 19327>, + <19345 19348 19360 19337 19320>, + <19337 19340 19358 19328 19312>, + <19339 19335 19342 19326 19312>, + <19316 19318 19331 19324 19309>, + <19320 19317 19352 19335 19324>, + <19371 19345 19355 19339 19331>, + <19418 19350 19357 19342 19332>, + <19442 19348 19353 19346 19335>, + <19464 19360 19359 19349 19340>, + <19464 19360 19359 19349 19340>, + <19464 19360 19359 19349 19340>; + }; + + qcom,pc-temp-z4-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <16385 15501 14962 14712 14715>, + <16621 15491 14959 14790 14777>, + <16602 15456 14922 14802 14786>, + <16518 15370 14881 14784 14773>, + <16384 15265 14843 14759 14750>, + <16241 15178 14812 14736 14726>, + <16119 15106 14786 14721 14710>, + <16009 15051 14764 14710 14700>, + <15894 15008 14752 14704 14694>, + <15746 14969 14746 14701 14689>, + <15604 14928 14744 14698 14685>, + <15557 14895 14744 14693 14681>, + <15579 14889 14745 14687 14673>, + <15600 14901 14749 14689 14670>, + <15554 14908 14754 14704 14683>, + <15436 14889 14752 14715 14696>, + <15339 14846 14732 14699 14686>, + <15282 14813 14713 14669 14663>, + <15245 14793 14712 14671 14662>, + <15230 14781 14722 14728 14708>, + <15221 14780 14742 14778 14758>, + <15217 14783 14794 14782 14763>, + <15221 14793 14846 14777 14751>, + <15227 14842 14846 14766 14737>, + <15232 14904 14815 14739 14722>, + <15237 14918 14783 14717 14709>, + <15244 14915 14759 14707 14700>, + <15250 14910 14740 14702 14693>, + <15262 14895 14729 14697 14687>, + <15275 14872 14722 14693 14682>, + <15283 14853 14717 14690 14677>, + <15290 14837 14715 14686 14673>, + <15294 14821 14714 14682 14670>, + <15292 14806 14713 14682 14669>, + <15285 14792 14713 14684 14672>, + <15265 14778 14712 14686 14677>, + <15218 14764 14710 14689 14683>, + <15171 14753 14707 14691 14689>, + <15100 14750 14704 14691 14691>, + <15036 14748 14701 14691 14688>, + <15028 14745 14698 14690 14685>, + <15035 14740 14695 14688 14684>, + <15033 14741 14690 14685 14683>, + <15011 14800 14682 14681 14680>, + <15037 14827 14679 14667 14668>, + <15046 14838 14675 14645 14644>, + <15051 14840 14669 14641 14637>, + <15043 14842 14681 14633 14624>, + <15056 14851 14689 14629 14622>, + <15040 14847 14670 14638 14636>, + <15003 14839 14678 14645 14640>, + <14990 14846 14681 14646 14645>, + <14996 14862 14691 14647 14646>, + <15017 14877 14695 14650 14646>, + <15017 14877 14695 14650 14646>, + <15017 14877 14695 14650 14646>; + }; + + qcom,pc-temp-z5-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <11068 11690 13464 19085 17868>, + <12016 12370 14843 18209 18510>, + <12567 13373 16287 18434 19041>, + <12767 14431 17166 19331 19871>, + <12906 14953 17644 19970 20772>, + <13043 15275 18035 20553 21985>, + <13254 15589 18448 20812 22838>, + <13520 16021 18878 20763 23075>, + <13787 16665 19253 20832 23069>, + <14074 17170 19532 21287 23403>, + <14425 17078 19373 21540 24108>, + <14893 16220 17894 20839 24888>, + <15428 16083 16100 18925 24832>, + <15715 18342 16976 18223 24189>, + <15770 20589 20553 20659 24472>, + <15797 20502 22513 23616 25498>, + <15834 19565 21295 23828 25788>, + <15830 19061 19385 22969 25708>, + <15750 18918 21990 23440 25684>, + <15580 18870 30436 27428 25707>, + <15309 20532 34653 30469 25746>, + <15057 25755 30884 27232 24220>, + <14852 31080 25218 20500 20766>, + <14649 35866 22212 18547 19399>, + <14406 39481 20440 20518 19854>, + <14102 39590 19963 22400 20596>, + <13801 37343 21441 23200 21434>, + <13549 34779 23939 23840 22513>, + <13290 32437 26091 24203 23750>, + <13021 30286 28345 24605 25226>, + <12746 29196 30150 25017 26620>, + <12479 28629 31211 25585 27804>, + <12282 28181 32038 26640 28805>, + <12126 27688 32872 28101 29029>, + <11990 27267 33745 30291 28636>, + <11896 27207 34089 31579 28289>, + <11945 27442 32771 31455 28513>, + <12049 27808 30864 31087 28942>, + <12350 28315 30537 30322 28828>, + <12671 28953 30633 27821 27284>, + <12642 29117 30687 26060 26101>, + <12299 27717 30577 26308 26287>, + <12208 24781 30313 26635 26505>, + <12309 16408 28848 26643 26112>, + <11428 13096 22891 26468 25271>, + <11198 12322 18301 26248 25109>, + <11112 12144 18213 22490 22887>, + <11116 12041 15832 22757 25790>, + <10935 11705 14733 23506 25696>, + <10976 11757 17791 27597 30144>, + <11440 12275 17295 25361 28944>, + <11648 12197 17311 24873 26253>, + <11657 11966 16067 25059 25290>, + <11600 11884 16052 23410 24581>, + <11600 11884 16052 23410 24581>, + <11600 11884 16052 23410 24581>; + }; + + qcom,pc-temp-z6-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <16538 15406 14813 14639 14611>, + <16749 15432 14830 14667 14637>, + <16795 15447 14830 14674 14643>, + <16769 15440 14820 14671 14641>, + <16699 15411 14805 14663 14634>, + <16612 15372 14791 14653 14625>, + <16540 15333 14779 14645 14619>, + <16482 15307 14768 14638 14613>, + <16423 15289 14762 14634 14608>, + <16352 15271 14759 14633 14606>, + <16282 15242 14755 14632 14604>, + <16243 15204 14746 14628 14603>, + <16229 15190 14734 14620 14598>, + <16213 15202 14738 14617 14595>, + <16158 15216 14756 14631 14602>, + <16064 15204 14764 14643 14610>, + <15984 15167 14745 14634 14604>, + <15930 15138 14722 14613 14590>, + <15887 15120 14722 14612 14588>, + <15858 15110 14737 14646 14613>, + <15836 15113 14757 14675 14640>, + <15826 15129 14785 14678 14644>, + <15826 15150 14807 14675 14644>, + <15831 15182 14806 14671 14642>, + <15836 15213 14793 14664 14635>, + <15841 15221 14782 14658 14628>, + <15846 15221 14776 14653 14623>, + <15850 15220 14772 14648 14620>, + <15854 15214 14769 14645 14617>, + <15856 15204 14766 14641 14614>, + <15856 15196 14763 14638 14611>, + <15856 15188 14761 14635 14608>, + <15855 15180 14760 14632 14605>, + <15853 15174 14759 14632 14604>, + <15851 15168 14759 14633 14604>, + <15851 15164 14758 14634 14604>, + <15853 15160 14756 14636 14607>, + <15855 15157 14754 14637 14611>, + <15855 15157 14752 14637 14612>, + <15854 15158 14751 14634 14610>, + <15851 15158 14750 14632 14608>, + <15842 15157 14749 14631 14608>, + <15832 15156 14747 14631 14607>, + <15821 15148 14743 14630 14607>, + <15777 15126 14731 14621 14600>, + <15764 15120 14719 14609 14585>, + <15763 15114 14716 14602 14578>, + <15759 15116 14713 14598 14572>, + <15757 15111 14711 14595 14570>, + <15765 15116 14716 14605 14584>, + <15777 15136 14723 14612 14591>, + <15805 15152 14732 14616 14594>, + <15840 15173 14739 14621 14598>, + <15893 15213 14754 14628 14605>, + <15893 15213 14754 14628 14605>, + <15893 15213 14754 14628 14605>; + }; + + qcom,pc-temp-y1-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <7598 6764 6071 5440 5223 5179>, + <7604 6767 6083 5439 5222 5181>, + <7616 6772 6090 5438 5222 5182>, + <7629 6778 6094 5436 5222 5184>, + <7640 6782 6096 5435 5223 5185>, + <7645 6784 6096 5434 5223 5187>, + <7644 6784 6092 5434 5224 5187>, + <7642 6784 6086 5434 5226 5188>, + <7635 6781 6085 5435 5228 5189>, + <7612 6774 6088 5436 5229 5190>, + <7594 6768 6090 5437 5231 5192>, + <7603 6766 6086 5437 5232 5193>, + <7624 6767 6080 5437 5234 5195>, + <7644 6772 6081 5438 5236 5197>, + <7668 6789 6096 5445 5241 5202>, + <7683 6807 6107 5453 5244 5204>, + <7674 6820 6111 5455 5244 5205>, + <7655 6831 6115 5458 5245 5205>, + <7640 6832 6116 5460 5246 5206>, + <7626 6817 6114 5461 5248 5209>, + <7619 6805 6114 5464 5251 5212>, + <7638 6807 6125 5468 5255 5216>, + <7673 6815 6139 5472 5259 5219>, + <7681 6821 6141 5477 5262 5223>, + <7680 6824 6136 5481 5265 5226>, + <7684 6828 6135 5485 5267 5230>, + <7689 6840 6144 5489 5270 5234>, + <7692 6860 6155 5494 5274 5237>, + <7690 6871 6158 5499 5277 5240>, + <7672 6876 6162 5505 5280 5242>, + <7648 6878 6167 5510 5283 5245>, + <7641 6875 6171 5515 5287 5248>, + <7643 6871 6175 5520 5290 5252>, + <7645 6871 6176 5523 5293 5255>, + <7649 6869 6177 5526 5296 5257>, + <7656 6867 6179 5529 5298 5259>, + <7671 6879 6183 5531 5300 5260>, + <7690 6895 6188 5533 5301 5261>, + <7693 6895 6193 5534 5301 5262>, + <7679 6883 6197 5535 5302 5262>, + <7669 6879 6202 5537 5303 5263>, + <7670 6885 6209 5541 5305 5265>, + <7670 6891 6220 5544 5306 5266>, + <7670 6898 6217 5546 5307 5267>, + <7674 6904 6224 5551 5310 5269>, + <7684 6923 6224 5553 5310 5270>, + <7689 6920 6233 5556 5310 5270>, + <7718 6926 6243 5556 5310 5270>, + <7735 6923 6251 5558 5311 5270>, + <7724 6942 6247 5561 5314 5272>, + <7721 6975 6265 5570 5317 5275>, + <7736 7003 6293 5585 5324 5280>, + <7777 7007 6312 5604 5331 5286>, + <7862 7038 6346 5623 5340 5292>, + <7862 7038 6346 5623 5340 5292>, + <7862 7038 6346 5623 5340 5292>; + }; + + qcom,pc-temp-y2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <9686 10401 10680 11050 11104 11401>, + <9784 10367 10651 11029 11106 11345>, + <9844 10346 10618 11003 11105 11260>, + <9875 10335 10585 10974 11102 11170>, + <9887 10331 10557 10941 11096 11098>, + <9890 10330 10539 10906 11089 11068>, + <9836 10343 10530 10861 11080 11075>, + <9739 10365 10523 10815 11067 11086>, + <9714 10360 10518 10793 11048 11085>, + <9726 10302 10514 10780 11017 11066>, + <9749 10260 10512 10771 10981 11044>, + <9880 10338 10522 10756 10934 11003>, + <10116 10474 10547 10736 10885 10947>, + <10170 10505 10586 10738 10874 10940>, + <9944 10486 10664 10781 10896 10992>, + <9729 10473 10720 10835 10928 11033>, + <9701 10495 10746 10897 10988 11035>, + <9694 10532 10766 10960 11059 11032>, + <9688 10541 10781 10991 11079 11043>, + <9682 10540 10795 11004 11080 11097>, + <9677 10537 10806 11018 11082 11163>, + <9674 10483 10815 11049 11128 11225>, + <9672 10313 10824 11092 11200 11283>, + <9670 10193 10827 11124 11234 11325>, + <9667 10079 10832 11151 11254 11356>, + <9664 10012 10836 11169 11271 11377>, + <9663 9998 10834 11180 11289 11395>, + <9662 9984 10826 11184 11309 11414>, + <9661 9965 10822 11175 11317 11445>, + <9660 9940 10820 11150 11329 11500>, + <9659 9913 10815 11136 11341 11537>, + <9659 9889 10729 11139 11328 11522>, + <9658 9867 10574 11151 11311 11482>, + <9657 9842 10507 11164 11315 11466>, + <9656 9813 10490 11161 11321 11473>, + <9656 9786 10478 11140 11317 11478>, + <9655 9762 10470 11112 11316 11484>, + <9655 9732 10507 11097 11321 11496>, + <9654 9708 10556 11103 11323 11495>, + <9654 9694 10525 11104 11318 11473>, + <9654 9684 10426 11103 11314 11461>, + <9654 9675 10396 11106 11316 11468>, + <9654 9668 10406 11101 11314 11471>, + <9653 9662 10267 11078 11283 11464>, + <9653 9659 10199 11060 11283 11440>, + <9653 9659 10180 11025 11296 11394>, + <9653 9658 10256 11021 11274 11345>, + <9653 9657 10321 11043 11240 11336>, + <9653 9656 10323 11048 11247 11344>, + <9652 9656 10295 10982 11294 11322>, + <9652 9654 10240 10956 11255 11261>, + <9652 9653 10172 10913 11134 11175>, + <9652 9652 10118 10825 11023 11061>, + <9650 9652 10099 10780 10831 10826>, + <9650 9652 10099 10780 10831 10826>, + <9650 9652 10099 10780 10831 10826>; + }; + + qcom,pc-temp-y3-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <13434 13398 13345 13285 13280 13272>, + <13675 13407 13338 13284 13280 13274>, + <13823 13420 13334 13283 13280 13275>, + <13901 13433 13334 13283 13280 13277>, + <13931 13444 13336 13283 13280 13278>, + <13936 13449 13340 13285 13280 13278>, + <13804 13449 13347 13288 13280 13278>, + <13564 13448 13355 13293 13281 13278>, + <13499 13451 13358 13295 13281 13278>, + <13498 13470 13359 13296 13281 13277>, + <13499 13484 13360 13296 13281 13277>, + <13523 13470 13373 13303 13284 13279>, + <13572 13441 13392 13313 13289 13282>, + <13584 13425 13393 13314 13290 13283>, + <13548 13416 13371 13310 13288 13282>, + <13516 13410 13351 13307 13286 13282>, + <13520 13407 13346 13309 13288 13282>, + <13536 13405 13343 13313 13292 13283>, + <13543 13402 13339 13313 13292 13283>, + <13545 13397 13334 13305 13287 13280>, + <13546 13391 13329 13296 13283 13277>, + <13548 13381 13324 13288 13281 13276>, + <13552 13365 13319 13283 13280 13275>, + <13557 13351 13318 13282 13279 13275>, + <13568 13340 13317 13283 13278 13275>, + <13586 13335 13317 13284 13278 13274>, + <13605 13336 13317 13283 13278 13274>, + <13625 13339 13317 13283 13277 13274>, + <13647 13343 13317 13285 13277 13274>, + <13675 13347 13317 13289 13277 13273>, + <13709 13352 13317 13292 13277 13273>, + <13746 13357 13312 13293 13278 13273>, + <13786 13364 13305 13292 13278 13274>, + <13834 13372 13302 13292 13279 13274>, + <13889 13385 13303 13290 13278 13274>, + <13952 13400 13304 13288 13278 13273>, + <14017 13416 13307 13286 13278 13273>, + <14082 13434 13314 13284 13277 13273>, + <14146 13456 13320 13283 13277 13273>, + <14209 13488 13324 13283 13277 13273>, + <14273 13532 13327 13283 13277 13273>, + <14339 13585 13333 13283 13278 13274>, + <14405 13648 13342 13283 13278 13274>, + <14482 13731 13345 13284 13278 13274>, + <14570 13843 13353 13283 13278 13274>, + <14605 13890 13360 13291 13279 13276>, + <14655 13886 13365 13292 13281 13277>, + <14684 13912 13378 13296 13283 13280>, + <14733 14009 13393 13298 13282 13280>, + <14859 14104 13394 13294 13281 13277>, + <14999 14246 13402 13296 13280 13277>, + <15153 14472 13423 13301 13283 13281>, + <15376 14712 13458 13305 13286 13284>, + <16172 14971 13514 13315 13290 13286>, + <16172 14971 13514 13315 13290 13286>, + <16172 14971 13514 13315 13290 13286>; + }; + + qcom,pc-temp-y4-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <17845 16850 16626 16493 16453 16452>, + <17707 16859 16623 16499 16453 16450>, + <17643 16875 16623 16504 16455 16449>, + <17641 16896 16626 16507 16456 16448>, + <17685 16923 16631 16509 16458 16448>, + <17761 16953 16638 16510 16459 16448>, + <17959 16995 16646 16508 16461 16449>, + <18315 17038 16657 16506 16462 16452>, + <18708 17060 16668 16506 16465 16454>, + <19236 17069 16679 16513 16469 16457>, + <19572 17084 16696 16524 16475 16461>, + <19006 17415 16799 16542 16489 16473>, + <17760 17958 16951 16564 16509 16488>, + <17274 17986 16977 16573 16513 16492>, + <17223 17320 16899 16575 16509 16491>, + <17197 16817 16810 16579 16507 16490>, + <17184 16821 16750 16620 16529 16506>, + <17165 16866 16699 16681 16570 16536>, + <17135 16877 16663 16682 16576 16541>, + <17076 16837 16634 16593 16532 16509>, + <17012 16792 16611 16517 16486 16475>, + <16969 16768 16596 16504 16468 16461>, + <16936 16750 16584 16498 16457 16451>, + <16927 16747 16578 16495 16456 16450>, + <16931 16735 16574 16491 16456 16450>, + <16939 16719 16571 16489 16457 16451>, + <16945 16707 16570 16491 16459 16453>, + <16955 16695 16570 16493 16462 16456>, + <16966 16694 16569 16494 16465 16460>, + <16978 16706 16564 16496 16471 16465>, + <16990 16724 16560 16498 16478 16472>, + <17002 16743 16564 16500 16488 16483>, + <17014 16767 16573 16502 16499 16496>, + <17027 16792 16580 16500 16501 16498>, + <17040 16818 16585 16489 16484 16481>, + <17052 16845 16589 16478 16463 16460>, + <17064 16879 16594 16475 16452 16451>, + <17077 16927 16600 16473 16446 16447>, + <17095 16964 16604 16474 16446 16448>, + <17121 16978 16617 16477 16450 16453>, + <17160 16988 16637 16480 16455 16458>, + <17211 16994 16652 16483 16456 16459>, + <17278 17008 16664 16484 16454 16456>, + <17363 17031 16681 16481 16445 16443>, + <17450 17090 16711 16491 16449 16446>, + <17435 17135 16736 16501 16471 16474>, + <17438 17159 16742 16516 16496 16504>, + <17389 17194 16787 16546 16537 16546>, + <17360 17262 16870 16574 16540 16536>, + <17381 17283 16862 16542 16494 16484>, + <17398 17284 16856 16542 16480 16473>, + <17425 17312 16891 16573 16496 16487>, + <17507 17393 16998 16635 16528 16517>, + <18186 17570 17197 16862 16705 16664>, + <18186 17570 17197 16862 16705 16664>, + <18186 17570 17197 16862 16705 16664>; + }; + + qcom,pc-temp-y5-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <8712 13450 15024 13637 17779 13876>, + <8712 13482 14393 13094 17299 16002>, + <9887 13538 13920 12763 16795 17370>, + <12171 13602 13593 12592 16319 18144>, + <13352 13655 13402 12528 15924 18488>, + <13712 13682 13338 12519 15663 18564>, + <12526 13686 13491 13011 15524 18119>, + <10345 13688 13732 13797 15423 17285>, + <9855 13494 13762 13896 15233 16665>, + <10836 12338 13637 13520 14742 16018>, + <12278 11512 13460 13263 14463 15589>, + <14305 12246 13117 13605 14692 15613>, + <16658 13838 12700 14184 15051 15805>, + <17024 14948 12908 14300 15117 15807>, + <14139 15828 14686 14149 14970 15538>, + <11513 16242 16074 14033 14913 15280>, + <11523 16069 16259 14411 15080 15197>, + <11996 15810 16323 15261 15416 15147>, + <12172 15770 16274 15815 15959 15251>, + <12062 15859 16079 16180 16933 16031>, + <11868 15956 15846 16328 17499 16947>, + <11620 15469 15368 15383 17703 17632>, + <11312 13975 14705 13688 17924 18203>, + <11115 12872 14496 13266 17959 18431>, + <11014 12058 14552 13626 17682 18509>, + <10964 11631 14629 13920 17362 18511>, + <10973 11596 14709 13944 17173 18320>, + <10988 11605 14796 13932 17044 17852>, + <10995 11588 14900 14573 17019 17407>, + <11030 11538 15113 16622 17008 17007>, + <11086 11527 15270 18010 17024 16810>, + <11136 11527 14539 18405 17391 17083>, + <11177 11500 13186 18651 18220 17910>, + <11216 11497 12702 18616 19096 18783>, + <11256 11585 12708 17851 20108 19561>, + <11296 11690 12725 16773 20954 20137>, + <11333 11737 12833 15892 21243 20622>, + <11364 11658 13487 15086 21079 21066>, + <11372 11570 14099 14616 20668 21138>, + <11354 11602 14046 14527 20112 20711>, + <11333 11673 13559 14611 19900 20367>, + <11347 11689 13647 14598 20136 20790>, + <11447 11633 14091 14488 20830 22215>, + <11628 11564 13261 14690 21851 23634>, + <11886 11464 12890 13840 19650 20132>, + <12228 11536 12810 15945 17300 17267>, + <12464 11547 13361 15880 17100 16566>, + <12844 11910 14094 16530 16574 16161>, + <12886 12441 14613 16353 15911 15963>, + <12844 12583 14513 15967 17037 16654>, + <12567 12345 14561 17027 17428 17457>, + <12151 12056 14328 17704 18241 18950>, + <11887 11870 14282 17302 18299 19121>, + <11109 11677 14642 17219 17830 18283>, + <11109 11677 14642 17219 17830 18283>, + <11109 11677 14642 17219 17830 18283>; + }; + + qcom,pc-temp-y6-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <6900 5639 5266 5065 5021 5010>, + <6907 5646 5261 5064 5021 5011>, + <6911 5654 5258 5063 5021 5012>, + <6911 5662 5258 5064 5021 5013>, + <6908 5670 5260 5065 5022 5013>, + <6903 5678 5262 5066 5023 5014>, + <6855 5686 5268 5068 5023 5015>, + <6776 5694 5276 5071 5025 5015>, + <6772 5702 5281 5074 5026 5016>, + <6911 5708 5283 5076 5027 5017>, + <7024 5719 5288 5079 5029 5018>, + <6900 5804 5324 5090 5036 5023>, + <6611 5932 5379 5103 5045 5030>, + <6465 5932 5387 5106 5047 5032>, + <6414 5744 5349 5105 5045 5031>, + <6390 5602 5310 5104 5043 5031>, + <6395 5604 5291 5117 5051 5036>, + <6409 5621 5276 5138 5065 5045>, + <6413 5625 5263 5138 5067 5047>, + <6412 5613 5251 5107 5051 5035>, + <6410 5600 5242 5078 5035 5023>, + <6413 5590 5235 5069 5028 5018>, + <6426 5582 5230 5064 5025 5015>, + <6444 5577 5229 5063 5024 5015>, + <6469 5575 5230 5063 5024 5015>, + <6500 5574 5231 5064 5024 5016>, + <6530 5579 5232 5065 5025 5016>, + <6560 5589 5235 5066 5026 5017>, + <6592 5602 5237 5068 5027 5018>, + <6630 5619 5238 5072 5029 5020>, + <6673 5639 5239 5076 5031 5022>, + <6719 5661 5240 5078 5035 5026>, + <6770 5688 5241 5079 5039 5030>, + <6823 5717 5243 5078 5040 5031>, + <6880 5750 5247 5074 5035 5026>, + <6940 5787 5251 5070 5029 5020>, + <7001 5830 5256 5068 5026 5018>, + <7062 5880 5264 5067 5024 5016>, + <7124 5938 5274 5066 5024 5017>, + <7187 6002 5285 5067 5025 5018>, + <7249 6076 5296 5069 5027 5020>, + <7312 6161 5311 5070 5028 5021>, + <7379 6261 5328 5071 5027 5020>, + <7458 6383 5344 5072 5025 5017>, + <7552 6532 5369 5074 5027 5018>, + <7589 6585 5388 5083 5033 5027>, + <7631 6596 5395 5089 5042 5037>, + <7646 6631 5423 5100 5055 5051>, + <7684 6743 5466 5110 5056 5048>, + <7789 6847 5472 5099 5042 5031>, + <7903 6977 5491 5102 5038 5029>, + <8038 7181 5547 5117 5046 5036>, + <8244 7391 5646 5141 5058 5047>, + <9160 7653 5795 5217 5112 5092>, + <9160 7653 5795 5217 5112 5092>, + <9160 7653 5795 5217 5112 5092>; + }; +}; diff --git a/qcom/qg-batterydata-atl466271_3300mAh.dtsi b/qcom/qg-batterydata-atl466271_3300mAh.dtsi new file mode 100644 index 00000000..456c17bc --- /dev/null +++ b/qcom/qg-batterydata-atl466271_3300mAh.dtsi @@ -0,0 +1,1041 @@ +qcom,ATL466271_3300mAh { + /* ATL466271_3300mAh_averaged_MasterSlave_Jun12th2019 */ + qcom,max-voltage-uv = <4400000>; + qcom,fg-cc-cv-threshold-uv = <4390000>; + qcom,fastchg-current-ma = <8000>; + qcom,batt-id-kohm = <24>; + qcom,battery-beta = <4250>; + qcom,battery-therm-kohm = <100>; + qcom,battery-type = + "ATL466271_3300mAh_averaged_MasterSlave_Jun12th2019"; + qcom,qg-batt-profile-ver = <100>; + + qcom,jeita-fcc-ranges = <0 100 1600000 + 101 200 3200000 + 201 450 8000000 + 451 550 1600000>; + + qcom,jeita-fv-ranges = <0 100 4400000 + 101 200 4400000 + 201 450 4400000 + 451 550 4050000>; + + qcom,step-chg-ranges = <3500000 4000000 8000000 + 4000001 4200000 6000000 + 4200001 4400000 4000000>; + qcom,ocv-based-step-chg; + + /* COOL = 10 degc, WARM = 45 degC */ + qcom,jeita-soft-thresholds = <0x4ccc 0x20b8>; + /* COLD = 0 degC, HOT = 55 degC*/ + qcom,jeita-hard-thresholds = <0x58cd 0x181d>; + /* COOL hys = 13 degC, WARM hys = 42 degC */ + qcom,jeita-soft-hys-thresholds = <0x48d4 0x23c0>; + qcom,jeita-soft-fcc-ua = <1600000 1600000>; + qcom,jeita-soft-fv-uv = <4400000 4050000>; + + qcom,fcc1-temp-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-data = <3191 3260 3320 3354 3366>; + }; + + qcom,fcc2-temp-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-data = <3307 3309 3324 3332 3330 3326>; + }; + + qcom,pc-temp-v1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <43710 43825 43909 43937 43942>, + <43473 43605 43706 43721 43723>, + <43237 43380 43489 43509 43510>, + <43003 43150 43267 43294 43299>, + <42775 42918 43038 43070 43079>, + <42550 42687 42804 42837 42850>, + <42328 42457 42573 42606 42620>, + <42109 42230 42341 42375 42390>, + <41894 42008 42113 42145 42161>, + <41684 41789 41886 41917 41933>, + <41476 41574 41663 41690 41705>, + <41278 41360 41446 41467 41481>, + <41103 41159 41232 41247 41261>, + <40943 40987 41027 41035 41047>, + <40756 40823 40831 40833 40840>, + <40499 40625 40638 40639 40642>, + <40235 40371 40434 40442 40448>, + <40047 40136 40224 40241 40259>, + <39905 39978 40039 40053 40076>, + <39770 39845 39893 39894 39909>, + <39637 39668 39742 39742 39748>, + <39498 39402 39527 39546 39554>, + <39319 39159 39260 39286 39299>, + <39057 39018 39056 39062 39070>, + <38841 38914 38916 38909 38913>, + <38748 38814 38798 38783 38786>, + <38688 38714 38686 38668 38667>, + <38628 38621 38584 38566 38559>, + <38566 38536 38491 38471 38460>, + <38504 38459 38406 38380 38367>, + <38445 38391 38330 38297 38282>, + <38388 38330 38261 38223 38205>, + <38337 38276 38199 38156 38134>, + <38292 38228 38143 38095 38068>, + <38251 38187 38095 38043 38009>, + <38214 38146 38049 37992 37951>, + <38182 38111 38004 37933 37881>, + <38143 38071 37958 37869 37800>, + <38074 38006 37895 37793 37711>, + <37974 37903 37802 37697 37614>, + <37864 37788 37692 37587 37506>, + <37736 37663 37571 37457 37376>, + <37592 37522 37433 37310 37228>, + <37427 37351 37270 37152 37071>, + <37293 37218 37135 37037 36964>, + <37218 37148 37061 36976 36918>, + <37197 37127 37043 36958 36899>, + <37176 37114 37027 36945 36884>, + <37152 37086 37005 36915 36845>, + <37053 36954 36879 36723 36623>, + <36674 36578 36526 36347 36242>, + <36195 36086 36041 35859 35751>, + <35574 35449 35427 35229 35116>, + <34729 34574 34574 34362 34242>, + <33401 33172 33225 32989 32851>, + <30000 30000 30000 30000 30000>; + }; + + qcom,pc-temp-v2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <43975 43950 43930 43905 43855 43835>, + <43614 43647 43667 43663 43617 43596>, + <43279 43361 43410 43424 43383 43362>, + <42972 43092 43162 43188 43150 43130>, + <42688 42841 42921 42956 42921 42903>, + <42432 42596 42682 42724 42691 42675>, + <42220 42350 42446 42490 42458 42443>, + <42020 42110 42212 42257 42225 42210>, + <41772 41881 41982 42027 41995 41980>, + <41458 41662 41755 41799 41766 41751>, + <41235 41448 41531 41574 41541 41526>, + <41153 41235 41310 41352 41318 41305>, + <41088 41026 41094 41134 41100 41087>, + <40904 40832 40899 40930 40893 40877>, + <40447 40653 40720 40736 40694 40672>, + <40034 40458 40525 40537 40495 40472>, + <39788 40221 40292 40319 40288 40277>, + <39585 39967 40050 40106 40087 40088>, + <39406 39734 39841 39926 39912 39913>, + <39248 39515 39652 39767 39754 39750>, + <39074 39305 39456 39583 39572 39566>, + <38832 39100 39232 39336 39328 39323>, + <38584 38908 39017 39089 39082 39080>, + <38426 38747 38845 38906 38903 38901>, + <38310 38609 38699 38752 38755 38754>, + <38226 38477 38570 38621 38627 38625>, + <38164 38335 38453 38506 38513 38511>, + <38113 38204 38348 38403 38410 38407>, + <38062 38112 38253 38308 38314 38311>, + <38014 38043 38166 38221 38224 38220>, + <37968 37988 38082 38140 38142 38137>, + <37925 37942 37996 38064 38067 38062>, + <37882 37901 37921 37993 37995 37989>, + <37836 37861 37870 37925 37926 37914>, + <37789 37823 37831 37859 37858 37837>, + <37739 37781 37790 37789 37775 37745>, + <37688 37735 37747 37715 37668 37625>, + <37631 37682 37698 37637 37559 37505>, + <37562 37619 37632 37559 37469 37410>, + <37480 37542 37547 37477 37386 37325>, + <37385 37449 37447 37382 37290 37228>, + <37268 37321 37322 37269 37178 37113>, + <37144 37177 37181 37135 37045 36979>, + <37027 37026 37025 36987 36895 36830>, + <36932 36918 36939 36908 36841 36784>, + <36855 36857 36899 36885 36818 36762>, + <36812 36827 36875 36867 36801 36749>, + <36761 36786 36846 36843 36779 36722>, + <36679 36721 36775 36779 36692 36597>, + <36475 36551 36546 36552 36390 36264>, + <36066 36173 36127 36133 35937 35797>, + <35499 35647 35579 35596 35370 35211>, + <34766 34968 34863 34909 34633 34453>, + <33784 34024 33935 33996 33658 33408>, + <32412 32711 32567 32650 31840 31311>, + <28215 28831 27522 28579 27814 27518>; + }; + + qcom,pc-temp-z1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <11770 11167 10508 10200 10123>, + <11802 11193 10579 10273 10190>, + <11806 11200 10581 10275 10191>, + <11805 11183 10570 10275 10191>, + <11792 11170 10557 10270 10189>, + <11777 11154 10545 10264 10185>, + <11765 11131 10537 10259 10182>, + <11755 11116 10530 10255 10180>, + <11743 11111 10524 10251 10178>, + <11735 11108 10520 10250 10177>, + <11730 11108 10517 10249 10175>, + <11726 11108 10514 10248 10174>, + <11721 11108 10512 10248 10173>, + <11717 11105 10511 10247 10173>, + <11714 11099 10510 10247 10172>, + <11704 11097 10508 10245 10172>, + <11693 11095 10507 10245 10172>, + <11693 11095 10506 10245 10172>, + <11704 11097 10506 10246 10174>, + <11714 11101 10509 10248 10175>, + <11726 11106 10513 10252 10177>, + <11741 11114 10517 10254 10179>, + <11744 11122 10522 10256 10181>, + <11737 11128 10527 10258 10183>, + <11732 11133 10532 10260 10185>, + <11733 11134 10537 10264 10187>, + <11737 11132 10542 10267 10190>, + <11740 11131 10548 10272 10194>, + <11743 11133 10553 10276 10197>, + <11747 11137 10558 10280 10200>, + <11750 11142 10564 10285 10203>, + <11754 11154 10571 10288 10206>, + <11758 11165 10579 10292 10209>, + <11769 11165 10584 10296 10213>, + <11781 11161 10589 10301 10217>, + <11789 11159 10594 10306 10221>, + <11796 11169 10600 10312 10225>, + <11803 11182 10606 10317 10229>, + <11809 11185 10612 10322 10233>, + <11816 11186 10619 10326 10236>, + <11819 11188 10625 10330 10239>, + <11821 11199 10630 10335 10243>, + <11823 11208 10636 10340 10246>, + <11826 11206 10642 10342 10248>, + <11820 11215 10648 10344 10249>, + <11820 11220 10655 10347 10250>, + <11830 11225 10660 10348 10252>, + <11816 11232 10658 10350 10253>, + <11831 11224 10662 10354 10257>, + <11856 11221 10671 10358 10261>, + <11833 11233 10673 10362 10265>, + <11848 11251 10678 10368 10270>, + <11885 11257 10688 10374 10275>, + <11898 11288 10702 10382 10282>, + <11898 11288 10702 10382 10282>, + <11898 11288 10702 10382 10282>; + }; + + qcom,pc-temp-z2-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <9894 9757 10034 10106 10345>, + <9913 9932 10014 10164 10226>, + <9939 10003 10052 10124 10214>, + <9961 9993 10069 10079 10205>, + <9956 9975 10063 10081 10205>, + <9932 9968 10050 10100 10208>, + <9909 9964 10028 10116 10214>, + <9894 9962 9988 10127 10224>, + <9882 9965 9971 10137 10239>, + <9879 9971 9979 10146 10256>, + <9887 9975 9990 10155 10278>, + <9899 9978 9996 10160 10293>, + <9908 9983 10003 10160 10302>, + <9915 10111 10010 10159 10307>, + <9923 10305 10017 10164 10303>, + <9937 10319 10021 10171 10296>, + <9949 10152 10020 10170 10294>, + <9950 10028 10015 10163 10294>, + <9944 10019 10013 10158 10295>, + <9940 10013 10022 10178 10307>, + <9940 10015 10039 10212 10331>, + <9943 10049 10081 10217 10334>, + <9948 10079 10155 10205 10297>, + <9962 10074 10180 10185 10246>, + <9973 10059 10141 10123 10180>, + <9974 10052 10094 10050 10113>, + <9972 10052 10070 10041 10102>, + <9972 10053 10053 10046 10113>, + <9973 10046 10049 10054 10127>, + <9975 10033 10060 10064 10141>, + <9976 10029 10075 10077 10158>, + <9978 10038 10091 10098 10180>, + <9980 10052 10108 10129 10208>, + <9983 10064 10127 10163 10243>, + <9988 10077 10148 10206 10293>, + <9992 10087 10168 10244 10345>, + <9997 10095 10183 10263 10380>, + <10003 10102 10195 10276 10409>, + <10012 10114 10208 10287 10417>, + <10023 10130 10226 10298 10403>, + <10024 10137 10237 10306 10390>, + <10014 10120 10220 10308 10389>, + <10008 10106 10192 10307 10384>, + <10006 10106 10186 10298 10361>, + <10058 10124 10199 10299 10329>, + <10061 10124 10204 10309 10360>, + <10054 10113 10214 10301 10359>, + <10052 10093 10207 10352 10392>, + <10039 10104 10227 10397 10452>, + <9972 10155 10228 10268 10254>, + <10081 10129 10171 10193 10218>, + <10034 10095 10128 10161 10175>, + <9993 10043 10103 10128 10146>, + <9836 9993 10057 10083 10063>, + <9836 9993 10057 10083 10063>, + <9836 9993 10057 10083 10063>; + }; + + qcom,pc-temp-z3-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <19500 19444 19370 19351 19313>, + <19626 19520 19402 19353 19340>, + <19677 19560 19426 19362 19348>, + <19706 19570 19435 19369 19353>, + <19708 19575 19432 19369 19353>, + <19704 19574 19427 19367 19351>, + <19701 19566 19421 19364 19348>, + <19699 19557 19414 19360 19345>, + <19697 19549 19409 19355 19341>, + <19692 19541 19406 19353 19340>, + <19680 19535 19404 19352 19339>, + <19665 19529 19401 19351 19338>, + <19649 19525 19397 19351 19337>, + <19632 19526 19395 19351 19336>, + <19625 19529 19394 19350 19335>, + <19632 19529 19394 19349 19331>, + <19639 19523 19394 19348 19329>, + <19638 19517 19394 19347 19327>, + <19628 19510 19394 19345 19325>, + <19621 19502 19390 19341 19323>, + <19618 19501 19385 19335 19320>, + <19616 19515 19389 19337 19322>, + <19618 19527 19402 19355 19339>, + <19632 19520 19415 19369 19354>, + <19643 19503 19428 19376 19357>, + <19638 19499 19437 19380 19359>, + <19626 19519 19437 19380 19359>, + <19619 19539 19434 19373 19356>, + <19618 19539 19430 19368 19353>, + <19618 19535 19425 19366 19350>, + <19619 19530 19418 19364 19347>, + <19621 19524 19413 19362 19343>, + <19622 19517 19409 19358 19340>, + <19621 19512 19405 19354 19336>, + <19618 19508 19401 19349 19331>, + <19615 19505 19398 19346 19328>, + <19611 19503 19397 19346 19330>, + <19607 19500 19396 19347 19336>, + <19603 19497 19395 19348 19339>, + <19597 19494 19393 19350 19339>, + <19593 19490 19390 19351 19339>, + <19592 19487 19386 19352 19339>, + <19588 19483 19383 19353 19339>, + <19579 19481 19385 19354 19341>, + <19543 19466 19382 19350 19341>, + <19529 19450 19368 19337 19321>, + <19525 19448 19365 19331 19318>, + <19523 19438 19363 19324 19312>, + <19489 19434 19359 19320 19312>, + <19401 19438 19363 19342 19330>, + <19514 19442 19376 19345 19331>, + <19508 19444 19378 19345 19332>, + <19506 19447 19381 19346 19334>, + <19479 19451 19379 19353 19342>, + <19479 19451 19379 19353 19342>, + <19479 19451 19379 19353 19342>; + }; + + qcom,pc-temp-z4-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <15847 15406 14998 14784 14808>, + <15949 15355 15044 14878 14825>, + <15794 15280 14959 14838 14798>, + <15524 15160 14880 14782 14745>, + <15335 15024 14821 14755 14725>, + <15199 14932 14776 14735 14717>, + <15092 14862 14760 14724 14712>, + <15007 14818 14752 14719 14708>, + <14938 14795 14745 14715 14704>, + <14892 14781 14736 14710 14700>, + <14861 14774 14728 14704 14696>, + <14839 14771 14722 14699 14691>, + <14823 14768 14716 14693 14687>, + <14809 14746 14714 14688 14682>, + <14805 14717 14714 14683 14677>, + <14837 14717 14714 14679 14672>, + <14877 14763 14713 14676 14669>, + <14877 14798 14707 14672 14666>, + <14845 14782 14700 14669 14663>, + <14819 14748 14691 14667 14660>, + <14809 14748 14684 14665 14657>, + <14802 14849 14717 14676 14662>, + <14817 14940 14810 14736 14713>, + <14926 14941 14844 14773 14752>, + <15018 14932 14810 14755 14738>, + <15011 14916 14769 14725 14711>, + <14979 14870 14751 14712 14699>, + <14949 14826 14739 14706 14693>, + <14922 14811 14733 14701 14688>, + <14898 14803 14730 14696 14684>, + <14881 14800 14728 14693 14681>, + <14867 14800 14728 14691 14678>, + <14859 14800 14727 14689 14675>, + <14855 14800 14728 14689 14674>, + <14853 14801 14730 14689 14673>, + <14850 14801 14732 14690 14672>, + <14845 14800 14733 14694 14676>, + <14843 14799 14734 14701 14687>, + <14846 14800 14735 14703 14692>, + <14851 14805 14736 14701 14691>, + <14852 14807 14737 14699 14691>, + <14843 14799 14733 14696 14691>, + <14831 14786 14724 14692 14690>, + <14819 14776 14719 14690 14690>, + <14767 14740 14703 14678 14676>, + <14740 14710 14680 14653 14645>, + <14731 14703 14668 14647 14637>, + <14725 14696 14656 14637 14627>, + <14741 14692 14651 14632 14622>, + <14832 14699 14662 14641 14641>, + <14739 14707 14661 14645 14646>, + <14748 14705 14661 14648 14648>, + <14752 14704 14661 14650 14649>, + <14789 14699 14665 14647 14645>, + <14789 14699 14665 14647 14645>, + <14789 14699 14665 14647 14645>; + }; + + qcom,pc-temp-z5-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <11792 12279 13535 15414 14204>, + <13001 13808 15235 16383 17416>, + <13841 15100 16456 17237 19077>, + <14514 16104 17533 18315 20517>, + <15113 17028 18754 19244 21245>, + <15689 18181 19650 20146 21743>, + <16375 19593 19683 20412 21915>, + <17353 20752 19475 20064 21544>, + <18570 21607 19385 19726 21069>, + <19714 22312 19837 19833 21119>, + <20922 22624 20368 20227 21592>, + <21654 22649 20366 20704 22135>, + <21494 22792 20190 21409 22819>, + <21073 24392 20127 22129 23478>, + <21017 26764 20584 22757 23767>, + <22555 26941 21094 23386 23725>, + <24349 24455 21214 23801 23655>, + <24216 22548 21439 24313 23878>, + <22900 22853 21828 24599 24211>, + <22166 23930 23250 24474 24553>, + <23067 25813 24579 24129 24960>, + <25218 31144 24161 23371 24839>, + <27733 35337 22682 21648 23111>, + <31628 31478 21716 20674 21705>, + <34089 22242 21182 20941 21493>, + <31865 19114 20879 21395 21408>, + <26536 20884 21549 21643 21618>, + <23985 23280 23503 21875 22646>, + <23503 25063 24966 22255 23786>, + <23364 26728 25863 23569 24665>, + <23874 27767 26627 25316 25537>, + <25339 28404 27366 26549 26565>, + <26580 28812 28051 27647 27783>, + <27299 28952 28637 28369 28438>, + <27859 29013 29244 28922 28605>, + <28127 28980 29596 29269 28749>, + <28121 28632 29354 28928 29008>, + <28035 28071 28613 27970 29397>, + <28032 27480 27672 27629 29838>, + <28024 26731 26146 27677 30769>, + <27889 25936 24626 27779 31609>, + <27436 24934 23369 28434 31801>, + <26929 24388 22499 29368 31887>, + <26421 24450 22608 28936 31937>, + <27988 25663 22852 26365 31185>, + <27430 25453 21972 22626 21099>, + <26554 25602 22352 22600 22211>, + <26806 23914 24361 22775 24450>, + <23478 23641 24736 23227 28936>, + <18946 23905 22228 28971 29716>, + <23561 21707 23990 27451 26335>, + <20333 21474 23601 25150 24619>, + <18967 20996 23606 23367 22997>, + <16796 21104 21653 24495 23716>, + <16796 21104 21653 24495 23716>, + <16796 21104 21653 24495 23716>; + }; + + qcom,pc-temp-z6-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <15776 15081 14574 14403 14378>, + <15822 15066 14611 14457 14412>, + <15728 15042 14587 14444 14404>, + <15561 14985 14560 14425 14386>, + <15434 14901 14531 14412 14376>, + <15332 14840 14504 14402 14371>, + <15250 14790 14491 14394 14367>, + <15184 14755 14482 14389 14362>, + <15130 14736 14475 14384 14359>, + <15088 14723 14469 14380 14356>, + <15057 14715 14464 14377 14353>, + <15033 14710 14459 14374 14350>, + <15014 14704 14454 14371 14348>, + <14997 14693 14451 14368 14345>, + <14991 14680 14450 14366 14342>, + <15002 14679 14449 14363 14338>, + <15017 14691 14448 14361 14335>, + <15016 14701 14446 14359 14333>, + <14999 14693 14443 14357 14331>, + <14987 14676 14438 14354 14328>, + <14985 14676 14433 14350 14326>, + <14985 14729 14451 14357 14329>, + <14996 14777 14500 14394 14362>, + <15054 14775 14519 14417 14387>, + <15101 14767 14512 14412 14383>, + <15097 14759 14503 14404 14374>, + <15080 14752 14497 14398 14368>, + <15067 14746 14492 14393 14365>, + <15057 14742 14488 14389 14362>, + <15050 14739 14484 14386 14358>, + <15047 14737 14482 14384 14356>, + <15045 14735 14480 14382 14353>, + <15045 14734 14478 14379 14350>, + <15046 14734 14478 14378 14347>, + <15047 14735 14478 14376 14345>, + <15049 14736 14479 14375 14343>, + <15050 14738 14480 14377 14345>, + <15052 14740 14481 14381 14354>, + <15055 14743 14482 14384 14358>, + <15061 14747 14484 14384 14358>, + <15065 14749 14485 14385 14359>, + <15066 14747 14482 14385 14359>, + <15067 14746 14478 14385 14360>, + <15067 14745 14478 14385 14361>, + <15047 14732 14473 14378 14356>, + <15035 14716 14457 14362 14333>, + <15030 14712 14451 14356 14327>, + <15027 14706 14445 14348 14320>, + <15020 14704 14442 14344 14318>, + <15023 14714 14450 14360 14336>, + <15046 14724 14459 14366 14341>, + <15055 14730 14462 14368 14344>, + <15068 14739 14467 14371 14347>, + <15088 14751 14472 14376 14351>, + <15088 14751 14472 14376 14351>, + <15088 14751 14472 14376 14351>; + }; + + qcom,pc-temp-y1-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <5821 5347 5037 4674 4481 4427>, + <5843 5351 5036 4672 4484 4429>, + <5865 5355 5035 4670 4485 4430>, + <5883 5361 5033 4667 4485 4430>, + <5897 5365 5031 4664 4484 4431>, + <5903 5367 5030 4660 4482 4431>, + <5900 5367 5025 4656 4477 4430>, + <5895 5365 5019 4650 4473 4429>, + <5896 5364 5014 4646 4472 4427>, + <5901 5359 5010 4643 4472 4425>, + <5903 5356 5008 4640 4472 4423>, + <5904 5358 5011 4637 4470 4422>, + <5908 5361 5015 4634 4468 4422>, + <5911 5361 5013 4632 4467 4421>, + <5920 5359 5004 4630 4465 4419>, + <5925 5358 5000 4629 4464 4419>, + <5922 5365 5003 4629 4464 4419>, + <5917 5374 5007 4629 4464 4419>, + <5917 5376 5008 4629 4464 4419>, + <5916 5373 5005 4630 4465 4419>, + <5914 5372 5003 4631 4465 4419>, + <5914 5377 5004 4633 4467 4420>, + <5916 5382 5005 4635 4469 4422>, + <5917 5383 5005 4638 4469 4422>, + <5917 5382 5006 4640 4469 4422>, + <5917 5382 5008 4643 4470 4423>, + <5915 5390 5013 4646 4472 4423>, + <5911 5400 5019 4650 4474 4424>, + <5907 5401 5024 4654 4476 4426>, + <5900 5398 5029 4659 4479 4428>, + <5896 5395 5032 4664 4481 4430>, + <5906 5395 5032 4669 4484 4431>, + <5922 5398 5032 4675 4487 4432>, + <5932 5401 5035 4679 4490 4434>, + <5943 5403 5043 4682 4493 4437>, + <5946 5405 5047 4686 4496 4440>, + <5933 5401 5047 4691 4499 4442>, + <5912 5395 5048 4695 4501 4444>, + <5901 5393 5053 4701 4504 4445>, + <5892 5393 5061 4707 4506 4446>, + <5887 5393 5065 4710 4509 4448>, + <5896 5394 5064 4713 4511 4451>, + <5900 5398 5066 4715 4513 4451>, + <5883 5418 5079 4717 4515 4451>, + <5915 5410 5075 4725 4518 4454>, + <5906 5399 5089 4726 4521 4456>, + <5899 5402 5088 4727 4519 4457>, + <5893 5400 5081 4734 4522 4457>, + <5894 5416 5082 4737 4521 4457>, + <5893 5422 5089 4735 4523 4458>, + <5951 5403 5099 4738 4525 4460>, + <5978 5411 5100 4752 4529 4462>, + <5943 5406 5107 4748 4534 4464>, + <5955 5420 5108 4757 4536 4469>, + <5955 5420 5108 4757 4536 4469>, + <5955 5420 5108 4757 4536 4469>; + }; + + qcom,pc-temp-y2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <10091 10247 10509 10767 10785 10927>, + <10085 10259 10500 10740 10807 10958>, + <10082 10274 10489 10711 10818 10974>, + <10082 10288 10479 10684 10821 10978>, + <10084 10301 10470 10661 10818 10974>, + <10088 10309 10463 10643 10813 10967>, + <10129 10314 10458 10630 10787 10948>, + <10196 10318 10454 10619 10754 10920>, + <10242 10317 10452 10606 10748 10891>, + <10309 10310 10448 10589 10749 10854>, + <10343 10306 10446 10578 10750 10833>, + <10348 10349 10451 10581 10744 10834>, + <10361 10433 10462 10588 10735 10837>, + <10354 10516 10482 10588 10734 10833>, + <10267 10617 10525 10585 10733 10822>, + <10196 10671 10577 10591 10733 10816>, + <9993 10677 10646 10622 10733 10824>, + <9724 10679 10709 10670 10734 10837>, + <9677 10682 10732 10741 10732 10847>, + <9671 10689 10745 10841 10729 10857>, + <9668 10692 10750 10877 10736 10873>, + <9666 10695 10747 10828 10833 10914>, + <9664 10701 10743 10775 10940 10965>, + <9663 10698 10754 10784 10956 10999>, + <9661 10676 10777 10824 10960 11030>, + <9660 10640 10792 10857 10965 11054>, + <9659 10551 10798 10880 10972 11078>, + <9658 10416 10805 10900 10980 11102>, + <9657 10287 10820 10916 10994 11121>, + <9656 10134 10847 10930 11021 11137>, + <9656 10010 10858 10948 11048 11156>, + <9655 9913 10844 10989 11077 11185>, + <9655 9833 10824 11022 11105 11210>, + <9654 9791 10807 11021 11137 11220>, + <9654 9761 10786 11011 11170 11226>, + <9654 9737 10768 11005 11177 11228>, + <9654 9716 10753 11011 11139 11200>, + <9654 9699 10737 11017 11102 11170>, + <9653 9689 10712 11012 11096 11161>, + <9653 9681 10675 10996 11093 11144>, + <9653 9675 10616 10980 11081 11118>, + <9653 9671 10491 10961 11032 11066>, + <9653 9667 10377 10936 11009 11056>, + <9653 9664 10284 10902 11002 11096>, + <9653 9661 10205 10867 11000 10997>, + <9652 9659 10189 10820 10935 10941>, + <9652 9659 10170 10842 10880 10907>, + <9652 9658 10266 10786 10907 10898>, + <9652 9657 10342 10819 10926 10908>, + <9652 9656 10250 10823 10875 10851>, + <9652 9655 10037 10750 10829 10802>, + <9652 9654 9972 10651 10750 10766>, + <9651 9653 9891 10735 10690 10675>, + <9650 9653 10171 10679 10569 10544>, + <9650 9653 10171 10679 10569 10544>, + <9650 9653 10171 10679 10569 10544>; + }; + + qcom,pc-temp-y3-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <14020 13485 13348 13290 13276 13269>, + <13912 13484 13350 13290 13276 13270>, + <13847 13482 13351 13290 13277 13271>, + <13814 13481 13352 13290 13277 13272>, + <13802 13479 13353 13290 13278 13274>, + <13800 13477 13353 13290 13278 13274>, + <13846 13474 13353 13290 13278 13275>, + <13915 13471 13353 13289 13279 13275>, + <13881 13472 13353 13290 13279 13275>, + <13646 13477 13352 13291 13279 13275>, + <13499 13480 13351 13292 13280 13275>, + <13535 13470 13351 13294 13280 13276>, + <13592 13454 13351 13296 13280 13277>, + <13605 13449 13352 13297 13281 13277>, + <13589 13442 13356 13297 13282 13277>, + <13574 13436 13358 13298 13282 13277>, + <13544 13434 13352 13298 13282 13277>, + <13507 13429 13343 13300 13283 13277>, + <13503 13421 13341 13301 13284 13278>, + <13510 13403 13340 13302 13285 13280>, + <13517 13385 13338 13303 13286 13281>, + <13521 13372 13331 13298 13282 13278>, + <13523 13361 13323 13291 13278 13275>, + <13523 13352 13319 13288 13277 13274>, + <13533 13345 13316 13286 13277 13273>, + <13553 13338 13314 13285 13276 13272>, + <13593 13320 13311 13285 13277 13273>, + <13646 13299 13309 13285 13277 13273>, + <13696 13288 13308 13285 13276 13273>, + <13750 13271 13307 13286 13276 13273>, + <13806 13266 13305 13286 13275 13273>, + <13866 13268 13303 13285 13275 13273>, + <13929 13271 13301 13285 13275 13272>, + <13994 13274 13301 13285 13275 13272>, + <14060 13278 13303 13284 13276 13272>, + <14134 13284 13305 13284 13277 13272>, + <14220 13295 13307 13283 13276 13273>, + <14312 13311 13309 13282 13275 13273>, + <14405 13332 13311 13282 13275 13273>, + <14501 13362 13312 13282 13276 13274>, + <14596 13393 13313 13282 13276 13274>, + <14687 13416 13313 13282 13277 13274>, + <14781 13443 13314 13283 13277 13274>, + <14884 13488 13317 13284 13276 13273>, + <14998 13565 13322 13285 13276 13274>, + <14988 13596 13326 13288 13278 13276>, + <15059 13649 13330 13289 13279 13277>, + <15152 13712 13339 13294 13283 13279>, + <15247 13784 13351 13296 13282 13277>, + <15340 13847 13352 13295 13280 13276>, + <15443 13922 13355 13295 13281 13277>, + <15627 14060 13367 13298 13284 13279>, + <15865 14258 13384 13304 13286 13283>, + <16661 14530 13427 13312 13291 13287>, + <16661 14530 13427 13312 13291 13287>, + <16661 14530 13427 13312 13291 13287>; + }; + + qcom,pc-temp-y4-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <18008 16999 16718 16500 16460 16456>, + <18072 17065 16719 16497 16459 16454>, + <18111 17109 16717 16493 16457 16452>, + <18131 17135 16714 16489 16455 16451>, + <18138 17148 16709 16486 16453 16449>, + <18139 17152 16703 16485 16453 16448>, + <18029 17137 16693 16486 16452 16448>, + <17863 17112 16683 16486 16452 16447>, + <17896 17097 16681 16488 16452 16448>, + <18235 17083 16680 16490 16454 16449>, + <18508 17077 16680 16492 16455 16450>, + <18619 17111 16683 16496 16457 16451>, + <18700 17180 16689 16501 16461 16452>, + <18607 17260 16712 16509 16466 16453>, + <18107 17384 16786 16522 16473 16457>, + <17766 17446 16846 16538 16481 16462>, + <17718 17379 16883 16554 16487 16468>, + <17687 17259 16908 16574 16496 16475>, + <17629 17174 16905 16613 16516 16490>, + <17534 17108 16880 16675 16554 16516>, + <17407 17042 16841 16697 16568 16526>, + <17159 16963 16746 16628 16535 16505>, + <16891 16889 16644 16542 16492 16476>, + <16806 16845 16607 16507 16473 16463>, + <16770 16818 16587 16484 16461 16454>, + <16755 16786 16580 16478 16457 16452>, + <16753 16727 16578 16479 16457 16452>, + <16753 16673 16578 16480 16457 16452>, + <16756 16669 16579 16483 16459 16453>, + <16763 16685 16581 16490 16462 16455>, + <16771 16697 16581 16497 16467 16458>, + <16783 16705 16558 16506 16473 16464>, + <16797 16717 16535 16512 16481 16470>, + <16813 16732 16538 16515 16488 16475>, + <16831 16753 16552 16517 16495 16479>, + <16846 16769 16568 16515 16495 16479>, + <16858 16781 16587 16493 16474 16465>, + <16869 16791 16601 16473 16454 16451>, + <16877 16794 16600 16470 16450 16451>, + <16883 16792 16599 16468 16449 16452>, + <16885 16788 16599 16469 16448 16452>, + <16876 16770 16608 16474 16449 16451>, + <16865 16757 16618 16479 16448 16448>, + <16860 16757 16628 16481 16442 16435>, + <16879 16761 16645 16484 16444 16435>, + <16891 16789 16652 16498 16455 16453>, + <16943 16827 16682 16511 16475 16497>, + <17014 16881 16733 16537 16536 16562>, + <17081 16976 16802 16590 16557 16530>, + <17089 17020 16800 16563 16478 16467>, + <17047 16991 16801 16554 16477 16469>, + <17042 17006 16834 16584 16500 16488>, + <17105 17082 16903 16649 16553 16544>, + <17555 17233 17100 16828 16767 16718>, + <17555 17233 17100 16828 16767 16718>, + <17555 17233 17100 16828 16767 16718>; + }; + + qcom,pc-temp-y5-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <11727 11942 13506 16264 17485 13743>, + <11187 12181 13834 16304 17713 15443>, + <10948 12440 14154 16154 17943 16969>, + <10946 12689 14439 15889 18142 18238>, + <11119 12897 14661 15580 18277 19164>, + <11403 13035 14792 15300 18315 19661>, + <12465 13100 14855 14911 18249 19739>, + <13822 13150 14864 14518 18113 19553>, + <13670 13301 14746 14395 17867 19106>, + <11695 13714 14420 14341 17361 18217>, + <10462 13958 14096 14326 16853 17639>, + <11501 13114 13863 14506 16406 17596>, + <13219 11865 13624 14722 15945 17611>, + <13884 11823 13278 14498 15435 17295>, + <13848 12774 12797 13693 14834 16535>, + <13691 13748 12589 13309 14470 15845>, + <13167 14554 12751 13334 14271 15143>, + <12586 15195 13107 13390 14142 14574>, + <13020 15258 13900 13564 14152 14504>, + <14413 15027 15523 14068 14254 14631>, + <15535 14881 16342 14723 14446 14876>, + <15575 14923 16444 15913 15152 15787>, + <15061 15014 16478 16911 16165 16899>, + <14339 15197 16434 16931 17201 17475>, + <12334 15627 16343 16746 18331 17902>, + <11314 15978 16268 16667 18791 18109>, + <11399 15505 16100 16581 18776 18180>, + <11512 14520 15934 16533 18615 18169>, + <11525 13737 16028 16730 18175 18053>, + <11550 12045 16380 17082 17340 17858>, + <11588 11352 16565 17187 16713 17565>, + <11718 11445 16382 17060 16198 16814>, + <11865 11550 16160 16944 15883 16183>, + <11908 11637 16198 17254 16375 16323>, + <11980 11737 16327 17954 17689 16949>, + <12075 11818 16423 18152 18505 17767>, + <12422 11915 16495 17982 18987 19240>, + <12794 12071 16540 17734 19303 20755>, + <12843 12334 16444 17425 19669 21829>, + <12812 12824 16116 17020 20264 22723>, + <12740 13086 15663 16654 20463 22879>, + <12356 12741 14862 16171 20541 22449>, + <11882 12264 14369 16034 20626 22711>, + <11570 11949 14152 16151 21020 24835>, + <11487 11951 14006 15816 18734 20674>, + <11662 11903 13943 16003 17805 20181>, + <11655 12101 13682 15426 17094 17583>, + <11840 12432 13801 16015 16324 15006>, + <12476 12948 14155 15430 14898 14594>, + <12752 13151 14323 16256 17791 17272>, + <12081 13073 14285 16869 17629 17625>, + <11734 12858 14199 16707 19166 17889>, + <11770 12567 13945 17145 18317 18429>, + <11976 12244 15223 16959 17784 17367>, + <11976 12244 15223 16959 17784 17367>, + <11976 12244 15223 16959 17784 17367>; + }; + + qcom,pc-temp-y6-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <6551 5600 5220 4990 4943 4930>, + <6534 5605 5216 4988 4942 4931>, + <6511 5605 5211 4986 4942 4931>, + <6488 5601 5205 4984 4942 4931>, + <6470 5594 5199 4983 4942 4932>, + <6461 5584 5193 4982 4942 4932>, + <6460 5570 5186 4981 4942 4932>, + <6461 5554 5179 4980 4942 4932>, + <6450 5545 5174 4981 4942 4932>, + <6403 5538 5169 4981 4942 4933>, + <6375 5535 5166 4982 4943 4933>, + <6433 5536 5165 4984 4943 4933>, + <6517 5539 5164 4987 4945 4934>, + <6504 5548 5169 4989 4946 4935>, + <6362 5577 5191 4993 4949 4936>, + <6258 5593 5206 4998 4951 4938>, + <6231 5576 5210 5003 4954 4939>, + <6212 5543 5212 5009 4956 4942>, + <6209 5514 5211 5021 4962 4946>, + <6205 5486 5203 5040 4974 4955>, + <6199 5459 5190 5046 4978 4958>, + <6156 5431 5159 5023 4966 4950>, + <6101 5407 5125 4994 4951 4939>, + <6096 5397 5113 4982 4945 4934>, + <6119 5393 5107 4974 4941 4931>, + <6146 5387 5105 4972 4940 4930>, + <6186 5373 5105 4973 4940 4930>, + <6237 5359 5106 4974 4940 4931>, + <6285 5359 5108 4975 4940 4931>, + <6335 5374 5112 4978 4941 4932>, + <6386 5394 5113 4981 4942 4933>, + <6438 5418 5109 4984 4944 4934>, + <6491 5448 5106 4986 4946 4936>, + <6546 5478 5109 4988 4949 4938>, + <6603 5512 5120 4989 4952 4939>, + <6665 5547 5133 4989 4952 4939>, + <6732 5583 5145 4983 4946 4936>, + <6803 5621 5158 4978 4940 4932>, + <6876 5662 5167 4978 4940 4932>, + <6950 5708 5176 4978 4940 4933>, + <7022 5754 5186 4979 4940 4933>, + <7089 5799 5201 4982 4942 4934>, + <7157 5850 5219 4985 4942 4933>, + <7235 5915 5240 4987 4939 4929>, + <7330 6003 5272 4991 4941 4930>, + <7326 6045 5279 4998 4946 4937>, + <7395 6104 5304 5003 4952 4950>, + <7483 6173 5341 5014 4973 4970>, + <7577 6261 5385 5032 4978 4960>, + <7656 6331 5397 5024 4954 4941>, + <7727 6392 5417 5023 4955 4943>, + <7873 6517 5468 5035 4965 4950>, + <8078 6702 5539 5060 4982 4970>, + <8853 6954 5681 5120 5047 5023>, + <8853 6954 5681 5120 5047 5023>, + <8853 6954 5681 5120 5047 5023>; + }; + +}; diff --git a/qcom/smb1355.dtsi b/qcom/smb1355.dtsi new file mode 100644 index 00000000..f244a0dc --- /dev/null +++ b/qcom/smb1355.dtsi @@ -0,0 +1,87 @@ +#include + +smb1355: qcom,smb1355@c { + compatible = "qcom,i2c-pmic"; + reg = <0xc>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x2 0xC5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt_names = "smb1355"; + interrupt-controller; + #interrupt-cells = <3>; + qcom,periph-map = <0x10 0x12 0x13 0x16>; + status = "disabled"; + + smb1355_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + smb1355_charger: qcom,smb1355-charger@1000 { + compatible = "qcom,smb1355"; + qcom,pmic-revid = <&smb1355_revid>; + reg = <0x1000 0x700>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&smb1355>; + status = "disabled"; + + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = <0x10 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "chg-state-change"; + }; + + qcom,chgr-misc@1600 { + reg = <0x1600 0x100>; + interrupts = <0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x16 0x6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog-bark", + "temperature-change"; + }; + }; +}; + +smb1355_0: qcom,smb1355@8 { + compatible = "qcom,i2c-pmic"; + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x0 0xd1 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt_names = "smb1355_0"; + interrupt-controller; + #interrupt-cells = <3>; + qcom,periph-map = <0x10 0x12 0x13 0x16>; + status = "disabled"; + + smb1355_revid_0: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + smb1355_charger_0: qcom,smb1355-charger@1000 { + compatible = "qcom,smb1355"; + qcom,pmic-revid = <&smb1355_revid_0>; + reg = <0x1000 0x700>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&smb1355_0>; + status = "disabled"; + + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = <0x10 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "chg-state-change"; + }; + + qcom,chgr-misc@1600 { + reg = <0x1600 0x100>; + interrupts = <0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x16 0x6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog-bark", + "temperature-change"; + }; + }; +}; diff --git a/qcom/smb1394.dtsi b/qcom/smb1394.dtsi new file mode 100644 index 00000000..23d03b6b --- /dev/null +++ b/qcom/smb1394.dtsi @@ -0,0 +1,40 @@ +#include +#include + +smb1394: qcom,smb1394@34 { + compatible = "qcom,i2c-pmic"; + reg = <0x34>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + qcom,periph-map = <0x6 0x26 0x27>; + status = "disabled"; + + smb1394_revid: qcom,revid { + compatible = "qcom,qpnp-revid"; + reg = <0x100>; + }; + + smb1394_div2_cp_primary: qcom,div2_cp_pry { + compatible = "qcom,smb1394-div2-cp-primary"; + qcom,pmic-revid = <&smb1394_revid>; + #io-channel-cells = <1>; + interrupts = <0x26 0x1 IRQ_TYPE_EDGE_RISING>, + <0x26 0x3 IRQ_TYPE_EDGE_RISING>, + <0x26 0x5 IRQ_TYPE_EDGE_RISING>, + <0x26 0x7 IRQ_TYPE_EDGE_RISING>, + <0x27 0x5 IRQ_TYPE_EDGE_RISING>, + <0x27 0x6 IRQ_TYPE_EDGE_RISING>, + <0x27 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "temp-shdwn", + "div2-irev", + "usbin-uv", + "usbin-ov", + "div2-ilim", + "div2-win-uv", + "div2-win-ov"; + qcom,div2-cp-min-ilim-ua = <1000000>; + status = "disabled"; + }; +};