From 3679382c9f3f9b70129d06acd7370d252f8eefd5 Mon Sep 17 00:00:00 2001 From: Naveen Kumar Goud Arepalli Date: Thu, 13 Oct 2022 11:36:31 +0530 Subject: [PATCH] ARM: dts: msm: Enable support for sdcc1 on sa410 Enable support for sdcc1 on SA410, eMMC will be mounted on sdcc1. Change-Id: Ia06fb217d82c4040c68abcba81c8bc5fe8a558c9 --- qcom/sa410m-idp.dtsi | 16 ++++++++++++ qcom/sa410m-nand-ccard.dts | 4 +++ qcom/sa410m-nand-idp.dts | 4 +++ qcom/sa410m-pinctrl.dtsi | 50 ++++++++++++++++++++++++++++++++++++++ qcom/sa410m-rumi.dtsi | 23 ++++++++++++++++++ qcom/sa410m.dtsi | 48 ++++++++++++++++++++++++++++++++++++ 6 files changed, 145 insertions(+) diff --git a/qcom/sa410m-idp.dtsi b/qcom/sa410m-idp.dtsi index dbb2d010..d9b9fec9 100644 --- a/qcom/sa410m-idp.dtsi +++ b/qcom/sa410m-idp.dtsi @@ -3,3 +3,19 @@ &qnand_1 { status = "ok"; }; + +&sdhc_1 { + status = "ok"; + vdd-supply = <&L20A>; + qcom,vdd-voltage-level = <2856000 2856000>; + qcom,vdd-current-level = <0 570000>; + vdd-io-supply = <&L14A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + max-frequency = <100000000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; diff --git a/qcom/sa410m-nand-ccard.dts b/qcom/sa410m-nand-ccard.dts index 3ba0a6f2..6429a222 100644 --- a/qcom/sa410m-nand-ccard.dts +++ b/qcom/sa410m-nand-ccard.dts @@ -12,3 +12,7 @@ &qnand_1 { status = "ok"; }; + +&sdhc_1 { + status = "disabled"; +}; diff --git a/qcom/sa410m-nand-idp.dts b/qcom/sa410m-nand-idp.dts index 35baded8..920712c2 100644 --- a/qcom/sa410m-nand-idp.dts +++ b/qcom/sa410m-nand-idp.dts @@ -12,3 +12,7 @@ &qnand_1 { status = "ok"; }; + +&sdhc_1 { + status = "disabled"; +}; diff --git a/qcom/sa410m-pinctrl.dtsi b/qcom/sa410m-pinctrl.dtsi index ce0b7470..e80bf951 100644 --- a/qcom/sa410m-pinctrl.dtsi +++ b/qcom/sa410m-pinctrl.dtsi @@ -691,4 +691,54 @@ }; }; }; + + sdc1_on: sdc1_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; }; diff --git a/qcom/sa410m-rumi.dtsi b/qcom/sa410m-rumi.dtsi index 7239e490..cdcc4486 100644 --- a/qcom/sa410m-rumi.dtsi +++ b/qcom/sa410m-rumi.dtsi @@ -42,3 +42,26 @@ status = "ok"; }; +&sdhc_1 { + status = "ok"; + vdd-supply = <&L20A>; + qcom,vdd-voltage-level = <2856000 2856000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L14A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + /delete-property/ mmc-ddr-1_8v; + /delete-property/ mmc-hs200-1_8v; + /delete-property/ mmc-hs400-1_8v; + /delete-property/ mmc-hs400-enhanced-strobe; + + max-frequency = <100000000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; diff --git a/qcom/sa410m.dtsi b/qcom/sa410m.dtsi index e7f26e36..5b74d8c0 100644 --- a/qcom/sa410m.dtsi +++ b/qcom/sa410m.dtsi @@ -25,6 +25,7 @@ aliases { serial0 = &qupv3_se4_2uart; qpic_nand1 = &qnand_1; + mmc0 = &sdhc_1; /*SDC1 eMMC slot*/ }; firmware: firmware {}; @@ -521,6 +522,53 @@ qcom,iommu-dma = "bypass"; status = "disabled"; }; + + sdhc_1: sdhci@4744000 { + status = "disabled"; + + compatible = "qcom,sdhci-msm-v5"; + reg = <0x04744000 0x1000>, <0x04745000 0x1000>; + reg-names = "hc", "cqhci"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + bus-width = <8>; + non-removable; + supports-cqe; + + no-sd; + no-sdio; + qcom,restore-after-cx-collapse; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + cap-mmc-hw-reset; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", "iface"; + + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040868>; + + /* Add dt entry for gcc hw reset */ + //resets = <&gcc GCC_EMMC_BCR>; + //reset-names = "core_reset"; + + iommus = <&apps_smmu 0xC0 0x0>; + qcom,iommu-dma = "bypass"; + + qos0 { + mask = <0x0f>; + vote = <44>; + }; + }; }; #include "sa410m-stub-regulators.dtsi"