From 5cfdcdde335290bcd85c00254f9c245eb97b4f04 Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Mon, 17 Oct 2022 17:52:34 +0530 Subject: [PATCH 1/2] bindings: interrupt-controller: Update bindings for sa410m to mpm irqchip Update target compatible with sa410m for the mpm irqchip dt-binding. Change-Id: I59fd49fed011165eb58a4b01e6783425bdc0b00f --- bindings/interrupt-controller/qcom,mpm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/interrupt-controller/qcom,mpm.txt b/bindings/interrupt-controller/qcom,mpm.txt index 9abf5c6b..f4196db8 100644 --- a/bindings/interrupt-controller/qcom,mpm.txt +++ b/bindings/interrupt-controller/qcom,mpm.txt @@ -27,6 +27,7 @@ Properties: "qcom,mpm-khaje" "qcom,mpm-monaco" "qcom,mpm-scuba" + "qcom,mpm-sa410m" - interrupts: Usage: required From 9ac7aa2795ed89148182c27bac2a40d4abd74423 Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Wed, 12 Oct 2022 19:28:16 +0530 Subject: [PATCH 2/2] ARM: dts: msm: Add LPM modes, mpm, rpm_smd and stats nodes for SA410m_auto Add LPM modes, mpm, rpm_smd and stats nodes. Change-Id: Ifc19fa4cd55ee4f6ea1144fdcc8f122fa811b6ce --- qcom/sa410m.dtsi | 96 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 95 insertions(+), 1 deletion(-) diff --git a/qcom/sa410m.dtsi b/qcom/sa410m.dtsi index 28354d71..afaff2c2 100644 --- a/qcom/sa410m.dtsi +++ b/qcom/sa410m.dtsi @@ -36,6 +36,8 @@ device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x0>; + cpu-idle-states = <&SILVER_OFF>; + power-domains = <&CPU_PD0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -59,6 +61,8 @@ device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x1>; + cpu-idle-states = <&SILVER_OFF>; + power-domains = <&CPU_PD1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -79,6 +83,8 @@ compatible = "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + cpu-idle-states = <&SILVER_OFF>; + power-domains = <&CPU_PD2>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; @@ -98,6 +104,8 @@ compatible = "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + cpu-idle-states = <&SILVER_OFF>; + power-domains = <&CPU_PD3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; @@ -133,9 +141,56 @@ }; }; + idle-states { + SILVER_OFF: silver-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <297>; + exit-latency-us = <324>; + min-residency-us = <1110>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + SILVER_CLUSTER_D3: silver-cluster-d3 { /* D3 */ + compatible = "domain-idle-state"; + idle-state-name = "pwr-l2-pc"; + entry-latency-us = <800>; + exit-latency-us = <2118>; + min-residency-us = <7376>; + arm,psci-suspend-param = <0x41000043>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD2: cpu-pd2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD3: cpu-pd3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD0: cluster-pd0 { + #power-domain-cells = <0>; + domain-idle-states = <&SILVER_CLUSTER_D3>; + }; + }; chosen { @@ -282,6 +337,45 @@ #gpio-cells = <0>; }; + mpm: interrupt-controller@45f01b8 { + compatible = "qcom,mpm-sa410m", "qcom,mpm"; + reg = <0x45f01b8 0x1000>, + <0xf111008 0x4>, /* MSM_APCS_GCC_BASE 4K */ + <0xf121000 0x1000>; + reg-names = "vmpm", "ipc", "timer"; + interrupts = ; + qcom,num-mpm-irqs = <96>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + interrupts = ; + power-domains = <&CLUSTER_PD>; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + cluster-device { + compatible = "qcom,lpm-cluster-dev"; + power-domains = <&CLUSTER_PD>; + }; + + rpm-sleep-stats@4690000 { + compatible = "qcom,rpm-sleep-stats"; + reg = <0x04690000 0x400>; + }; + + qcom,rpm-master-stats@45f0150 { + compatible = "qcom,rpm-master-stats"; + reg = <0x45f0150 0x5000>; + qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ"; + qcom,master-stats-version = <2>; + qcom,master-offset = <4096>; + }; + arch_timer: timer { compatible = "arm,armv8-timer"; interrupts = , @@ -361,7 +455,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - //wakeup-parent = <&wakegic>; + wakeup-parent = <&mpm>; }; qcom-secure-buffer {