From 48dc18df7c6f52417df6079430be548bcf0fdcbd Mon Sep 17 00:00:00 2001 From: Mukesh Kumar Savaliya Date: Fri, 20 May 2022 10:15:14 +0530 Subject: [PATCH] ARM: dts: msm: change PIN func of qup2_se0 per pinctrl driver This change is to modify the pinctrl function for GPIO no - 56, 57, 58, 59 for QUP2 SE0 as per the IPCAT. This also needs a change from pinctrl.c to define the same name in the driver. Change-Id: I1eafb7565c6f4eedcae6dcc6f48b233ddfbf0092 --- qcom/kalama-pinctrl.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/qcom/kalama-pinctrl.dtsi b/qcom/kalama-pinctrl.dtsi index 2f4e901a..dba20851 100644 --- a/qcom/kalama-pinctrl.dtsi +++ b/qcom/kalama-pinctrl.dtsi @@ -1078,7 +1078,7 @@ qupv3_se8_i2c_sda_active: qupv3_se8_i2c_sda_active { mux { pins = "gpio56"; - function = "qup2_se0_l0"; + function = "qup2_se0_l0_mira"; }; config { @@ -1091,7 +1091,7 @@ qupv3_se8_i2c_scl_active: qupv3_se8_i2c_scl_active { mux { pins = "gpio57"; - function = "qup2_se0_l1"; + function = "qup2_se0_l1_mira"; }; config { @@ -1187,7 +1187,7 @@ qupv3_se8_spi_miso_active: qupv3_se8_spi_miso_active { mux { pins = "gpio56"; - function = "qup2_se0_l0"; + function = "qup2_se0_l0_mira"; }; config { @@ -1200,7 +1200,7 @@ qupv3_se8_spi_mosi_active: qupv3_se8_spi_mosi_active { mux { pins = "gpio57"; - function = "qup2_se0_l1"; + function = "qup2_se0_l1_mira"; }; config { @@ -1213,7 +1213,7 @@ qupv3_se8_spi_clk_active: qupv3_se8_spi_clk_active { mux { pins = "gpio58"; - function = "qup2_se0_l2"; + function = "qup2_se0_l2_mira"; }; config { @@ -1226,7 +1226,7 @@ qupv3_se8_spi_cs_active: qupv3_se8_spi_cs_active { mux { pins = "gpio59"; - function = "qup2_se0_l3"; + function = "qup2_se0_l3_mira"; }; config {