From 4b8a31cd244a17faa80d7aec51bac3fec631aa40 Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Fri, 21 Jan 2022 12:05:56 -0800 Subject: [PATCH] ARM: dts: msm: Use RPMH_CXO_PAD_CLK with USB PHYs as ref_clk_src on Kalama CXO_CLK is running as 19.2 MHz whereas USB PHYs are directly feed ref clock from XO which is running at 38.4MHz. Hence replace RPMH_CXO_CLK with RPMH_CXO_PAD_CLK for voting/devoting from USB PHYs driver. Change-Id: I7c6fe3aac46ec1615323ce6b6886df40dc7425ea --- qcom/kalama-usb.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/kalama-usb.dtsi b/qcom/kalama-usb.dtsi index b1fc272c..a890839d 100644 --- a/qcom/kalama-usb.dtsi +++ b/qcom/kalama-usb.dtsi @@ -115,7 +115,7 @@ qcom,vdd-voltage-level = <0 880000 880000>; vdda12-supply = <&pm_v6e_l3>; - clocks = <&rpmhcc RPMH_CXO_CLK>, + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>, <&tcsrcc TCSR_USB2_CLKREF_EN>; clock-names = "ref_clk_src", "ref_clk"; @@ -139,7 +139,7 @@ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, - <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_PAD_CLK>, <&tcsrcc TCSR_USB3_CLKREF_EN>, <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",