From 4f35d8bab146e9412fe3706beaa9f715bc6aa4ee Mon Sep 17 00:00:00 2001
From: Imran Shaik <imrashai@qti.qualcomm.com>
Date: Thu, 26 May 2022 10:39:52 +0530
Subject: [PATCH] ARM: dts: msm: Add support for dummy clocks/GDSC for
 sdxbaagha

Add the clock and GDSC handles for clients to be able to request
on them for sdxbaagha.

Change-Id: I2683a908234b8129d415026cd682bba4574d4c6f
---
 qcom/sdxbaagha.dtsi | 75 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)

diff --git a/qcom/sdxbaagha.dtsi b/qcom/sdxbaagha.dtsi
index 16654416..4774ac2e 100644
--- a/qcom/sdxbaagha.dtsi
+++ b/qcom/sdxbaagha.dtsi
@@ -1,4 +1,6 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,gcc-sdxbaagha.h>
 
 / {
 	#address-cells = <1>;
@@ -206,6 +208,79 @@
 	qcom,secure-buffer {
 		compatible = "qcom,secure-buffer";
 	};
+
+	clocks {
+		xo_board: xo_board {
+			compatible = "fixed-clock";
+			clock-frequency = <19200000>;
+			clock-output-names = "xo_board";
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			clock-output-names = "sleep_clk";
+			#clock-cells = <0>;
+		};
+
+		pcie_pipe_clk: pcie_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "pcie_pipe_clk";
+			#clock-cells = <0>;
+		};
+	};
+
+	bi_tcxo: bi_tcxo {
+		compatible = "fixed-factor-clock";
+		clocks = <&xo_board>;
+		clock-mult = <1>;
+		clock-div = <1>;
+		#clock-cells = <0>;
+		clock-output-names = "bi_tcxo";
+	};
+
+	bi_tcxo_ao: bi_tcxo_ao {
+		compatible = "fixed-factor-clock";
+		clocks = <&xo_board>;
+		clock-mult = <1>;
+		clock-div = <1>;
+		#clock-cells = <0>;
+		clock-output-names = "bi_tcxo_ao";
+	};
+
+	rpmhcc: clock-controller {
+		compatible = "fixed-clock";
+		clock-output-names = "rpmh_clocks";
+		clock-frequency = <19200000>;
+		#clock-cells = <1>;
+	};
+
+	gcc: clock-controller@80000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "gcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	/* GCC GDSCs */
+	gcc_emac0_gdsc: qcom,gdsc@f1004 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "gcc_emac0_gdsc";
+		qcom,support-hw-trigger;
+	};
+
+	gcc_pcie_gdsc: qcom,gdsc@d3004 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "gcc_pcie_gdsc";
+		qcom,support-hw-trigger;
+	};
+
+	gcc_usb20_gdsc: qcom,gdsc@a7004 {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "gcc_usb20_gdsc";
+	};
 };
 
 #include "sdxbaagha-pinctrl.dtsi"