From 7062f308e42d6e50c4f5e238bf291bcf62b48598 Mon Sep 17 00:00:00 2001
From: Yatish Kumar Singh <yatishku@qti.qualcomm.com>
Date: Mon, 13 Jun 2022 18:58:28 +0530
Subject: [PATCH] ARM: dts: msm: Add QUPv3 UART console node for sdxbaagha

Enable console support on sdxbaagha.

Change-Id: Ic7ea9a049b2066100b8120d7da5c459429ee44c1
---
 qcom/sdxbaagha-pinctrl.dtsi | 41 ++++++++++++++++++++++++++++++++++++
 qcom/sdxbaagha-qupv3.dtsi   | 42 +++++++++++++++++++++++++++++++++++++
 qcom/sdxbaagha-rumi.dtsi    |  4 ++++
 qcom/sdxbaagha.dtsi         |  9 +++++++-
 4 files changed, 95 insertions(+), 1 deletion(-)
 create mode 100644 qcom/sdxbaagha-qupv3.dtsi

diff --git a/qcom/sdxbaagha-pinctrl.dtsi b/qcom/sdxbaagha-pinctrl.dtsi
index e385ccce..8a5dd3c8 100644
--- a/qcom/sdxbaagha-pinctrl.dtsi
+++ b/qcom/sdxbaagha-pinctrl.dtsi
@@ -8,5 +8,46 @@
 		interrupt-controller;
 		interrupt-parent = <&intc>;
 		#interrupt-cells = <2>;
+
+		qupv3_se3_2uart_pins: qupv3_se3_2uart_pins {
+			qupv3_se3_2uart_tx_active: qupv3_se3_2uart_tx_active {
+				mux {
+					pins = "gpio8";
+					function = "qup0_se3_l2_mira";
+				};
+
+				config {
+					pins = "gpio8";
+					drive-strength= <2>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se3_2uart_rx_active: qupv3_se3_2uart_rx_active {
+				mux {
+					pins = "gpio9";
+					function = "qup0_se3_l3_mira";
+				};
+
+				config {
+					pins = "gpio9";
+					drive-strength= <2>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se3_2uart_sleep: qupv3_se3_2uart_sleep {
+				mux {
+					pins = "gpio8", "gpio9";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio8", "gpio9";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+		};
 	};
 };
diff --git a/qcom/sdxbaagha-qupv3.dtsi b/qcom/sdxbaagha-qupv3.dtsi
new file mode 100644
index 00000000..8a77bfff
--- /dev/null
+++ b/qcom/sdxbaagha-qupv3.dtsi
@@ -0,0 +1,42 @@
+&soc {
+	/* QUPv3_0 wrapper instance */
+	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0x9c0000 0x2000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		/*
+		 * iommus = <&apps_smmu 0xa3 0x0>;
+		 * qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		 * qcom,iommu-geometry = <0x40000000 0x10000000>;
+		 * qcom,iommu-dma = "fastmap";
+		 * dma-coherent;
+		 */
+		ranges;
+		status = "ok";
+
+		/*PORed Debug UART Instance */
+		qupv3_se3_2uart: qcom,qup_uart@98c000 {
+			compatible = "qcom,geni-debug-uart";
+			reg = <0x98c000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+			/*
+			 * interconnect-names = "qup-core", "qup-config", "qup-memory";
+			 * interconnects =
+			 * <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
+			 * <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+			 * <&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
+			 */
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se3_2uart_tx_active>, <&qupv3_se3_2uart_rx_active>;
+			pinctrl-1 = <&qupv3_se3_2uart_sleep>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/qcom/sdxbaagha-rumi.dtsi b/qcom/sdxbaagha-rumi.dtsi
index 17f1e228..893253f1 100644
--- a/qcom/sdxbaagha-rumi.dtsi
+++ b/qcom/sdxbaagha-rumi.dtsi
@@ -1,2 +1,6 @@
 &soc {
 };
+
+&qupv3_se3_2uart {
+	qcom,rumi_platform;
+};
diff --git a/qcom/sdxbaagha.dtsi b/qcom/sdxbaagha.dtsi
index 2b820090..57f09519 100644
--- a/qcom/sdxbaagha.dtsi
+++ b/qcom/sdxbaagha.dtsi
@@ -11,7 +11,9 @@
 	qcom,msm-id = <570 0x10000>, <571 0x10000>;
 	interrupt-parent = <&intc>;
 
-	aliases { };
+	aliases {
+		serial0 = &qupv3_se3_2uart;
+	};
 
 	chosen { };
 
@@ -295,3 +297,8 @@
 #include "sdxbaagha-pinctrl.dtsi"
 #include "sdxbaagha-dma-heaps.dtsi"
 #include "msm-arm-smmu-sdxbaagha.dtsi"
+#include "sdxbaagha-qupv3.dtsi"
+
+&qupv3_se3_2uart {
+	status = "ok";
+};