From bd9db74256687e210cbecdd0e3776ab753ddcf83 Mon Sep 17 00:00:00 2001 From: Praveen koya Date: Mon, 17 Oct 2022 16:38:10 +0530 Subject: [PATCH 01/71] ARM: dts: qcom: Add AON device tree to monaco Include AON device tree file to monaco. Change-Id: I2d5c9a6c65af7cfa8828edf910d8de06fafa0891 --- qcom/monaco-idp-v1.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/monaco-idp-v1.dtsi b/qcom/monaco-idp-v1.dtsi index 28aa6597..46a0a0f2 100644 --- a/qcom/monaco-idp-v1.dtsi +++ b/qcom/monaco-idp-v1.dtsi @@ -2,6 +2,7 @@ #include #include #include +#include "slate.dtsi" &soc { bluetooth: bt_wcn3990 { From a589228e0f93964f5ce80537c961560e9e6a1b01 Mon Sep 17 00:00:00 2001 From: Grace An Date: Tue, 18 Oct 2022 14:30:05 -0700 Subject: [PATCH 02/71] ARM: dts: msm: increase size of memory region for hw-fence driver This change increases the size of the carved-out memory region for the hw-fence driver to communicate with the fence controller component. Change-Id: Ida9135a5af6ffc4221246133efddbf6b28b484c2 --- qcom/kalama.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/kalama.dtsi b/qcom/kalama.dtsi index 6955570f..451888a2 100644 --- a/qcom/kalama.dtsi +++ b/qcom/kalama.dtsi @@ -506,7 +506,7 @@ hwfence_shbuf: hwfence-shmem { no-map; - reg = <0x0 0xe6440000 0x0 0x279000>; + reg = <0x0 0xe6440000 0x0 0x2dd000>; }; trust_ui_vm_mem: trust_ui_vm_region@f3800000 { From a1f4d1d44d98ecb2269207b44f7c63f3910e24af Mon Sep 17 00:00:00 2001 From: Sarannya S Date: Thu, 20 Oct 2022 11:06:57 +0530 Subject: [PATCH 03/71] ARM: dts: msm: no APPS wake for Sensors QMI Add 0x190 Sensors QMI service, to QRTR ADSP "no-wake-svc" node. This will ensure any packets intended for Sensor QMI service will not force a wake up on APPS. Change-Id: I7f11ea37ba63d2d6b134222c239f206873095984 --- qcom/khaje.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index e1cf6674..78cf706e 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -2218,6 +2218,7 @@ qcom,intents = <0x800 5 0x2000 3 0x4400 2>; + qcom,no-wake-svc = <0x190>; }; qcom,msm_fastrpc_rpmsg { From de4e6f24fdf8954dee1f4d0ca7963ba34f04cbad Mon Sep 17 00:00:00 2001 From: Shivangi Yadav Date: Fri, 28 Oct 2022 14:09:48 +0530 Subject: [PATCH 04/71] ARM: dts: msm: Correct MHI EP's mhi-soc-reset-offset on cinder Correct MHI EP's mhi-soc-reset-offset on cinder. Change-Id: If4bbfaff4c477211c8bfd753094e75b72582fc20 --- qcom/cinder.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi index 0bc99812..fef23b54 100644 --- a/qcom/cinder.dtsi +++ b/qcom/cinder.dtsi @@ -1316,7 +1316,7 @@ qcom,pcie-mhi-a7-irq; qcom,tcsr-not-supported; qcom,phy-status-reg2 = <0x1214>; - qcom,mhi-soc-reset-offset = <0xb01b8>; + qcom,mhi-soc-reset-offset = <0xb001b8>; qcom,aux-clk = <0x11>; qcom,sriov-mask = <0x1E0>; From 17f3075afb5c8582d63addc529bacf35a4696fe7 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Thu, 20 Oct 2022 11:58:32 +0530 Subject: [PATCH 05/71] ARM: dts: msm: Modify the obsolete property with proper name Regardless of whether the runtime suspend is performed or not, perform PM_Suspend for msm usb for auto target. Modify the property obsolete name from old kernel to align with kernel upgrades. Change-Id: Ie4f4208e773f0a4903c19b85c8dcb8d3583081ba --- qcom/sm8150-usb.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sm8150-usb.dtsi b/qcom/sm8150-usb.dtsi index 65ec1043..031d5413 100644 --- a/qcom/sm8150-usb.dtsi +++ b/qcom/sm8150-usb.dtsi @@ -34,7 +34,7 @@ qcom,core-clk-rate = <200000000>; qcom,core-clk-rate-hs = <66666667>; - qcom,ignore-wakeup-src-in-hostmode; + qcom,host-poweroff-in-pm-suspend; interconnect-names = "usb-ddr", "ddr-usb"; interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, @@ -105,7 +105,7 @@ "ss_phy_irq","dm_hs_phy_irq"; qcom,use-pdc-interrupts; qcom,default-mode-host; - qcom,ignore-wakeup-src-in-hostmode; + qcom,host-poweroff-in-pm-suspend; USB3_GDSC-supply = <&usb30_sec_gdsc>; clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, From 16e2759515bb5fd03170dbd53604c28b2bd816a0 Mon Sep 17 00:00:00 2001 From: Anurag Chouhan Date: Mon, 7 Nov 2022 11:32:36 +0530 Subject: [PATCH 06/71] ARM: dts: qcom: Add interconnect and smr handoff for monaco Add interconnect and smr handoff entry for monaco smmu. Change-Id: I0c36f30bfabc06c3cf2a0efb38ca6449d66744c3 --- qcom/msm-arm-smmu-monaco.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/msm-arm-smmu-monaco.dtsi b/qcom/msm-arm-smmu-monaco.dtsi index 5ae347c6..f1a4d55a 100644 --- a/qcom/msm-arm-smmu-monaco.dtsi +++ b/qcom/msm-arm-smmu-monaco.dtsi @@ -57,6 +57,7 @@ #iommu-cells = <2>; qcom,skip-init; qcom,use-3-lvl-tables; + qcom,handoff-smrs = <0x420 0x2>; #global-interrupts = <1>; #size-cells = <1>; #address-cells = <1>; @@ -127,7 +128,11 @@ , ; + interconnects = <&bimc MASTER_AMPSS_M0 + &system_noc SLAVE_TCU>; + qcom,active-only; + qcom,actlr = /* For rt TBU +3 deep PF */ <0x400 0x3ff 0x103>, @@ -140,6 +145,10 @@ <0xc7f2200 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; + interconnects = <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_IMEM_CFG>, + <&bimc MASTER_AMPSS_M0 + &system_noc SLAVE_TCU>; qcom,active-only; qcom,iova-width = <36>; }; @@ -152,6 +161,10 @@ qcom,stream-id-range = <0x400 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc>; + interconnects = <&mmrt_virt MASTER_MDP_PORT0 + &mmrt_virt SLAVE_SNOC_BIMC_RT>, + <&bimc MASTER_AMPSS_M0 + &system_noc SLAVE_TCU>; qcom,active-only; qcom,iova-width = <36>; }; @@ -164,6 +177,10 @@ qcom,stream-id-range = <0x800 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc>; + interconnects = <&mmnrt_virt MASTER_CAMNOC_SF + &mmnrt_virt SLAVE_SNOC_BIMC_NRT>, + <&bimc MASTER_AMPSS_M0 + &system_noc SLAVE_TCU>; qcom,active-only; qcom,iova-width = <36>; }; From 0603f2a62c34f39ff07fb1bf76721f98d77d053c Mon Sep 17 00:00:00 2001 From: Sriram Dash Date: Mon, 7 Nov 2022 14:02:54 +0530 Subject: [PATCH 07/71] ARM: dts: qcom: Fix the min/max voltage level for L7A regulator Min request for lower voltage levels result in shutdown for system during bootup. Fix with proper values. Change-Id: Id87250d37465d9735be4ec446a50469a5f4eb079 --- qcom/lemans-4pmic-regulators.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/lemans-4pmic-regulators.dtsi b/qcom/lemans-4pmic-regulators.dtsi index fd73f348..56bb6e8d 100644 --- a/qcom/lemans-4pmic-regulators.dtsi +++ b/qcom/lemans-4pmic-regulators.dtsi @@ -386,8 +386,8 @@ pm8775_a_l7: regulator-pm8775_a-l7 { regulator-name = "pm8775_a_l7"; qcom,set = ; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <950000>; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; qcom,init-voltage = <880000>; qcom,init-mode = ; From 7ec81df6cac32b358b2a68ec950c62a22b3cd581 Mon Sep 17 00:00:00 2001 From: Sriram Dash Date: Mon, 7 Nov 2022 14:06:55 +0530 Subject: [PATCH 08/71] ARM: dts: qcom: Make L7A always ON regulator Make the L7A regulator always ON. Unvoting the regulator results in system shutdown. Change-Id: I3707192529ee6d8f9333314e61370b0a56cb3ee4 --- qcom/lemans-4pmic-regulators.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lemans-4pmic-regulators.dtsi b/qcom/lemans-4pmic-regulators.dtsi index 56bb6e8d..2da37d95 100644 --- a/qcom/lemans-4pmic-regulators.dtsi +++ b/qcom/lemans-4pmic-regulators.dtsi @@ -388,6 +388,7 @@ qcom,set = ; regulator-min-microvolt = <830000>; regulator-max-microvolt = <920000>; + regulator-always-on; qcom,init-voltage = <880000>; qcom,init-mode = ; From dd4b5dc2c07ef77b6596c4cdcb7511431508cae7 Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Wed, 2 Nov 2022 18:07:30 +0530 Subject: [PATCH 09/71] ARM: dts: msm: Add gold and silver mask for high/low load Add gold and silver cluster mask for High/Low load data for ufs. Change-Id: I15c0b51cf95963655c5eaab1b817816b002b26fc --- qcom/khaje.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index e9e96265..eb633c12 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -2704,6 +2704,9 @@ phys = <&ufsphy_mem>; phy-names = "ufsphy"; + qcom,prime-mask = <0x80>; + qcom,silver-mask = <0x0f>; + limit-rx-hs-gear = <3>; limit-tx-hs-gear = <3>; lanes-per-direction = <2>; From a11608c8574dd21bf64d031761f1575232a3616d Mon Sep 17 00:00:00 2001 From: Suraj Jaiswal Date: Thu, 24 Sep 2020 16:33:58 +0530 Subject: [PATCH 10/71] ARM: dts: msm: STMMAC changes for SA8195 Add support for STMMAC in SA8195 dts. Change-Id: Idd79ff6b9eeb0e10dbf6550a8d44f546ed700585 --- qcom/sa8195p-adp-common.dtsi | 141 +++++++++++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) diff --git a/qcom/sa8195p-adp-common.dtsi b/qcom/sa8195p-adp-common.dtsi index db0223b0..1d064c79 100644 --- a/qcom/sa8195p-adp-common.dtsi +++ b/qcom/sa8195p-adp-common.dtsi @@ -1,5 +1,146 @@ #include +#include &qupv3_se12_2uart { status = "ok"; }; + +&soc { + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xC>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-sp; + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3E800>; + snps,low_credit = <0xFFC18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3E800>; + snps,low_credit = <0xFFC18000>; + }; + }; + + ethqos_hw: qcom,ethernet@00020000 { + compatible = "qcom,stmmac-ethqos", "snps,dwmac-4.20a"; + qcom,arm-smmu; + emac-core-version = <0x20010001>; + reg = <0x20000 0x10000>, + <0x36000 0x100>, + <0x3D00000 0x300000>; + reg-names = "stmmaceth", "rgmii","tlmm-central-base"; + clocks = <&gcc GCC_EMAC_AXI_CLK>, + <&gcc GCC_EMAC_SLV_AHB_CLK>, + <&gcc GCC_EMAC_PTP_CLK>, + <&gcc GCC_EMAC_RGMII_CLK>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; + snps,ptp-ref-clk-rate = <250000000>; + snps,ptp-req-clk-rate = <96000000>; + interrupts-extended = <&intc 0 689 4>, <&intc 0 700 4>, + <&tlmm 124 2>; + interrupt-names = "macirq", "eth_lpi", + "phy-intr"; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <20480>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,reset-gpios = <&tlmm 79 GPIO_ACTIVE_HIGH>; + qcom,phy-intr-redirect = <&tlmm 124 GPIO_ACTIVE_LOW>; + gdsc_emac-supply = <&emac_gdsc>; + + pinctrl-names = "dev-emac-mdc", + "dev-emac-mdio", + "dev-emac-rgmii_txd0_state", + "dev-emac-rgmii_txd1_state", + "dev-emac-rgmii_txd2_state", + "dev-emac-rgmii_txd3_state", + "dev-emac-rgmii_txc_state", + "dev-emac-rgmii_tx_ctl_state", + "dev-emac-rgmii_rxd0_state", + "dev-emac-rgmii_rxd1_state", + "dev-emac-rgmii_rxd2_state", + "dev-emac-rgmii_rxd3_state", + "dev-emac-rgmii_rxc_state", + "dev-emac-rgmii_rx_ctl_state", + "dev-emac-phy_intr", + "dev-emac-phy_reset_state", + "dev-emac_pin_pps_0"; + + pinctrl-0 = <&emac_mdc>; + pinctrl-1 = <&emac_mdio>; + + pinctrl-2 = <&emac_rgmii_txd0>; + pinctrl-3 = <&emac_rgmii_txd1>; + pinctrl-4 = <&emac_rgmii_txd2>; + pinctrl-5 = <&emac_rgmii_txd3>; + pinctrl-6 = <&emac_rgmii_txc>; + pinctrl-7 = <&emac_rgmii_tx_ctl>; + + pinctrl-8 = <&emac_rgmii_rxd0>; + pinctrl-9 = <&emac_rgmii_rxd1>; + pinctrl-10 = <&emac_rgmii_rxd2>; + pinctrl-11 = <&emac_rgmii_rxd3>; + pinctrl-12 = <&emac_rgmii_rxc>; + pinctrl-13 = <&emac_rgmii_rx_ctl>; + + pinctrl-14 = <&emac_phy_intr>; + pinctrl-15 = <&emac_phy_reset_state>; + pinctrl-16 = <&emac_pin_pps_0>; + + snps,reset-delays-us = <0 11000 70000>; + phy-mode = "rgmii"; + eth-c22-mdio-probe; + ethqos_emb_smmu: ethqos_emb_smmu { + compatible = "qcom,emac-smmu-embedded"; + iommus = <&apps_smmu 0x7C0 0x0>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>; + }; + }; +}; From d150540df1829b0e9f9ab09fd743084e792cfa0a Mon Sep 17 00:00:00 2001 From: Mohana Basava Tejesh Reddy Mareddy Date: Wed, 26 Oct 2022 12:15:12 -0700 Subject: [PATCH 11/71] dt-bindings: msm: mhi-dev: correct ipa property name Correcting use-ipa-software-channel property name Change-Id: Ib6e238383cfa445bd92499d6cadef35a42e504d1 --- bindings/msm_mhi_dev.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bindings/msm_mhi_dev.txt b/bindings/msm_mhi_dev.txt index c46a176a..52d20dde 100644 --- a/bindings/msm_mhi_dev.txt +++ b/bindings/msm_mhi_dev.txt @@ -20,7 +20,7 @@ Required properties: - qcom,mhi-version: MHI specification version supported by the device. Optional property: - - qcom,use-ipa-software-channel: If property is present use IPA hardware + - qcom,use-mhi-dma-software-channel: If property is present use IPA hardware accelerated path for MHI software channel data transfers between host and device. - qcom,mhi-config-iatu: If property is present map the control and data region From edd8412c2f8b1eb43636aaa9bfcdb9ca210bfb0f Mon Sep 17 00:00:00 2001 From: Vito Wang Date: Tue, 1 Nov 2022 11:27:34 +0800 Subject: [PATCH 12/71] ARM: dts: msm: Add kalama_le-overlays for kalama LE Add kalama_le-overlays config for kalama LE when installing dtbs. Change-Id: I11cd3c15808e90fb1bfad9e1f4c3277431ba679c --- qcom/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/Makefile b/qcom/Makefile index e8d09d92..98ad754d 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -71,6 +71,7 @@ kalama-dtb-$(CONFIG_ARCH_KALAMA) += \ $(call add-overlays, $(KALAMA_BOARDS) $(NOAPQ_KALAMA_BOARDS),$(KALAMA_BASE_DTB))\ $(call add-overlays, $(KALAMA_BOARDS) $(APQ_KALAMA_BOARDS),$(KALAMA_APQ_BASE_DTB)) kalama-overlays-dtb-$(CONFIG_ARCH_KALAMA) += $(KALAMA_BOARDS) $(NOAPQ_KALAMA_BOARDS) $(KALAMA_BASE_DTB) $(KALAMA_APQ_BASE_DTB) +kalama_le-overlays-dtb-$(CONFIG_ARCH_KALAMA) += $(KALAMA_BOARDS) $(NOAPQ_KALAMA_BOARDS) $(KALAMA_BASE_DTB) $(KALAMA_APQ_BASE_DTB) dtb-y += $(kalama-dtb-y) KHAJE_BASE_DTB += khaje.dtb khajep.dtb khajeq.dtb khajeg.dtb From fe2c1c62756effd24826d83a43653b39d69ae0d5 Mon Sep 17 00:00:00 2001 From: Adithya Naga Sai Tirumanisetti Date: Tue, 8 Nov 2022 09:32:05 +0530 Subject: [PATCH 13/71] ARM: dts: qcom: Add HS-I2S Device tree support on SA8195 adding device node for HS-I2S driver Change-Id: Iecb4ede108ba06ad4619deaab8b71bc0c1bdc330 --- qcom/sa8195p.dtsi | 102 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 101 insertions(+), 1 deletion(-) diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index e381c9a9..a4ad019f 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -19,10 +19,110 @@ #size-cells = <1>; read-only; ranges; - gpu_speed_bin: gpu_speed_bin@4002 { reg = <0x4002 0x2>; bits = <4 8>; + }; + }; + + hsi2s: qcom,hsi2s { + compatible = "qcom,sa8195-hsi2s", "qcom,hsi2s"; + number-of-interfaces = <3>; + reg = <0x172C0000 0x28000>, + <0x17080000 0xE000>; + reg-names = "lpa_if", "lpass_tcsr"; + interrupts = ; + number-of-rate-detectors = <2>; + rate-detector-interfaces = <0 1>; + iommus = <&apps_smmu 0x1B5C 0x1>, + <&apps_smmu 0x1B5E 0x0>; + qcom,iommu-dma-addr-pool = <0x0 0xFFFFFFFF>; + + sdr0: qcom,hs0_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs1_i2s_mclk_active &hs1_i2s_sck_active + &hs1_i2s_ws_active &hs1_i2s_data0_active + &hs1_i2s_data1_active>; + pinctrl-1 = <&hs1_i2s_mclk_sleep &hs1_i2s_sck_sleep + &hs1_i2s_ws_sleep &hs1_i2s_data0_sleep + &hs1_i2s_data1_sleep>; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; + }; + + sdr1: qcom,hs1_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs2_i2s_mclk_active &hs2_i2s_sck_active + &hs2_i2s_ws_active &hs2_i2s_data0_active + &hs2_i2s_data1_active>; + pinctrl-1 = <&hs2_i2s_mclk_sleep &hs2_i2s_sck_sleep + &hs2_i2s_ws_sleep &hs2_i2s_data0_sleep + &hs2_i2s_data1_sleep>; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; + }; + + sdr2: qcom,hs2_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <2>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs3_i2s_mclk_active &hs3_i2s_sck_active + &hs3_i2s_ws_active &hs3_i2s_data0_active + &hs3_i2s_data1_active>; + pinctrl-1 = <&hs3_i2s_mclk_sleep &hs3_i2s_sck_sleep + &hs3_i2s_ws_sleep &hs3_i2s_data0_sleep + &hs3_i2s_data1_sleep>; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; }; }; }; From ad7a8692a8258e08b0615e5e1a967e6a6aae5905 Mon Sep 17 00:00:00 2001 From: kamasali Satyanarayan Date: Wed, 21 Sep 2022 17:16:04 +0530 Subject: [PATCH 14/71] ARM: dts: msm: Add bus voting and pm-qos for khaje Add bus voting and pm-qos for khaje. Change-Id: Ie0df75e9fae5dd48de2415c9a2f23c78f0c7dae7 --- qcom/khaje.dtsi | 132 +++++++++++++++++++----------------------------- 1 file changed, 53 insertions(+), 79 deletions(-) diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index e9e96265..e0e8b5fd 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -2508,6 +2508,22 @@ }; }; + sdhc1_opp_table: sdhc1-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <250000 133320>; + opp-avg-kBps = <104000 0>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-peak-kBps = <800000 300000>; + opp-avg-kBps = <400000 0>; + }; + }; + sdhc_1: sdhci@4744000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x4744000 0x1000>, <0x4745000 0x1000>, @@ -2536,14 +2552,6 @@ mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; - /* PM QoS */ - qcom,pm-qos-irq-type = "affine_irq"; - qcom,pm-qos-irq-latency = <26 26>; - qcom,pm-qos-cpu-groups = <0x0f 0xf0>; - - qcom,pm-qos-cmdq-latency-us = <26 26>, <26 26>; - qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>; - clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_ICE_CORE_CLK>; @@ -2554,38 +2562,7 @@ interconnects = <&system_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>, <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_1>; interconnect-names = "sdhc-ddr","cpu-sdhc"; - qcom,msm-bus,name = "sdhc1"; - qcom,msm-bus,num-cases = <9>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - /* No vote */ - <0 0>, <0 0>, - /* 400 KB/s*/ - <1046 1600>, - <1600 1600>, - /* 20 MB/s */ - <20480 80000>, - <80000 80000>, - /* 25 MB/s */ - <25600 250000>, - <50000 133320>, - /* 50 MB/s */ - <51200 250000>, - <65000 133320>, - /* 100 MB/s */ - <102400 250000>, - <65000 133320>, - /* 200 MB/s */ - <204800 800000>, - <200000 300000>, - /* 400 MB/s */ - <204800 800000>, - <200000 300000>, - /* Max. bandwidth */ - <1338562 4096000>, - <1338562 4096000>; - qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 - 100750000 200000000 400000000 4294967295>; + operating-points-v2 = <&sdhc1_opp_table>; /* Add support for gcc hw reset */ resets = <&gcc GCC_SDCC1_BCR>; @@ -2597,6 +2574,31 @@ qcom,iommu-dma = "fastmap"; status = "disabled"; + qos0 { + mask = <0xf0>; + vote = <44>; + }; + + qos1 { + mask = <0x0f>; + vote = <44>; + }; + }; + + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <250000 133320>; + opp-avg-kBps = <50000 0>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + opp-peak-kBps = <800000 300000>; + opp-avg-kBps = <104000 0>; + }; }; sdhc_2: sdhci@4784000 { @@ -2614,13 +2616,6 @@ no-mmc; qcom,restore-after-cx-collapse; - /* PM QoS */ - qcom,pm-qos-irq-type = "affine_irq"; - qcom,pm-qos-irq-latency = <26 26>; - - qcom,pm-qos-cpu-groups = <0x0f 0xf0>; - qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>; clock-names = "iface", "core"; @@ -2628,38 +2623,7 @@ interconnects = <&system_noc MASTER_SDCC_2 &bimc SLAVE_EBI_CH0>, <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_2>; interconnect-names = "sdhc-ddr","cpu-sdhc"; - - qcom,msm-bus,name = "sdhc2"; - qcom,msm-bus,num-cases = <8>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - /* No vote */ - <0 0>, <0 0>, - /* 400 KB/s*/ - <1046 3200>, - <1600 1600>, - /* 20 MB/s */ - <52286 250000>, - <80000 133320>, - /* 25 MB/s */ - <65360 250000>, - <100000 133320>, - /* 50 MB/s */ - <130718 250000>, - <133320 133320>, - /* 100 MB/s */ - <261438 250000>, - <150000 133320>, - /* 200 MB/s */ - <261438 800000>, - <300000 300000>, - /* Max. bandwidth */ - <1338562 4096000>, - <1338562 4096000>; - qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 - 100750000 200000000 4294967295>; - - qcom,devfreq,freq-table = <50000000 202000000>; + operating-points-v2 = <&sdhc2_opp_table>; /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; @@ -2669,6 +2633,16 @@ qcom,iommu-dma = "fastmap"; status = "disabled"; + + qos0 { + mask = <0xf0>; + vote = <44>; + }; + + qos1 { + mask = <0x0f>; + vote = <44>; + }; }; ufsphy_mem: ufsphy_mem@4807000 { From 841fde987fd57f2b5b6a3c6db0fe4fb012bfa1b6 Mon Sep 17 00:00:00 2001 From: Ping Li Date: Mon, 7 Nov 2022 16:19:07 -0800 Subject: [PATCH 15/71] ARM: dts: msm: add feature enabler UID to qtee config on kalama-vm This change adds feature enabler UID to qtee config on kalama-vm. Change-Id: I934960a2ceb75505f713a01fe4b97a2c47e195a0 --- qcom/kalama-vm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/kalama-vm.dtsi b/qcom/kalama-vm.dtsi index 8c68c186..993c89e7 100644 --- a/qcom/kalama-vm.dtsi +++ b/qcom/kalama-vm.dtsi @@ -106,7 +106,7 @@ vendor = "QTI"; image-name = "qcom,trustedvm"; qcom,pasid = <0x0 0x1c>; - qcom,qtee-config-info = "p=39,77,78,7C,8F,97,159,199,47E,7F1;"; + qcom,qtee-config-info = "p=39,77,78,7C,8F,97,FE,159,199,47E,7F1;"; qcom,secdomain-ids = <45>; qcom,primary-vm-index = <0>; vm-uri = "vmuid/trusted-ui"; From 6cc5300eef3408ed10407ec0c16ccf8252317ade Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Thu, 20 Oct 2022 10:58:56 +0530 Subject: [PATCH 16/71] ARM: dts: msm: Add kernel command line ftrace_dump_on_oops Add kernel command line arg ftrace_dump_on_oops for neo. This kernel command line will be used to dump Ftraces to KFTRACE buffers in minidump. Change-Id: I1c90c979d9ac235547161a54e9a0a01fc4b14084 --- qcom/khaje.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index e9e96265..0e67dcd7 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -587,7 +587,7 @@ }; chosen { - bootargs = "lpm_levels.sleep_disabled=1 console=ttyMSM0,115200n8 msm_rtb.filter=0x237 service_locator.enable=1 swiotlb=2048 loop.max_part=7 cpufreq.default_governor=performance rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off export_pmu_events movable_node"; + bootargs = "lpm_levels.sleep_disabled=1 console=ttyMSM0,115200n8 msm_rtb.filter=0x237 service_locator.enable=1 swiotlb=2048 loop.max_part=7 cpufreq.default_governor=performance rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off export_pmu_events movable_node ftrace_dump_on_oops"; }; soc: soc { }; From 15b5484eab5ddf2fd0cda4b8694c3d183ddd06dc Mon Sep 17 00:00:00 2001 From: Yadu MG Date: Fri, 30 Sep 2022 01:34:07 +0530 Subject: [PATCH 17/71] ARM: dts: qcom: Add dt node for adsp remoteproc on Lemans Add remoteproc device node for ADSP subsystem on Lemans target. Change-Id: Ib51f304d41746643f8f9f45c4e506f5e284b380d --- qcom/lemans.dtsi | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index d69a1497..5e4706fb 100644 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -302,7 +303,7 @@ reg = <0x0 0x95200000 0x0 0x500000>; }; - pil_adsp_mem: pil_adsp_region@95c00000 { + rproc_adsp_mem: rproc_adsp_region@95c00000 { no-map; reg = <0x0 0x95c00000 0x0 0x1e00000>; }; @@ -1040,6 +1041,42 @@ compatible = "qcom,cpu-vendor-hooks"; }; + adsp_pas: remoteproc-adsp@3000000 { + compatible = "qcom,lemans-adsp-pas"; + reg = <0x3000000 0x00100>; + status = "ok"; + + memory-region = <&rproc_adsp_mem>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + vdd_cx-supply = <&VDD_LPI_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_mx-supply = <&VDD_LPI_MX_LEVEL>; + qcom,vdd_mx-uV-uA = ; + reg-names = "cx","mx"; + + /* Inputs from lpass */ + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack"; + + qcom,qmp = <&aoss_qmp>; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + }; + spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0x1100>, From 8bd5387d4c8ff3dc2fe505f3a8a1924ff6784c99 Mon Sep 17 00:00:00 2001 From: Yadu MG Date: Fri, 30 Sep 2022 01:46:39 +0530 Subject: [PATCH 18/71] ARM: dts: qcom: Add dt node for cdsp remoteproc on Lemans Add remoteproc device node for CDSP subsystem on Lemans target. Change-Id: Ia903f4e02c9198dbc0d97bbf70b784e104869577 --- qcom/lemans.dtsi | 43 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index 5e4706fb..6723f28a 100644 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -318,7 +318,7 @@ reg = <0x0 0x99900000 0x0 0x1e00000>; }; - pil_cdsp0_mem: pil_cdsp0_region@9b800000 { + rproc_cdsp_mem: rproc_cdsp_region@9b800000 { no-map; reg = <0x0 0x9b800000 0x0 0x1e00000>; }; @@ -1077,6 +1077,47 @@ qcom,smem-state-names = "stop"; }; + cdsp_pas: remoteproc-cdsp@26300000 { + compatible = "qcom,lemans-cdsp-pas"; + reg = <0x26300000 0x10000>; + status = "ok"; + + memory-region = <&rproc_cdsp_mem>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_MXC_LEVEL>; + mx-uV-uA = ; + nsp0-supply = <&VDD_NSP_0_LEVEL>; + nsp0-uV-uA = ; + reg-names = "cx","mx","nsp0"; + + interconnects = <&nspa_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; + interconnect-names = "crypto_ddr"; + + /* Inputs from turing */ + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack"; + + qcom,qmp = <&aoss_qmp>; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + }; + spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0x1100>, From a1faf61687df8224d92e5db562c75ef5920699b6 Mon Sep 17 00:00:00 2001 From: Adithya Naga Sai Tirumanisetti Date: Tue, 8 Nov 2022 09:34:47 +0530 Subject: [PATCH 19/71] ARM: dts: qcom: Add qti-can device tree node for 8195 Add qti-can device node for sa8195 Change-Id: I6be225567d71dd0db93236db7c44499055577b68 --- qcom/sa8195p-adp-common.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/qcom/sa8195p-adp-common.dtsi b/qcom/sa8195p-adp-common.dtsi index db0223b0..5b136c0e 100644 --- a/qcom/sa8195p-adp-common.dtsi +++ b/qcom/sa8195p-adp-common.dtsi @@ -1,5 +1,30 @@ #include +&qupv3_3 { + status = "ok"; +}; + + +&qupv3_se0_spi { +status = "ok"; + +#address-cells = <1>; +#size-cells = <0>; + + can-controller@0 { + compatible = "qcom,nxp,mpc5746c"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <38 0>; + spi-max-frequency = <5000000>; + qcom,clk-freq-mhz = <40000000>; + qcom,max-can-channels = <1>; + qcom,bits-per-word = <8>; + qcom,support-can-fd; + }; +}; + + &qupv3_se12_2uart { status = "ok"; }; From 4ef4853f6c651ebf569231a75d15d8a7fe3fe411 Mon Sep 17 00:00:00 2001 From: Yao Zhao Date: Mon, 17 Oct 2022 08:52:56 +0530 Subject: [PATCH 20/71] dt-bindings: llcc: add Kona llcc bindings Add Kona llcc bindings. Change-Id: I1327a92dd3e8dfd24728f1a565bfc8f2226da631 --- bindings/arm/msm/qcom,llcc.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt index 9b82f696..6c035229 100644 --- a/bindings/arm/msm/qcom,llcc.txt +++ b/bindings/arm/msm/qcom,llcc.txt @@ -15,7 +15,8 @@ Properties: "qcom,lahaina-llcc" or "qcom,shima-llcc" or "qcom,waipio-llcc" or "qcom,sdxlemur-llcc" or "qcom,diwali-llcc" or "qcom,kalama-llcc" or "qcom,cinder-llcc" - or "qcom,sdmshrike-llcc" or "qcom,lemans-llcc". + or "qcom,sdmshrike-llcc" or "qcom,lemans-llcc" + or "qcom,kona-llcc". "qcom,llcc-v2" must be appended for V2 hardware or "qcom,llcc-v21" for V2.1 or "qcom,llcc-v31" for V3.1 or "qcom,llcc-v41" for V4.1. From 7ad3ea5062cff03acd8ab2a2f3091e9e2e018004 Mon Sep 17 00:00:00 2001 From: Chetan C R Date: Fri, 4 Nov 2022 18:12:32 +0530 Subject: [PATCH 21/71] ARM: dts: qcom: Add clock and interconnect for qrng driver Add clock and interconnect property for qrng node on Khaje targets. Change-Id: Ia38d28e955478a3435d8ff90260eb4e43ad5562a --- qcom/khaje.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index e9e96265..9ffff253 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -1955,9 +1955,9 @@ qcom,msm-rng-iface-clk; qcom,no-qrng-config; interconnect-names = "data_path"; - interconnects = <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_HWKM_CORE>; + interconnects = <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_PRNG>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "km_clk_src"; - clocks = <&rpmcc RPM_SMD_HWKM_CLK>; }; qcom_tzlog: tz-log@c125720 { From 053318ad5f86effe5e63074489dde7c06100d05e Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Thu, 3 Nov 2022 11:38:04 +0530 Subject: [PATCH 22/71] ARM: dts: msm: Fix wdog interrupt of LPASS on SM8150 On newer kernels PDC interrupt can only be requested if its actually routed through PDC HW. Update the LPASS subsystem interrupt to use intc interrupts when they are direct interrupts at GIC and only use PDC if it has routing to PDC HW. Change-Id: Ie60515cd51e55ce0772d5d2c89a603b63ba44545 --- qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 77f81a81..0966bfd4 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1482,7 +1482,7 @@ memory-region = <&rproc_adsp_mem>; /* Inputs from ssc */ - interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <&adsp_smp2p_in 0 0>, <&adsp_smp2p_in 2 0>, <&adsp_smp2p_in 1 0>, From 3fb564d6300916cbfcd17f9f7b33404db27e348e Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Wed, 9 Nov 2022 10:14:39 +0530 Subject: [PATCH 23/71] ARM: dts: msm: Remove dma-coherent property Remove dma-coherent property from gpi node to avoid smmu crash during SPI data transfer. In 5.4 also, dma-coherent property is not used. Change-Id: Ic39e17728c2620d1bef1ed355dbefa5f2a7a7830 --- qcom/monaco-qupv3.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/monaco-qupv3.dtsi b/qcom/monaco-qupv3.dtsi index 4abcfea1..5e6684e6 100644 --- a/qcom/monaco-qupv3.dtsi +++ b/qcom/monaco-qupv3.dtsi @@ -34,7 +34,6 @@ qcom,ev-factor = <2>; qcom,iommu-dma-addr-pool = <0x100000 0x100000>; qcom,gpi-ee-offset = <0x10000>; - dma-coherent; status = "ok"; }; @@ -51,7 +50,6 @@ qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; - dma-coherent; ranges; status = "ok"; From e9c51fbcde25487d61bca24e750e9d6d20699f19 Mon Sep 17 00:00:00 2001 From: Yadu MG Date: Wed, 9 Nov 2022 12:29:42 +0530 Subject: [PATCH 24/71] ARM: dts: msm: Add LLCC device nodes for Lemans Add device nodes for Last level cache controller for Lemans target. Change-Id: I15641f24b18d1b85264a932955245fa1767b2549 --- qcom/lemans.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index d69a1497..8b4206ec 100644 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -668,6 +669,20 @@ #mbox-cells = <2>; }; + cache-controller@9200000 { + compatible = "qcom,lemans-llcc", "qcom,llcc-v31"; + reg = <0x9200000 0x580000> , <0x9a00000 0x80000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = ; + cap-based-alloc-and-pwr-collapse; + + llcc-perfmon { + compatible = "qcom,llcc-perfmon"; + clocks = <&aoss_qmp QDSS_CLK>; + clock-names = "qdss_clk"; + }; + }; + clocks { xo_board: xo_board { compatible = "fixed-clock"; From 6b5152e35ac18388aeeac3c112708a80d0052eed Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Mon, 26 Sep 2022 14:49:39 +0530 Subject: [PATCH 25/71] ARM: dts: msm: Add RPMh controlled PMIC regulators for sdxbaagha Add rpmh-regulator device nodes for the PMIC PMX35 regulators This ensures that consumers are able to modify the physical state of these PMIC regulators. Change-Id: I4a0f3872d3f481d5c37c21a78d8f77dab2790e49 --- qcom/sdxbaagha-regulators.dtsi | 365 +++++++++++++++++++++++++++++++++ 1 file changed, 365 insertions(+) create mode 100644 qcom/sdxbaagha-regulators.dtsi diff --git a/qcom/sdxbaagha-regulators.dtsi b/qcom/sdxbaagha-regulators.dtsi new file mode 100644 index 00000000..3671dbe3 --- /dev/null +++ b/qcom/sdxbaagha-regulators.dtsi @@ -0,0 +1,365 @@ +#include + +&apps_rsc_drv1 { + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "cx.lvl"; + proxy-supply = <&VDD_CX_LEVEL>; + + VDD_MODEM_LEVEL: + VDD_CX_LEVEL: S1A_LEVEL: + pmx35_s1_level: regulator-pmx35-s1-level { + regulator-name = "pmx35_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + + }; + + VDD_CX_LEVEL_AO: S1A_LEVEL_AO: + pmx35_s1_level_ao: regulator-pmx35-s1-level-ao { + regulator-name = "pmx35_s1_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mx.lvl"; + proxy-supply = <&VDD_MXA_LEVEL>; + + VDD_EBI_LEVEL: VDD_MXA_LEVEL: L1A_LEVEL: + pmx35_l1_level: regulator-pmx35-l1-level { + regulator-name = "pmx35_l1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_MXA_LEVEL_AO: L1A_LEVEL_AO: + pmx35_l1_level_ao: regulator-pmx35-l1-level-ao { + regulator-name = "pmx35_l1_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-mxclvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mxc.lvl"; + proxy-supply = <&VDD_MXC_LEVEL>; + + VDD_MXC_LEVEL: L2A_LEVEL: + pmx35_l2_level: regulator-pmx35-l2-level { + regulator-name = "pmx35_l2_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_MXC_LEVEL_AO: L2A_LEVEL_AO: + pmx35_l2_level_ao: regulator-pmx35-l2-level-ao { + regulator-name = "pmx35_l2_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldo3a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo3a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + + L3A: pmx35_l3: regulator-pmx35-l3 { + regulator-name = "pmx35_l3"; + qcom,set = ; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + qcom,init-voltage = <910000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldo4a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo4a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + + L4A: pmx35_l4: regulator-pmx35-l4 { + regulator-name = "pmx35_l4"; + qcom,set = ; + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + qcom,init-voltage = <620000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldo5a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo5a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + + L5A: pmx35_l5: regulator-pmx35-l5 { + regulator-name = "pmx35_l5"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldo6a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo6a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + + L6A: pmx35_l6: regulator-pmx35-l6 { + regulator-name = "pmx35_l6"; + qcom,set = ; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldo7a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo7a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + + L7A: pmx35_l7: regulator-pmx35-l7 { + regulator-name = "pmx35_l7"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldo8a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo8a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + + L8A: pmx35_l8: regulator-pmx35-l8 { + regulator-name = "pmx35_l8"; + qcom,set = ; + regulator-min-microvolt = <552000>; + regulator-max-microvolt = <904000>; + qcom,init-voltage = <552000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldo9a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo9a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + + L9A: pmx35_l9: regulator-pmx35-l9 { + regulator-name = "pmx35_l9"; + qcom,set = ; + regulator-min-microvolt = <960000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1128000>; + }; + }; + + rpmh-regulator-ldo10a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo10a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + + L10a: pmx35_l10: regulator-pmx35-l10 { + regulator-name = "pmx35_l10"; + qcom,set = ; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <3088000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldo11a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo11a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + + L11A: pmx35_l11: regulator-pmx35-l11 { + regulator-name = "pmx35_l11"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldo12a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo12a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + + L12A: pmx35_l12: regulator-pmx35-l12 { + regulator-name = "pmx35_l12"; + qcom,set = ; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldo13a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo13a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + + L13A: pmx35_l13: regulator-pmx35-l13 { + regulator-name = "pmx35_l13"; + qcom,set = ; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldo14a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo14a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + + L14A: pmx35_l14: regulator-pmx35-l14 { + regulator-name = "pmx35_l14"; + qcom,set = ; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldo15a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo15a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + + L15A: pmx35_l15: regulator-pmx35-l15 { + regulator-name = "pmx35_l15"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; +}; From fba4f9d3d0e5dbf6027b8cac5dced722a843cfee Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Wed, 9 Nov 2022 14:45:07 +0530 Subject: [PATCH 26/71] ARM: dts: msm: Add support for RPMHCC node for sdxbaagha Add support for RPMHCC node for sdxbaagha platform. While at it, use dummy clock controller for RPMHCC on RUMI platform. Change-Id: Id23dc91f9eceb5ec29322b71c08c579d04a126ef --- qcom/sdxbaagha-rumi.dtsi | 21 +++++++++++++++++++++ qcom/sdxbaagha.dtsi | 32 ++++++-------------------------- 2 files changed, 27 insertions(+), 26 deletions(-) diff --git a/qcom/sdxbaagha-rumi.dtsi b/qcom/sdxbaagha-rumi.dtsi index 48ff6d67..e3f70810 100644 --- a/qcom/sdxbaagha-rumi.dtsi +++ b/qcom/sdxbaagha-rumi.dtsi @@ -39,6 +39,22 @@ 0x0 0x4 0x9 0x14>; }; + + bi_tcxo: bi_tcxo { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <2>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; + + bi_tcxo_ao: bi_tcxo_ao { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <2>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; }; &qupv3_se3_2uart { @@ -63,3 +79,8 @@ &cpufreq_hw { clocks = <&bi_tcxo>, <&gcc GPLL0>; }; + +&rpmhcc { + compatible = "qcom,dummycc"; + clock-output-names = "rpmhcc_clocks"; +}; diff --git a/qcom/sdxbaagha.dtsi b/qcom/sdxbaagha.dtsi index 071966bd..ee346f23 100644 --- a/qcom/sdxbaagha.dtsi +++ b/qcom/sdxbaagha.dtsi @@ -262,6 +262,11 @@ , ; }; + + rpmhcc: clock-controller { + compatible = "qcom,sdxbaagha-rpmh-clk"; + #clock-cells = <1>; + }; }; }; @@ -380,7 +385,7 @@ clocks { xo_board: xo_board { compatible = "fixed-clock"; - clock-frequency = <19200000>; + clock-frequency = <38400000>; clock-output-names = "xo_board"; #clock-cells = <0>; }; @@ -400,31 +405,6 @@ }; }; - bi_tcxo: bi_tcxo { - compatible = "fixed-factor-clock"; - clocks = <&xo_board>; - clock-mult = <1>; - clock-div = <1>; - #clock-cells = <0>; - clock-output-names = "bi_tcxo"; - }; - - bi_tcxo_ao: bi_tcxo_ao { - compatible = "fixed-factor-clock"; - clocks = <&xo_board>; - clock-mult = <1>; - clock-div = <1>; - #clock-cells = <0>; - clock-output-names = "bi_tcxo_ao"; - }; - - rpmhcc: clock-controller { - compatible = "fixed-clock"; - clock-output-names = "rpmh_clocks"; - clock-frequency = <19200000>; - #clock-cells = <1>; - }; - gcc: clock-controller@80000 { compatible = "qcom,sdxbaagha-gcc", "syscon"; reg = <0x80000 0x1f4200>; From 1cdd2197d2c0fe2eac791dc9add144fc171e7f34 Mon Sep 17 00:00:00 2001 From: Yadu MG Date: Wed, 9 Nov 2022 14:59:21 +0530 Subject: [PATCH 27/71] ARM: dts: msm: Add secure display dma buf heap for Lemans Add secure display dma buf heap nodes for dma-buf heaps dirver on Lemans. Change-Id: I7d196ecea83a655d61b16d7ebc6505dee0be5637 --- qcom/lemans-dma-heaps.dtsi | 6 ++++++ qcom/lemans.dtsi | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/qcom/lemans-dma-heaps.dtsi b/qcom/lemans-dma-heaps.dtsi index 4bf89fdf..87f446c4 100644 --- a/qcom/lemans-dma-heaps.dtsi +++ b/qcom/lemans-dma-heaps.dtsi @@ -24,6 +24,12 @@ memory-region = <&non_secure_display_memory>; }; + qcom,secure_display { + qcom,dma-heap-name = "qcom,secure-display"; + qcom,dma-heap-type = ; + memory-region = <&secure_display_memory>; + }; + qcom,adsp { qcom,dma-heap-name = "qcom,adsp"; qcom,dma-heap-type = ; diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index d69a1497..96e6f72b 100644 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -422,6 +422,14 @@ alignment = <0x0 0x400000>; }; + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xA000000>; + }; + user_contig_mem: user_contig_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; From 27db297d084f4f51c0e90ed24abc1d730ffe6bed Mon Sep 17 00:00:00 2001 From: Khushal Bawankar Date: Thu, 20 Oct 2022 16:26:58 +0530 Subject: [PATCH 28/71] ARM: dts: qcom: Add pmic peripheral support for SCUBA Add pmic peripherals support for SCUBA. Change-Id: I73c56e37d28a0dfd2b6ddbdf27f01a8102fb8795 --- qcom/pm2250.dtsi | 378 ++++++++++++++++++++++++++++++++++++++ qcom/scuba_auto-pmic.dtsi | 152 +++++++++++++++ qcom/scuba_auto.dtsi | 22 +++ 3 files changed, 552 insertions(+) create mode 100644 qcom/pm2250.dtsi create mode 100644 qcom/scuba_auto-pmic.dtsi diff --git a/qcom/pm2250.dtsi b/qcom/pm2250.dtsi new file mode 100644 index 00000000..bcde3f10 --- /dev/null +++ b/qcom/pm2250.dtsi @@ -0,0 +1,378 @@ +#include +#include +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm2250@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + qcom,pon-dbc-delay = <15625>; + qcom,kpdpwr-sw-debounce; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up = <1>; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + qcom,pull-up = <1>; + linux,code = ; + }; + }; + + pm2250_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm2250_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pm2250_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5-lite"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel nodes */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vbat_sns { + reg = ; + label = "vbat_sns"; + qcom,pre-scaling = <1 3>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; + + chg_temp { + reg = ; + label = "chg_temp"; + qcom,pre-scaling = <1 1>; + }; + + bat_therm { + reg = ; + label = "bat_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_30k { + reg = ; + label = "bat_therm_30k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_400k { + reg = ; + label = "bat_therm_400k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + i_parallel { + reg = ; + label = "i_parallel"; + qcom,pre-scaling = <1 1>; + }; + + bat_id { + reg = ; + label = "bat_id"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + die_temp_s3 { + reg = ; + label = "die_temp_s3"; + qcom,pre-scaling = <1 3>; + qcom,scale-fn-type = ; + }; + }; + + pm2250_gpios: pinctrl@c000 { + compatible = "qcom,pm2250-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm2250_rtc: qcom,pm2250_rtc { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + + pm2250_qg: qpnp,qg { + compatible = "qcom,qpnp-qg-lite"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,vbatt-cutoff-mv = <3400>; + qcom,vbatt-low-mv = <3500>; + qcom,vbatt-low-cold-mv = <3800>; + qcom,vbatt-empty-mv = <3200>; + qcom,vbatt-empty-cold-mv = <3000>; + qcom,s3-entry-fifo-length = <2>; + + io-channels = <&pm2250_vadc ADC5_BAT_THERM_100K_PU>, + <&pm2250_vadc ADC5_BAT_ID_100K_PU>; + io-channel-names = "batt-therm", "batt-id"; + + qcom,qgauge@4800 { + status = "okay"; + reg = <0x4800>; + interrupts = + <0x0 0x48 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x48 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x48 0x5 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "qg-vbat-empty", + "qg-fifo-done", + "qg-good-ocv"; + }; + + qcom,qg-sdam@b600 { + status = "okay"; + reg = <0xb600>; + }; + }; + + pm2250_charger: qcom,qpnp-smblite { + compatible = "qcom,qpnp-smblite"; + #address-cells = <1>; + #size-cells = <0>; + #cooling-cells = <2>; + + qcom,chgr@1000 { + reg = <0x1000>; + interrupts = + <0x0 0x10 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "chgr-error", + "chg-state-change", + "buck-oc", + "vph-ov"; + }; + + qcom,batif@1200 { + reg = <0x1200>; + interrupts = + <0x0 0x12 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x4 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "bat-temp", + "bat-therm-or-id-missing", + "bat-low", + "bat-ov", + "bsm-active"; + }; + + qcom,usb@1300 { + reg = <0x1300>; + interrupts = + <0x0 0x13 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x13 0x6 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "usbin-plugin", + "usbin-collapse", + "usbin-uv", + "usbin-ov", + "usbin-gtvt", + "usbin-icl-change"; + }; + + qcom,typec@1500 { + reg = <0x1500>; + interrupts = + <0x0 0x15 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "typec-or-rid-detect-change", + "typec-vpd-detect", + "typec-cc-state-change", + "typec-vbus-change", + "typec-attach-detach", + "typec-legacy-cable-detect", + "typec-try-snk-src-detect"; + }; + + qcom,misc@1600 { + reg = <0x1600>; + interrupts = + <0x0 0x16 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x6 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "wdog-snarl", + "wdog-bark", + "aicl-fail", + "aicl-done", + "imp-trigger", + "all-chnl-cond-done", + "temp-change"; + }; + + qcom,schgm-flashlite@a600 { + reg = <0xa600>; + interrupts = + <0x0 0xa6 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0xa6 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0xa6 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0xa6 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "flash-state-change", + "ilim1-s1", + "ilim2-s2", + "vreg-ok"; + }; + }; + }; + + pm2250_1: qcom,pm2250@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm2250_vib: qcom,vibrator@5600 { + compatible = "qcom,qpnp-vibrator-ldo"; + reg = <0x5600>; + qcom,vib-ldo-volt-uv = <3000000>; + qcom,disable-overdrive; + }; + + pm2250_pwm1: qcom,pwms@bc00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbc00>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; + #pwm-cells = <2>; + }; + + pm2250_pwm2: qcom,pwms@bd00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbd00>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; + #pwm-cells = <2>; + }; + + pm2250_pwm3: qcom,pwms@be00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbe00>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; + #pwm-cells = <2>; + }; + }; +}; + +&thermal_zones { + pm2250-tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm2250_tz>; + + trips { + pm2250_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm2250_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/qcom/scuba_auto-pmic.dtsi b/qcom/scuba_auto-pmic.dtsi new file mode 100644 index 00000000..492c4e0b --- /dev/null +++ b/qcom/scuba_auto-pmic.dtsi @@ -0,0 +1,152 @@ +#include "pm2250.dtsi" + +&pm2250_gpios { + skin_therm { + skin_therm_default: skin_therm_default { + pins = "gpio5"; + bias-high-impedance; + }; + }; + + conn_therm { + conn_therm_default: conn_therm_default { + pins = "gpio6"; + bias-high-impedance; + }; + }; +}; + +&pm2250_vadc { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&conn_therm_default &skin_therm_default>; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm { + reg = ; + label = "pa_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + msm_therm { + reg = ; + label = "msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_therm { + reg = ; + label = "skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + /delete-node/ vbat_sns; + /delete-node/ usb_in_v_div_16; + /delete-node/ chg_temp; + /delete-node/ bat_therm; + /delete-node/ bat_therm_30k; + /delete-node/ bat_therm_400k; + /delete-node/ i_parallel; + /delete-node/ bat_id; + /delete-node/ die_temp_s3; +}; + +&spmi_bus { + qcom,pm2250@0 { + pm2250_adc_tm_iio: adc_tm@3400 { + compatible = "qcom,spmi-adc-tm5-iio"; + reg = <0x3400>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + xo_therm { + reg = <0>; + io-channels = <&pm2250_vadc ADC5_XO_THERM_100K_PU>; + }; + + pa_therm { + reg = <1>; + io-channels = <&pm2250_vadc ADC5_AMUX_THM1_100K_PU>; + }; + + quiet_therm { + reg = <2>; + io-channels = <&pm2250_vadc ADC5_AMUX_THM2_100K_PU>; + }; + + msm_therm { + reg = <3>; + io-channels = <&pm2250_vadc ADC5_AMUX_THM3_100K_PU>; + }; + + skin_therm { + reg = <4>; + io-channels = <&pm2250_vadc ADC5_GPIO3_100K_PU>; + }; + + conn_therm { + reg = <5>; + io-channels = <&pm2250_vadc ADC5_GPIO4_100K_PU>; + }; + }; + + /delete-node/ pm2250_qg; + /delete-node/ pm2250_charger; + }; + + qcom,pm2250@1 { + /delete-node/ pm2250_vib; + /delete-node/ pm2250_pwm1; + /delete-node/ pm2250_pwm2; + /delete-node/ pm2250_pwm3; + }; +}; + +&thermal_zones { + pm2250-tz { + trips { + trip0 { + temperature = <105000>; + }; + + trip1 { + temperature = <125000>; + }; + + trip2 { + temperature = <155000>; + }; + }; + }; +}; diff --git a/qcom/scuba_auto.dtsi b/qcom/scuba_auto.dtsi index 299b99b8..0f125493 100644 --- a/qcom/scuba_auto.dtsi +++ b/qcom/scuba_auto.dtsi @@ -973,6 +973,27 @@ #freq-domain-cells = <1>; }; + spmi_bus: qcom,spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x1c40000 0x1100>, + <0x1e00000 0x2000000>, + <0x3e00000 0x100000>, + <0x3f00000 0xa0000>, + <0x1c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + thermal_zones: thermal-zones { }; + clk_virt: interconnect@0 { compatible = "qcom,scuba-clk_virt"; qcom,keepalive; @@ -1091,6 +1112,7 @@ }; }; +#include "scuba_auto-pmic.dtsi" #include "pm2250-rpm-regulator.dtsi" #include "scuba-regulator.dtsi" #include "monaco-gdsc.dtsi" From b0aa9eb9928c8035e6d795da17c4ef916543e688 Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Tue, 25 Oct 2022 09:45:42 +0530 Subject: [PATCH 29/71] ARM: dts: msm: disable ssbd for khaje Disable ssbd mitigation for khaje soc. Change-Id: I1b5cefad194086ece1f31bb88578b618e92bcb7d --- qcom/khaje.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index 0e67dcd7..d7720001 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -587,7 +587,7 @@ }; chosen { - bootargs = "lpm_levels.sleep_disabled=1 console=ttyMSM0,115200n8 msm_rtb.filter=0x237 service_locator.enable=1 swiotlb=2048 loop.max_part=7 cpufreq.default_governor=performance rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off export_pmu_events movable_node ftrace_dump_on_oops"; + bootargs = "lpm_levels.sleep_disabled=1 console=ttyMSM0,115200n8 msm_rtb.filter=0x237 service_locator.enable=1 swiotlb=2048 loop.max_part=7 cpufreq.default_governor=performance rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off export_pmu_events movable_node ftrace_dump_on_oops ssbd=force-off"; }; soc: soc { }; From a08a82b3492e6f96557372a464693283c2507042 Mon Sep 17 00:00:00 2001 From: Srinivasarao Pathipati Date: Thu, 10 Nov 2022 18:13:05 +0530 Subject: [PATCH 30/71] ARM: dts: msm: remove clusters for Khaje remove clusters for 'core-hang-detect'. Change-Id: Ib7a08106eb0b8b4df5764995835ec1f045e85a48 --- qcom/khaje.dtsi | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index e9e96265..f81d912d 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -2126,24 +2126,13 @@ qcom,master-offset = <4096>; }; - qcom,chd_silver { + qcom,chd { compatible = "qcom,core-hang-detect"; - label = "silver"; - cluster-id = <0>; - qcom,threshold-arr = <0x0f1880b0 0x0f1980b0 - 0x0f1a80b0 0x0f1b80b0>; - qcom,config-arr = <0x0f1880b8 0x0f1980b8 - 0x0f1a80b8 0x0f1b80b8>; - }; - - qcom,chd_gold { - compatible = "qcom,core-hang-detect"; - label = "gold"; - cluster-id = <1>; - qcom,threshold-arr = <0x0f0880b0 0x0f0980b0 - 0x0f0a80b0 0x0f0b80b0>; - qcom,config-arr = <0x0f0880b8 0x0f0980b8 - 0x0f0a80b8 0x0f0b80b8>; + label = "core"; + qcom,threshold-arr = <0x0f1880b0 0x0f1980b0 0x0f1a80b0 0x0f1b80b0 + 0x0f0880b0 0x0f0980b0 0x0f0a80b0 0x0f0b80b0>; + qcom,config-arr = <0x0f1880b8 0x0f1980b8 0x0f1a80b8 0x0f1b80b8 + 0x0f0880b8 0x0f0980b8 0x0f0a80b8 0x0f0b80b8>; }; cluster-device0 { From b7b929468a79f590a0e5a46981dcc7023c805e20 Mon Sep 17 00:00:00 2001 From: jianshu Date: Thu, 10 Nov 2022 13:09:33 +0800 Subject: [PATCH 31/71] ARM: dts: msm: Add qseecom node for lemans.dtsi Add qseecom node and qtee_shmbridge node and disable FDE. Change-Id: Ida1aaf5f7c40c963a5e2bd1001b81a26e2da899d --- qcom/lemans.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index d69a1497..6b520029 100644 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -1246,6 +1246,27 @@ #mbox-cells = <1>; }; + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + qcom_qseecom: qseecom@d1800000 { + compatible = "qcom,qseecom"; + reg = <0xd1800000 0x3900000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + #qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + #qcom,disk-encrypt-pipe-pair = <2>; + #qcom,support-fde; + qcom,no-clock-support; + #qcom,fde-key-size; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,qsee-reentrancy-support = <2>; + }; + qcom,glinkpkt { compatible = "qcom,glinkpkt"; From 66a3d1588cd37b3adcbaf51ae55e29c9b4805850 Mon Sep 17 00:00:00 2001 From: Jeyaprabu J Date: Fri, 11 Nov 2022 16:56:11 +0530 Subject: [PATCH 32/71] ARM: dts: msm: Add compatible string for kgsl_smmu Add qcom,adreno-smmu compatible string for kgsl_smmu node. msm kgsl driver checks for this compatible string to enable per-process pagetables. Change-Id: I9713231d7f1a55c410078d078bfd20b5e42adf01 --- qcom/msm-arm-smmu-sdmshrike.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/msm-arm-smmu-sdmshrike.dtsi b/qcom/msm-arm-smmu-sdmshrike.dtsi index f63b387f..0cb085aa 100644 --- a/qcom/msm-arm-smmu-sdmshrike.dtsi +++ b/qcom/msm-arm-smmu-sdmshrike.dtsi @@ -2,7 +2,7 @@ &soc { kgsl_smmu: kgsl-smmu@2ca0000 { - compatible = "qcom,qsmmu-v500"; + compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu"; reg = <0x2ca0000 0x10000>, <0x2cc2000 0x20>; reg-names = "base", "tcu-base"; From 143c294c8a271e287436a157b2d236f05346a33c Mon Sep 17 00:00:00 2001 From: Singa Reddy Dasari Date: Fri, 11 Nov 2022 18:54:49 +0530 Subject: [PATCH 33/71] ARM: dts: msm: Add download-mode node to VM Add download-mode node to sm8150 DT for dump support. Change-Id: I76a3ec870e75268ac74ad17f222993e21a98c81d --- qcom/quin-vm-common.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index 85b07256..9d123dd1 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -219,6 +219,21 @@ compatible = "qcom,msm-imem-boot_stats"; reg = <0x6b0 0x20>; }; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; }; qcom,mpm2-sleep-counter@c221000 { From 5fdc75aca5c911693fc9a0432ecdb360b5d68a89 Mon Sep 17 00:00:00 2001 From: Yadu MG Date: Mon, 14 Nov 2022 08:47:16 +0530 Subject: [PATCH 34/71] dt-bindings: Add initial device tree for Lemans QAM Platform Add dt-bindings entries for Lemans QAM Platform. Change-Id: I3bae4eb3bc1e0876e2fd583c89cf8c428ec0e9ec --- bindings/arm/msm/msm.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index c8f05b54..57c1943f 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -187,6 +187,9 @@ Generic board variants: - CCARD device: compatible = "qcom,ccard" +- QAM device: + compatible = "qcom,qam" + Boards (SoC type + board variant): compatible = "qcom,apq8016" @@ -353,6 +356,8 @@ compatible = "qcom,lemans-rumi" compatible = "qcom,lemans-ivi" compatible = "qcom,lemans-ivi-adp-air" compatible = "qcom,lemans-ivi-adp-star" +compatible = "qcom,lemans-ivi-qam-star" compatible = "qcom,lemans-adas-high" compatible = "qcom,lemans-adas-high-adp-air" compatible = "qcom,lemans-adas-high-adp-star" +compatible = "qcom,lemans-adas-high-qam-star" From 3a4f48a4e05b0bb222938257383a76ab5eae559e Mon Sep 17 00:00:00 2001 From: Yadu MG Date: Mon, 14 Nov 2022 08:49:02 +0530 Subject: [PATCH 35/71] ARM: dts: msm: Add initial device tree for Lemans QAM platform Add initial device tree to support Lemans QAM platform. Change-Id: Ia03364a96b77048946a24b00a697646d47960db7 --- qcom/Makefile | 6 ++++-- qcom/lemans-adas-high-qam-star-overlay.dts | 12 ++++++++++++ qcom/lemans-adas-high-qam-star.dts | 10 ++++++++++ qcom/lemans-ivi-qam-star-overlay.dts | 12 ++++++++++++ qcom/lemans-ivi-qam-star.dts | 10 ++++++++++ qcom/lemans-qam-star.dtsi | 1 + 6 files changed, 49 insertions(+), 2 deletions(-) create mode 100644 qcom/lemans-adas-high-qam-star-overlay.dts create mode 100644 qcom/lemans-adas-high-qam-star.dts create mode 100644 qcom/lemans-ivi-qam-star-overlay.dts create mode 100644 qcom/lemans-ivi-qam-star.dts create mode 100644 qcom/lemans-qam-star.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 0eeb5937..5195e999 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -216,9 +216,11 @@ LEMANS_ADAS_HIGH_BASE_DTB += lemans-adas-high.dtb LEMANS_BOARDS += lemans-rumi-overlay.dtbo LEMANS_IVI_BOARDS += lemans-ivi-adp-air-overlay.dtbo \ - lemans-ivi-adp-star-overlay.dtbo + lemans-ivi-adp-star-overlay.dtbo \ + lemans-ivi-qam-star-overlay.dtbo LEMANS_ADAS_HIGH_BOARDS += lemans-adas-high-adp-air-overlay.dtbo \ - lemans-adas-high-adp-star-overlay.dtbo + lemans-adas-high-adp-star-overlay.dtbo \ + lemans-adas-high-qam-star-overlay.dtbo gen4auto-dtb-$(CONFIG_ARCH_LEMANS) += \ $(call add-overlays, $(LEMANS_IVI_BOARDS),$(LEMANS_IVI_BASE_DTB))\ diff --git a/qcom/lemans-adas-high-qam-star-overlay.dts b/qcom/lemans-adas-high-qam-star-overlay.dts new file mode 100644 index 00000000..d7d3a8c6 --- /dev/null +++ b/qcom/lemans-adas-high-qam-star-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "lemans-qam-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans ADAS HIGH QAM STAR"; + compatible = "qcom,lemans", "qcom,qam-star", "qcom,lemans-adas-high", "qcom,lemans-adas-high-qam-star"; + qcom,msm-id = <533 0x10000>; + qcom,board-id = <0x10025 0>; +}; + diff --git a/qcom/lemans-adas-high-qam-star.dts b/qcom/lemans-adas-high-qam-star.dts new file mode 100644 index 00000000..879abed8 --- /dev/null +++ b/qcom/lemans-adas-high-qam-star.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "lemans-adas-high.dtsi" +#include "lemans-qam-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans ADAS HIGH QAM STAR"; + compatible = "qcom,lemans", "qcom,qam-star", "qcom,lemans-adas-high", "qcom,lemans-adas-high-qam-star"; +}; + diff --git a/qcom/lemans-ivi-qam-star-overlay.dts b/qcom/lemans-ivi-qam-star-overlay.dts new file mode 100644 index 00000000..04dbe636 --- /dev/null +++ b/qcom/lemans-ivi-qam-star-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "lemans-qam-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans IVI QAM STAR"; + compatible = "qcom,lemans", "qcom,qam-star", "qcom,lemans-ivi", "qcom,lemans-ivi-qam-star"; + qcom,msm-id = <532 0x10000>; + qcom,board-id = <0x10025 0>; +}; + diff --git a/qcom/lemans-ivi-qam-star.dts b/qcom/lemans-ivi-qam-star.dts new file mode 100644 index 00000000..a77dd155 --- /dev/null +++ b/qcom/lemans-ivi-qam-star.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "lemans-ivi.dtsi" +#include "lemans-qam-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans IVI QAM STAR"; + compatible = "qcom,lemans", "qcom,qam-star", "qcom,lemans-ivi", "qcom,lemans-ivi-qam-star"; +}; + diff --git a/qcom/lemans-qam-star.dtsi b/qcom/lemans-qam-star.dtsi new file mode 100644 index 00000000..689bf563 --- /dev/null +++ b/qcom/lemans-qam-star.dtsi @@ -0,0 +1 @@ +#include "lemans-adp-common.dtsi" From 8dcba278134ca03e4e3418ca7e3df109c67f2a0f Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Mon, 14 Nov 2022 15:26:40 +0530 Subject: [PATCH 36/71] ARM: dts: msm: Update qseecom memory node for SM8150 Update qseecom node to allocate from a carveout. Change-Id: I0e4b301bccd238c7e61a949963f0a53ec2050b8c --- qcom/sm8150-dma-heaps.dtsi | 2 +- qcom/sm8150.dtsi | 6 ++---- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/qcom/sm8150-dma-heaps.dtsi b/qcom/sm8150-dma-heaps.dtsi index 3b46c5b0..c2a1bed8 100644 --- a/qcom/sm8150-dma-heaps.dtsi +++ b/qcom/sm8150-dma-heaps.dtsi @@ -31,7 +31,7 @@ qcom,qseecom { qcom,dma-heap-name = "qcom,qseecom"; - qcom,dma-heap-type = ; + qcom,dma-heap-type = ; memory-region = <&qseecom_mem>; }; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 77f81a81..db28dec9 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -456,10 +456,8 @@ qseecom_mem: qseecom_region { compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; + no-map; + reg = <0x0 0x9e400000 0x0 0x1400000>; }; cdsp_sec_mem: cdsp_sec_regions { From 01fae3453fe4e082c9a1c8fc83d189cca4b5a4f4 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Mon, 14 Nov 2022 15:29:54 +0530 Subject: [PATCH 37/71] ARM: dts: msm: Update qseecom memory node for SDMSHRIKE Update qseecom node to allocate from a carveout. Change-Id: I18030102800a6ab447fd30f56a6e7dc593f15339 --- qcom/sdmshrike-dma-heaps.dtsi | 2 +- qcom/sdmshrike.dtsi | 6 ++---- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/qcom/sdmshrike-dma-heaps.dtsi b/qcom/sdmshrike-dma-heaps.dtsi index 000e8954..a8e48717 100644 --- a/qcom/sdmshrike-dma-heaps.dtsi +++ b/qcom/sdmshrike-dma-heaps.dtsi @@ -24,7 +24,7 @@ qcom,qseecom { qcom,dma-heap-name = "qcom,qseecom"; - qcom,dma-heap-type = ; + qcom,dma-heap-type = ; memory-region = <&qseecom_mem>; }; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 7f3151c0..efbeaabb 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -459,10 +459,8 @@ qseecom_mem: qseecom_region { compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; + no-map; + reg = <0x0 0x9e400000 0x0 0x1400000>; }; From 22e7ee76f86fa26e6725b0c9ee67864ead10e50b Mon Sep 17 00:00:00 2001 From: Manoj Vishwanathan Date: Mon, 24 May 2021 16:47:31 -0700 Subject: [PATCH 38/71] dt-bindings: Add dt bindings for silent boot mode Add device tree bindings documentation support for silent mode. Change-Id: Id9d9b60cd0122a819cacb09403170e230554dc02 --- bindings/arm/msm/qcom,silent-boot.txt | 42 +++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 bindings/arm/msm/qcom,silent-boot.txt diff --git a/bindings/arm/msm/qcom,silent-boot.txt b/bindings/arm/msm/qcom,silent-boot.txt new file mode 100644 index 00000000..993ea6c6 --- /dev/null +++ b/bindings/arm/msm/qcom,silent-boot.txt @@ -0,0 +1,42 @@ +Power management Silent mode is a boot up mode with display and +audio disabled. This mode allows the platform to boot up the kernel +without enabling the UI, thereby masking the overall system boot latency. +Predominant usage could be seen in automotive applications where +boot latency is critical. +Top 2 use cases could be: +- One possible occasion for booting silently is when the driver approaches the + vehicle and based on the trigger by proximity sensor the vehicle does a remote + start before driver comes in the car. + +- Another might be if the system needs to run in the middle of + the night to perform updates. + +Add " pm_silentmode_kernel_state" viewable/editable via sysfs. + +Kernel driver to monitor external GPIO input to indicate boot into +kernel silent mode or not. This driver sets up the GPIO and links it +up with an IRQ that is rising/falling edge triggered. +On the GPIO rising edge, the IRQ thread is used to clear the sysfs +in the PM framework that holds the state of the pm_silentmode_kernel_state. +On the GPIO falling edge, the IRQ thread is used to set the sysfs +in the PM framework that holds the state of the pm_silentmode_kernel_state. + +The Device tree entry for silent mode can be used to register a GPIO +to the driver framework and use it to communicate to the Vehicle +interface processor. + +Required properties: + +- compatible: "qcom,silent-mode" +- qcom,silent-boot-gpio: GPIO needed HW interface from VIP to SoC +- interrupts: Assign interrupt that is dual edge triggered +- interrupt-names: Name of the interrupt under /proc/interrupt + +Example: + + qcom,silent-mode { + compatible = "qcom,silent-mode"; + qcom,silent-boot-gpio = <&pm8150_1_gpios 6 GPIO_ACTIVE_LOW>; + interrupts = < 0xc5 0 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "silent_pm8150_1_gpio6"; + }; From 77ef832588749fb8fa66b18d78b17a5a90136385 Mon Sep 17 00:00:00 2001 From: Sunish Nambayil Date: Mon, 19 Sep 2022 10:03:07 +0530 Subject: [PATCH 39/71] ARM: dts: msm: add silentboot reboot modes for SM8150 Add silent boot mode reboot reasons. Change-Id: Ia6a1452c563e1ef7ea6e2b008b86e4b064a93ef0 --- qcom/pm8150.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/pm8150.dtsi b/qcom/pm8150.dtsi index d0d24b5a..41e60e6d 100644 --- a/qcom/pm8150.dtsi +++ b/qcom/pm8150.dtsi @@ -36,6 +36,10 @@ mode-dm-verity-device-corrupted = <0x4>; mode-dm-verity-enforcing = <0x5>; mode-keys-clear = <0x6>; + mode-silent = <0xa>; + mode-nonsilent = <0xb>; + mode-forcedsilent = <0xc>; + mode-forcednonsilent = <0xd>; pon_pwrkey: pwrkey { compatible = "qcom,pm8941-pwrkey"; From df721d5c00883a9c676f6a9f23124c135ce13579 Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Thu, 3 Nov 2022 16:02:12 +0530 Subject: [PATCH 40/71] ARM: dts: msm: update msm-id to overlay device tree Update msm-id to overlay devicetree to avoid FDT merge issues. Change-Id: Ieb025b2b25a4a22a6dd1d2aba856c234f5c301b2 --- qcom/sa8155-vm-la-overlay.dts | 1 + qcom/sa8195-vm-la-overlay.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/qcom/sa8155-vm-la-overlay.dts b/qcom/sa8155-vm-la-overlay.dts index 1abe5787..b8a83882 100644 --- a/qcom/sa8155-vm-la-overlay.dts +++ b/qcom/sa8155-vm-la-overlay.dts @@ -5,5 +5,6 @@ / { model = "Qualcomm Technologies, Inc. SA8155 Single LA Guest Virtual Machine"; compatible = "qcom,sa8155", "qcom,quinvm"; + qcom,msm-id = <362 0x20000>; qcom,board-id = <0x0 0x1000001>; }; diff --git a/qcom/sa8195-vm-la-overlay.dts b/qcom/sa8195-vm-la-overlay.dts index 4c5bf46b..ab8fc5f4 100644 --- a/qcom/sa8195-vm-la-overlay.dts +++ b/qcom/sa8195-vm-la-overlay.dts @@ -8,5 +8,6 @@ model = "Qualcomm Technologies, Inc. SA8195 Single LA Virtual Machine"; compatible = "qcom,sa8195p", "qcom,quinvm"; qcom,pmic-name = "PM8195"; + qcom,msm-id = <405 0x20000>; qcom,board-id = <0 0x1000001>; }; From a18a95850c3597f350a206110ce257afce6a9796 Mon Sep 17 00:00:00 2001 From: Zou Shunxiang Date: Tue, 1 Nov 2022 18:02:07 +0800 Subject: [PATCH 41/71] ARM: dts: qcom: Add the APSS SMMU nodes for direwolf GVM Add the APSS SMMU nodes for the direwolf GVM platform to enable IOMMU control from the VM. Change-Id: Id08d765e4d47cbe0b115d71d8673d9b54ed696ac --- qcom/direwolf-vm.dtsi | 153 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 153 insertions(+) diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 82a270b1..6a792010 100644 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -6,6 +6,159 @@ qcom,msm-id = <460 0x10000>; }; +&soc { + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,handoff-smrs = <0xffff 0x0>; + qcom,multi-match-handoff-smr; + #global-interrupts = <2>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + dma_dev@0x0 { + compatible = "qcom,iommu-dma"; + memory-region = <&system_cma>; + }; +}; + ®ulator { virt_regulator { compatible = "virtio,device31"; From 9dca61242250f77e5b3970f1de8ec983a9bd59f8 Mon Sep 17 00:00:00 2001 From: Fei Yang Date: Tue, 8 Nov 2022 13:48:51 +0800 Subject: [PATCH 42/71] ARM: dts: msm: Add virtio_spmi node for direwolf vm Add virtio_spmi node for automotive vm on direwolf. Change-Id: I2115ff26fe5d693d06ad356f798c13b1b505235c --- qcom/direwolf-vm.dtsi | 2 ++ qcom/pm8540-vm.dtsi | 77 ++++++++++++++++++++++++++++++++++++++++ qcom/quin-vm-common.dtsi | 6 +++- 3 files changed, 84 insertions(+), 1 deletion(-) create mode 100644 qcom/pm8540-vm.dtsi diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 6a792010..78ac42b8 100644 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -270,3 +270,5 @@ }; }; }; + +#include "pm8540-vm.dtsi" diff --git a/qcom/pm8540-vm.dtsi b/qcom/pm8540-vm.dtsi new file mode 100644 index 00000000..483a3b82 --- /dev/null +++ b/qcom/pm8540-vm.dtsi @@ -0,0 +1,77 @@ +#include + +&spmi_bus { + + qcom,pm8540@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8540_1_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8540_1_rtc: qcom,pm8540_1_rtc { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + disable-alarm-wakeup; + }; + }; + + + qcom,pm8540@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8540_2_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,pm8540@8 { + compatible = "qcom,spmi-pmic"; + reg = <8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8540_3_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,pm8540@C { + compatible = "qcom,spmi-pmic"; + reg = <12 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8540_4_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index 85b07256..54ff81e6 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -227,7 +227,7 @@ clock-frequency = <32768>; }; - spmi_bus: virtio-spmi@1c800000 { + virtio-spmi@1c800000 { compatible = "virtio,mmio"; #address-cells = <1>; #size-cells = <1>; @@ -238,6 +238,10 @@ #interrupt-cells = <4>; cell-index = <0>; status = "okay"; + + spmi_bus: virt_spmi { + compatible = "virtio,device33"; + }; }; }; From 4c996f6ce6f0a2bb5e53c0b6995bf3722b9fbdd3 Mon Sep 17 00:00:00 2001 From: Balakrishna Godavarthi Date: Tue, 15 Nov 2022 10:25:55 +0530 Subject: [PATCH 43/71] ARM: dts: msm: Add support for BT control glink node This change add support to create device node for BT control glink node which used for communication between APPS and ADSP. Change-Id: I6448a56511681bc3239c72d2fdb181931427bffc --- qcom/kalama.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/kalama.dtsi b/qcom/kalama.dtsi index 30b8b4d4..d592845b 100644 --- a/qcom/kalama.dtsi +++ b/qcom/kalama.dtsi @@ -2582,7 +2582,7 @@ qcom,glinkpkt-ch-name = "DATA11"; qcom,glinkpkt-dev-name = "smd11"; }; - qcom,glinkpkt-btoip_control { + qcom,glinkpkt-xpan_control { qcom,glinkpkt-edge = "adsp"; qcom,glinkpkt-ch-name = "bt_cp_ctrl"; qcom,glinkpkt-dev-name = "bt_cp_ctrl"; From 496607611d2cdbe03e2476d8dd04187a7fd869c7 Mon Sep 17 00:00:00 2001 From: Meenu Raja Sundaram Date: Fri, 28 Oct 2022 17:56:29 +0530 Subject: [PATCH 44/71] ARM: dts: msm: Add glink support on adsp, cdsp0 Add glink node support for adsp and cdsp0 on lemans. Change-Id: I9996ec62255dd7543d939de7f5d2be16c1b2632a --- qcom/lemans.dtsi | 56 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index 15519e9e..aaf84221 100644 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -1098,6 +1098,34 @@ /* Outputs to lpass */ qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; + + glink_adsp: glink-edge { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "adsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + cpu-affinity = <1 2>; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + }; }; cdsp_pas: remoteproc-cdsp@26300000 { @@ -1139,6 +1167,34 @@ /* Outputs to turing */ qcom,smem-states = <&cdsp_smp2p_out 0>; qcom,smem-state-names = "stop"; + + glink_cdsp0: glink-edge { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "cdsp0_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "cdsp0"; + qcom,glink-label = "cdsp0"; + + qcom,cdsp0_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + }; }; spmi_bus: qcom,spmi@c440000 { From a6a47ab6f3ebe498f54ad90d7d4566b51dd8342e Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Tue, 15 Nov 2022 14:47:08 +0530 Subject: [PATCH 45/71] ARM: dts: msm: Add MVMSS clock for QoS programming for SDXPINN GCC_SYS_NOC_MVMSS_CLK clock node handle is needed for mvmss master qos programming. Change-Id: I3d43a600f271a6576e3b9b4a8a73c55869a54afc --- qcom/sdxpinn.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi index fc2cef49..3ae4812f 100644 --- a/qcom/sdxpinn.dtsi +++ b/qcom/sdxpinn.dtsi @@ -1407,6 +1407,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_SYS_NOC_MVMSS_CLK>; }; }; From f840480802134372c28b09f4b0ecec93535813f7 Mon Sep 17 00:00:00 2001 From: Naveen Kumar Goud Arepalli Date: Tue, 15 Nov 2022 18:22:56 +0530 Subject: [PATCH 46/71] ARM: dts: msm: Add sdcard support for SA8195 Add SD Card support for SA8195. Change-Id: Ic16f6bba9a7b68df7f020a5339451b460be43646 --- qcom/sa8195p.dtsi | 18 +++++++++++++ qcom/sdmshrike.dtsi | 63 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 81 insertions(+) diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index a4ad019f..fb46d767 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -132,6 +132,24 @@ status = "ok"; }; +&sdhc_2 { + vdd-supply = <&pm8195_1_l10>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8195_1_l2>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&pm8195_1_gpios 4 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4"; vdda-phy-supply = <&pm8195_3_l5>; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 7f3151c0..9b9a3f14 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -28,6 +28,7 @@ aliases { ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + mmc1 = &sdhc_2; /* SDC2 SD Card slot */ serial0 = &qupv3_se12_2uart; spi22 = &qupv3_se22_spi; i2c7 = &qupv3_se20_i2c; @@ -1574,6 +1575,68 @@ }; }; + + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <1600000 280000>; + opp-avg-kBps = <50000 0>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + opp-peak-kBps = <5600000 1500000>; + opp-avg-kBps = <104000 0>; + }; + }; + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + bus-width = <4>; + qcom,restore-after-cx-collapse; + + + iommus = <&apps_smmu 0x06A0 0x0>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + + interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + operating-points-v2 = <&sdhc2_opp_table>; + + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; + + qcom,devfreq,freq-table = <50000000 200000000>; + + status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <70>; + }; + + qos1 { + mask = <0xf0>; + vote = <70>; + }; + }; + ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>; /* PHY regs */ reg-names = "phy_mem"; From a2c4ad260867d310eb25a379db46b41043116226 Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Tue, 15 Nov 2022 10:18:21 +0530 Subject: [PATCH 47/71] ARM: dts: msm: Update PCIe RC0 PHY registers for QRD v102 QRD platform has ultrashort PCIe channel for RC0, update PHY settings for <5DB loss. Change-Id: Iee5dbae63cfccd4552b21c94901893020f1b2e0c --- qcom/kalama-qrd.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/qcom/kalama-qrd.dtsi b/qcom/kalama-qrd.dtsi index 400e9d0f..3b68e1d4 100644 --- a/qcom/kalama-qrd.dtsi +++ b/qcom/kalama-qrd.dtsi @@ -344,7 +344,7 @@ }; &pcie0 { - qcom,pcie-phy-ver = <101>; + qcom,pcie-phy-ver = <102>; qcom,phy-sequence = <0x0240 0x03 0x0 0x00c0 0x01 0x0 0x00cc 0x62 0x0 @@ -452,12 +452,12 @@ 0x060c 0x1d 0x0 0x0614 0x07 0x0 0x0620 0xc1 0x0 - 0x0368 0x0F 0x0 - 0x1180 0x8C 0x0 - 0x1980 0x8C 0x0 + 0x0368 0x0f 0x0 + 0x1180 0x8f 0x0 + 0x1980 0x8f 0x0 0x0120 0x40 0x0 - 0x0080 0x0A 0x0 - 0x0084 0x1A 0x0 + 0x0080 0x0a 0x0 + 0x0084 0x1a 0x0 0x0020 0x14 0x0 0x0024 0x34 0x0 0x0624 0x05 0x0 From 0e90823428ed01146cbb74dbf90186030da0b021 Mon Sep 17 00:00:00 2001 From: Chuanye Chai Date: Thu, 10 Nov 2022 10:18:37 +0800 Subject: [PATCH 48/71] ARM: dts: msm: Enable secure contiguous dma heap in 8195 Secure contiguous heap is used for secure video playback. Add bootargs commandline argument to enable secure contiguous dma heap as in 8155. Change-Id: Ib3456a83f367b7c154fb29254174d83b97dcb842 --- qcom/sdmshrike.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 7f3151c0..fe421617 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -335,7 +335,7 @@ }; chosen { - bootargs = "kpti=0 ssbd=force-off"; + bootargs = "kpti=0 ssbd=force-off qcom_dma_heaps.enable_bitstream_contig_heap=y"; }; firmware: firmware { From f8524b8f14e3735f52d136e65a97ad3ba1ccee97 Mon Sep 17 00:00:00 2001 From: Chuanye Chai Date: Tue, 15 Nov 2022 14:37:50 +0800 Subject: [PATCH 49/71] ARM: dts: msm: Enable secure buffer in lemans Secure buffer is used for the secure dmabuf heaps. Change-Id: I7585254e4f754e63e582ef1a033c7b58b46d295e --- qcom/lemans.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index 15519e9e..54d3ac19 100644 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -662,6 +662,11 @@ #interrupt-cells = <2>; }; + qcom,secure-buffer { + compatible = "qcom,secure-buffer"; + qcom,vmid-cp-camera-preview-ro; + }; + wdog: qcom,wdt@17c10000 { compatible = "qcom,msm-watchdog"; reg = <0x17c10000 0x1000>; From 389eb6cef325539959d2b61a91790762d31d5cee Mon Sep 17 00:00:00 2001 From: Chetan C R Date: Fri, 7 Oct 2022 14:28:36 +0530 Subject: [PATCH 50/71] ARM: dts: qcom: Add interconnect support for ufs Add ufs-ddr and cpu-ufs interconnect support for khaje target. Change-Id: Ic620bd58ff02e2031bfb27c189bfb3706e3aa79e --- qcom/khaje.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index 23ab0c9f..c0d1d37e 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -2711,6 +2711,9 @@ <0 0>, <0 0>, <0 0>; + interconnects = <&system_noc MASTER_UFS_MEM &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; qcom,ufs-bus-bw,name = "ufshc_mem"; qcom,ufs-bus-bw,num-cases = <22>; qcom,ufs-bus-bw,num-paths = <2>; From 462de25f25d4208313600397478a5502f10c1385 Mon Sep 17 00:00:00 2001 From: Abdul Salam Date: Fri, 11 Nov 2022 16:11:49 +0530 Subject: [PATCH 51/71] ARM: dts: msm: Reduce size for modem_region modem_region and uefi_log are overlapping causing paging request error. Reduce modem_region size to prevent overlap with uefi_log. Change-Id: I14f5faed3f0adf17b4eab0b0da67e39346aaee18 --- qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 77f81a81..c0678d33 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -416,7 +416,7 @@ pil_modem_mem: modem_region { no-map; - reg = <0x0 0x8d800000 0x0 0x9600000>; + reg = <0x0 0x8d800000 0x0 0x4c1c000>; }; pil_video_mem: pil_video_region { From 21467715bc64216ff76f519d6f2078bf37bd8502 Mon Sep 17 00:00:00 2001 From: vagdhan kumar kanukurthi Date: Thu, 10 Nov 2022 15:09:07 +0530 Subject: [PATCH 52/71] ARM: dts: msm: Add direwolf dts files for lagvm Add base direwolf dts files for lagvm. Change-Id: I6cc05c2354e0e2c173b27315b1a374788a9f6dc1 --- qcom/Makefile | 10 ++++++++-- qcom/direwolf-vm-la-overlay.dts | 12 ++++++++++++ qcom/direwolf-vm-la.dts | 10 ++++++++++ qcom/direwolf-vm-la.dtsi | 21 +++++++++++++++++++++ 4 files changed, 51 insertions(+), 2 deletions(-) create mode 100644 qcom/direwolf-vm-la-overlay.dts create mode 100644 qcom/direwolf-vm-la.dts create mode 100644 qcom/direwolf-vm-la.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 5e38c8a2..18b35a9b 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -255,6 +255,10 @@ DIREWOLF_LV_GVM_BASE_DTB += direwolf-vm-lv.dtb DIREWOLF_LV_GVM_BOARDS += \ direwolf-vm-lv-overlay.dtbo +DIREWOLF_LA_GVM_BASE_DTB += direwolf-vm-la.dtb + +DIREWOLF_LA_GVM_BOARDS += \ + direwolf-vm-la-overlay.dtbo SA8195_LA_GVM_BASE_DTB += sa8195-vm-la.dtb @@ -264,10 +268,12 @@ SA8195_LA_GVM_BOARDS += \ autogvm-dtb-$(CONFIG_QTI_QUIN_GVM) += \ $(call add-overlays, $(SA8155_LA_GVM_BOARDS),$(SA8155_LA_GVM_BASE_DTB)) \ $(call add-overlays, $(DIREWOLF_LV_GVM_BOARDS),$(DIREWOLF_LV_GVM_BASE_DTB)) \ - $(call add-overlays, $(SA8195_LA_GVM_BOARDS),$(SA8195_LA_GVM_BASE_DTB)) + $(call add-overlays, $(SA8195_LA_GVM_BOARDS),$(SA8195_LA_GVM_BASE_DTB)) \ + $(call add-overlays, $(DIREWOLF_LA_GVM_BOARDS),$(DIREWOLF_LA_GVM_BASE_DTB)) + autogvm-overlays-dtb-$(CONFIG_QTI_QUIN_GVM) += \ $(SA8155_LA_GVM_BOARDS) $(DIREWOLF_LV_GVM_BOARDS) $(SA8155_LA_GVM_BASE_DTB) $(DIREWOLF_LV_GVM_BASE_DTB) \ - $(SA8195_LA_GVM_BOARDS) $(SA8195_LA_GVM_BASE_DTB) + $(SA8195_LA_GVM_BOARDS) $(SA8195_LA_GVM_BASE_DTB) $(DIREWOLF_LA_GVM_BOARDS) $(DIREWOLF_LA_GVM_BASE_DTB) dtb-y += $(autogvm-dtb-y) diff --git a/qcom/direwolf-vm-la-overlay.dts b/qcom/direwolf-vm-la-overlay.dts new file mode 100644 index 00000000..d2cf8a1e --- /dev/null +++ b/qcom/direwolf-vm-la-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "direwolf-vm.dtsi" +#include "direwolf-vm-la.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Direwolf Single LA Virtual Machine"; + compatible = "qcom,direwolf", "qcom,quinvm"; + qcom,msm-id = <460 0x10000>; + qcom,board-id = <0 0x1000001>; +}; diff --git a/qcom/direwolf-vm-la.dts b/qcom/direwolf-vm-la.dts new file mode 100644 index 00000000..75989518 --- /dev/null +++ b/qcom/direwolf-vm-la.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "direwolf-vm.dtsi" +#include "direwolf-vm-la.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Direwolf Single LA Virtual Machine"; + compatible = "qcom,direwolf", "qcom,quinvm"; + qcom,board-id = <0 0x1000001>; +}; diff --git a/qcom/direwolf-vm-la.dtsi b/qcom/direwolf-vm-la.dtsi new file mode 100644 index 00000000..24f6fc98 --- /dev/null +++ b/qcom/direwolf-vm-la.dtsi @@ -0,0 +1,21 @@ +&soc { +}; + +&reserved_memory { + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x0a000000>; + }; +}; + +&qcom_dma_heaps { + qcom,display { + qcom,dma-heap-name = "qcom,display"; + qcom,dma-heap-type = ; + qcom,max-align = <9>; + memory-region = <&secure_display_memory>; + }; +}; From 3d6fc498cb712c2b9de5bc81a9929c9849c4a8b4 Mon Sep 17 00:00:00 2001 From: Nitesh Kumar Date: Wed, 19 Oct 2022 15:43:19 +0530 Subject: [PATCH 53/71] ARM: dts: qcom: Add support to read external pmic temperature and voltage Add devicetree nodes to initialize external temperature and voltage reading driver. Change-Id: Iae5c3abbf30fab0ad18214bb2e5da3b34974ba2c --- qcom/cinder-thermal.dtsi | 96 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 95 insertions(+), 1 deletion(-) diff --git a/qcom/cinder-thermal.dtsi b/qcom/cinder-thermal.dtsi index d35287d6..29dee327 100644 --- a/qcom/cinder-thermal.dtsi +++ b/qcom/cinder-thermal.dtsi @@ -26,6 +26,43 @@ qcom,logic = <1>; }; }; + + aop_pmic_sensor: aop-pmic-sensor@c3f03d8 { + compatible = "qcom,aop-pmic-sensor"; + reg = <0x0c3f03d8 0x28>; + mboxes = <&qmp_aop 0>; + #thermal-sensor-cells = <1>; + + mss-temp { + qcom,pmic-id = <1>; + qcom,type = <0>; + }; + + mx-temp { + qcom,pmic-id = <2>; + qcom,type = <0>; + }; + + cx-temp { + qcom,pmic-id = <3>; + qcom,type = <0>; + }; + + mss-volt { + qcom,pmic-id = <1>; + qcom,type = <1>; + }; + + mx-volt { + qcom,pmic-id = <2>; + qcom,type = <1>; + }; + + cx-volt { + qcom,pmic-id = <3>; + qcom,type = <1>; + }; + }; }; &thermal_zones { @@ -394,4 +431,61 @@ }; }; }; -}; + + cx_temp { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&aop_pmic_sensor 1>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mx_temp { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&aop_pmic_sensor 2>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mss_temp { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&aop_pmic_sensor 3>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; +}; \ No newline at end of file From 9b84959f5fbeeba2e43252bfabd22f8cc77d9b81 Mon Sep 17 00:00:00 2001 From: Nitesh Kumar Date: Fri, 11 Nov 2022 12:36:29 +0530 Subject: [PATCH 54/71] dt-bindings: thermal: Add AOP pmic sensor driver bindings Add bindings for the qti aop pmic sensor driver. Change-Id: I58ff96b66517d82fe1f5cfda01932fdac2b56157 --- bindings/thermal/qti-aop-pmic-sensor.txt | 62 ++++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 bindings/thermal/qti-aop-pmic-sensor.txt diff --git a/bindings/thermal/qti-aop-pmic-sensor.txt b/bindings/thermal/qti-aop-pmic-sensor.txt new file mode 100644 index 00000000..5176d2a6 --- /dev/null +++ b/bindings/thermal/qti-aop-pmic-sensor.txt @@ -0,0 +1,62 @@ +=================================================================== +QTI AOP pmic sensor driver +=================================================================== + +QTI AOP pmic sensor driver will be used to give external data of pmic rails like temperature, voltage, etc. +This driver reads the required external data from MSGRAM which is updated by +communicating to RPMH via QMP. + +Properties: +- compatible: + Usage: required + Value type: + Definition: must be "qcom,aop-pmic-sensor" + + QTI AOP pmic sensor driver properties: +-qcom,dbu-id: + Usage: required + Value type: + Definition: Unique ID for a particular pmic. + +-qcom,type: + Usage: required + Value type: + Definition: It will be 1 and 0. 1 is identifier for voltage and 0 is for temperature. + +Example: + aop_pmic_sensor: aop-pmic-sensor@c3f03d8 { + compatible = "qcom,aop-pmic-sensor"; + reg = <0x0c3f03d8 0x28>; + mboxes = <&qmp_aop 0>; + #thermal-sensor-cells = <1>; + + mss-temp { + qcom,dbu-id = <1>; + qcom,type = <0>; + }; + + mx-temp { + qcom,dbu-id = <2>; + qcom,type = <0>; + }; + + cx-temp { + qcom,dbu-id = <3>; + qcom,type = <0>; + }; + + mss-volt { + qcom,dbu-id = <1>; + qcom,type = <1>; + }; + + mx-volt { + qcom,dbu-id = <2>; + qcom,type = <1>; + }; + + cx-volt { + qcom,dbu-id = <3>; + qcom,type = <1>; + }; + }; \ No newline at end of file From 568c30cf7935bc27dfcc0fc425f1bf1f2ed1ecce Mon Sep 17 00:00:00 2001 From: Mao Jinlong Date: Thu, 17 Nov 2022 13:32:46 +0800 Subject: [PATCH 55/71] ARM: dts: msm: correct the name of tpdm swao-prio-0 for cinder Correct the name of tpdm swao-prio-0 for IPCB trace. Change-Id: I1750c7a9582ec47f0b82fb141cca4f79a0cf67ab --- qcom/cinder-coresight.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/cinder-coresight.dtsi b/qcom/cinder-coresight.dtsi index 884bb3f2..fa5d2503 100644 --- a/qcom/cinder-coresight.dtsi +++ b/qcom/cinder-coresight.dtsi @@ -6,7 +6,7 @@ reg-names = "tpdm-base"; atid = <71>; - coresight-name = "coresight-tpdm-swao_prio0"; + coresight-name = "coresight-tpdm-swao-prio-0"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; From 54b044a0f1e06db0be52d53fdd687ba135a32c97 Mon Sep 17 00:00:00 2001 From: Naga Rashmi Ayiluri Date: Fri, 11 Nov 2022 15:31:49 +0530 Subject: [PATCH 56/71] ARM: dts: msm: Fixing compilaion issue in pinctrl file Adding this change to fix compilation issue in SA410m pinctrl file. Change-Id: I5340af90f69bb9db3ac4127a5a36d4f436a25b19 --- qcom/sa410m-pinctrl.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/sa410m-pinctrl.dtsi b/qcom/sa410m-pinctrl.dtsi index 609b06df..d5ec8b66 100644 --- a/qcom/sa410m-pinctrl.dtsi +++ b/qcom/sa410m-pinctrl.dtsi @@ -739,6 +739,9 @@ rclk { pins = "sdc1_rclk"; bias-pull-down; + }; + }; + pcie0 { pcie0_clkreq_default: pcie0_clkreq_default { mux { From 7b4451c1d8f8ca60f086a91ec8c7f56d2bbcc1c8 Mon Sep 17 00:00:00 2001 From: Singa Reddy Dasari Date: Mon, 18 Jul 2022 12:20:31 +0530 Subject: [PATCH 57/71] ARM: dts: msm: Add firmware node for auto gvm Add firmware node for auto gvm boot up. Change-Id: Ia095751e1cdfde2c0987ea06e1e08183ea3690aa --- qcom/quin-vm-common.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index 9d123dd1..575da93e 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -54,6 +54,30 @@ size = <0x0 0x1000000>; }; }; + + firmware: firmware { + android { + compatible = "android,firmware"; + boot_devices = "vdevs/1c140000.virtio_blk,vdevs/1c0b0000.virtio_blk,vdevs/1c0f0000.virtio_blk,vdevs/1c160000.virtio_blk,vdevs/1c130000.virtio_blk,vdevs/1c0e0000.virtio_blk,vdevs/1c100000.virtio_blk,vdevs/1c170000.virtio_blk,vdevs/1c180000.virtio_blk,vdevs/1c110000.virtio_blk,vdevs/1c120000.virtio_blk,vdevs/1c210000.virtio_blk,vdevs/1c220000.virtio_blk,vdevs/1c230000.virtio_blk,vdevs/1c240000.virtio_blk,vdevs/1c250000.virtio_blk,vdevs/1c260000.virtio_blk"; + + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,system,vendor"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev="/dev/block/platform/vdevs/1c0f0000.virtio_blk/vdc"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait"; + status = "disabled"; + }; + }; + }; + }; }; &soc { From dc2e5b85a104f74563596bbc988faae05c31d5e4 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Fri, 7 Oct 2022 14:56:02 +0530 Subject: [PATCH 58/71] ARM: dts: msm: Add flag to know if APSS based l1ss-sleep is supported or not Some endpoints like NVMe D3cold transition is prohibited as it decreases the life time of the device (D3 cold is treated as power cycle). So turning off the link during S3 can reduce life span of the NVMe. For those endpoints adding a flag to inform the driver that APSS based l1ss-sleep is supported. The PCIe driver will keep the link in L1ss and turn off PCIe resources if this flag is set. Change-Id: I3682bda297181eb9f5b63cf817b05e37b160b3ce --- bindings/pci/pci-msm.txt | 5 +++++ qcom/kalamap-hdk.dtsi | 1 + qcom/kalamap-sg-hhg.dtsi | 1 + 3 files changed, 7 insertions(+) diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index 464a61b8..cdf1976c 100644 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -265,6 +265,11 @@ interconnects: Value type: Definition: L1 sub-state (L1ss) is not supported +- qcom,apss-based-l1ss-sleep: + Usage: optional + Value type: + Definition: Apss based L1ss sleep is supported + - qcom,no-aux-clk-sync: Usage: optional Value type: diff --git a/qcom/kalamap-hdk.dtsi b/qcom/kalamap-hdk.dtsi index 56db337e..a2342d72 100644 --- a/qcom/kalamap-hdk.dtsi +++ b/qcom/kalamap-hdk.dtsi @@ -35,4 +35,5 @@ &pcie1 { qcom,boot-option = <0x2>; + qcom,apss-based-l1ss-sleep; }; diff --git a/qcom/kalamap-sg-hhg.dtsi b/qcom/kalamap-sg-hhg.dtsi index 8db68a41..1c231a2b 100644 --- a/qcom/kalamap-sg-hhg.dtsi +++ b/qcom/kalamap-sg-hhg.dtsi @@ -14,6 +14,7 @@ &pcie1 { vreg-3p3-supply = <&nvme_vreg>; qcom,boot-option = <0x2>; + qcom,apss-based-l1ss-sleep; }; ®ulator_ocp_notifier { From d322ef2f3c6d835d50d4f568f89293466e9e3bcc Mon Sep 17 00:00:00 2001 From: Sai Chaitanya Kaveti Date: Fri, 9 Sep 2022 17:12:56 +0530 Subject: [PATCH 59/71] ARM: dts: msm: Add EP-PCIe and MHI device configuration for sdxbaagha Add EP-PCIe and MHI device configuration for sdxbaagha to support EP PCIe and MHI functionalities. Change-Id: I10e00ffdd501846ce2f5a3b287733c9c4818b237 --- qcom/sdxbaagha-pinctrl.dtsi | 42 +++++++++++++++ qcom/sdxbaagha.dtsi | 102 ++++++++++++++++++++++++++++++++++++ 2 files changed, 144 insertions(+) diff --git a/qcom/sdxbaagha-pinctrl.dtsi b/qcom/sdxbaagha-pinctrl.dtsi index 0516b956..2b9c9bb2 100644 --- a/qcom/sdxbaagha-pinctrl.dtsi +++ b/qcom/sdxbaagha-pinctrl.dtsi @@ -50,6 +50,48 @@ }; }; }; + + pcie_ep { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio56"; + function = "pcie_clkreq_n"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; + }; }; pcie0 { pcie0_perst_default: pcie0_perst_default { diff --git a/qcom/sdxbaagha.dtsi b/qcom/sdxbaagha.dtsi index ee346f23..0bae498a 100644 --- a/qcom/sdxbaagha.dtsi +++ b/qcom/sdxbaagha.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -547,6 +548,107 @@ compatible = "qcom,msm-sps-4k"; qcom,pipe-attr-ee; }; + + pcie_ep: qcom,pcie@48000000 { + compatible = "qcom,pcie-ep"; + + reg = <0x48002000 0x1000>, + <0x48000000 0xf1d>, + <0x48000f20 0xa8>, + <0x48001000 0x1000>, + <0x01bf0000 0x4000>, + <0x01bf6000 0x2000>, + <0x01bf4000 0x1000>, + <0x01fcb000 0x1000>, + <0xc2f1000 0x4>; + reg-names = "msi", "dm_core", "elbi", "iatu", "parf", "phy", + "mmio", "tcsr_pcie_perst_en", "aoss_cc_reset"; + + #address-cells = <0>; + interrupt-parent = <&pcie_ep>; + interrupts = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int_global"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; + + clkreq-gpio = <&tlmm 56 GPIO_ACTIVE_HIGH>; + perst-gpio = <&tlmm 57 GPIO_ACTIVE_HIGH>; + wake-gpio = <&tlmm 53 GPIO_ACTIVE_HIGH>; + + gdsc-vdd-supply = <&gcc_pcie_gdsc>; + vreg-1p2-supply = <&L14A>; + vreg-0p9-supply = <&L3A>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; + + qcom,vreg-1p2-voltage-level = <1200000 1200000 15000>; + qcom,vreg-0p9-voltage-level = <912000 880000 48100>; + qcom,vreg-mx-voltage-level = ; + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_PIPE_CLK_SRC>, + <&pcie_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>; + + clock-names = "pcie_pipe_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_aux_clk", "pcie_ldo", + "pcie_sleep_clk", "pcie_slv_q2a_axi_clk", + "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src", + "pcie_0_ref_clk_src"; + + resets = <&gcc GCC_PCIE_BCR>, <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "pcie_core_reset", "pcie_phy_reset"; + + interconnect-names = "icc_path"; + interconnects = <&aggre_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + + qcom,pcie-vendor-id = /bits/ 16 <0x17cb>; + qcom,pcie-device-id = /bits/ 16 <0x011a>; + qcom,pcie-link-speed = <1>; + qcom,pcie-phy-ver = <7>; + qcom,pcie-active-config; + qcom,pcie-aggregated-irq; + qcom,pcie-mhi-a7-irq; + qcom,phy-status-reg2 = <0x214>; + qcom,mhi-soc-reset-offset = <0xb001b8>; + qcom,aoss-rst-clr; + qcom,aux-clk = <0x13>; + + status = "disabled"; + }; + + mhi_device: mhi_dev@1bf4000 { + compatible = "qcom,msm-mhi-dev"; + reg = <0x1bf4000 0x1000>; + reg-names = "mhi_mmio_base"; + qcom,mhi-ep-msi = <0>; + qcom,mhi-version = <0x1000000>; + qcom,use-mhi-dma-software-channel; + interrupts = ; + interrupt-names = "mhi-device-inta"; + qcom,mhi-ifc-id = <0x011a17cb>; + qcom,mhi-interrupt; + qcom,no-m0-timeout; + status = "disabled"; + }; + + mhi_net_device: qcom,mhi_net_dev { + compatible = "qcom,msm-mhi-dev-net"; + status = "disabled"; + }; }; #include "sdxbaagha-pinctrl.dtsi" From dba840590b2a75faff9ab2006816b45a3444bbb1 Mon Sep 17 00:00:00 2001 From: jianshu Date: Fri, 18 Nov 2022 14:12:05 +0800 Subject: [PATCH 60/71] ARM: dts: msm: Add tz_log device node for lemans Validate pass in lemans board, can get tz_log in /proc/tzdbg. Change-Id: I47231d4519b67f44f07a4e47ef310bac22e7b61f --- qcom/lemans.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index 148ace40..21893b5f 100644 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -1429,6 +1429,14 @@ qcom,qsee-reentrancy-support = <2>; }; + qcom_tzlog: tz-log@146d8720 { + compatible = "qcom,tz-log"; + reg = <0x146d8720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + qcom,glinkpkt { compatible = "qcom,glinkpkt"; From c29e2d217c9e84b0022a9cf383e66c3e055e1d4b Mon Sep 17 00:00:00 2001 From: Sai Chaitanya Kaveti Date: Fri, 18 Nov 2022 14:15:32 +0530 Subject: [PATCH 61/71] ARM: dts: msm: Add EP-PCIe PHY settings for sdxbaagha Add EP-PCIe PHY settings for sdxbaagha as per HSR. Making the PHY version as 8 for 4nm QMP PHY. Change-Id: I379db95921f86e37cd7e4e3c57924fbc36970a75 --- qcom/sdxbaagha.dtsi | 72 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 71 insertions(+), 1 deletion(-) diff --git a/qcom/sdxbaagha.dtsi b/qcom/sdxbaagha.dtsi index 0bae498a..8128cc80 100644 --- a/qcom/sdxbaagha.dtsi +++ b/qcom/sdxbaagha.dtsi @@ -618,7 +618,7 @@ qcom,pcie-vendor-id = /bits/ 16 <0x17cb>; qcom,pcie-device-id = /bits/ 16 <0x011a>; qcom,pcie-link-speed = <1>; - qcom,pcie-phy-ver = <7>; + qcom,pcie-phy-ver = <8>; qcom,pcie-active-config; qcom,pcie-aggregated-irq; qcom,pcie-mhi-a7-irq; @@ -626,6 +626,76 @@ qcom,mhi-soc-reset-offset = <0xb001b8>; qcom,aoss-rst-clr; qcom,aux-clk = <0x13>; + qcom,phy-init = <0x0240 0x01 0x0 + 0x0094 0x00 0x0 + 0x0154 0x31 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x19 0x0 + 0x00b0 0x04 0x0 + 0x00ac 0xff 0x0 + 0x00c4 0x14 0x0 + 0x00b8 0x09 0x0 + 0x00b4 0xff 0x0 + 0x0158 0x01 0x0 + 0x0074 0x20 0x0 + 0x007c 0x13 0x0 + 0x0084 0x00 0x0 + 0x0078 0x12 0x0 + 0x0080 0x12 0x0 + 0x0088 0x00 0x0 + 0x01b0 0x1d 0x0 + 0x01ac 0x56 0x0 + 0x01b8 0x17 0x0 + 0x01b4 0x78 0x0 + 0x004c 0x07 0x0 + 0x0050 0x07 0x0 + 0x00f0 0x01 0x0 + 0x00ec 0xfb 0x0 + 0x00f8 0x01 0x0 + 0x00f4 0xfb 0x0 + 0x000c 0x02 0x0 + 0x01a0 0x14 0x0 + 0x0ee4 0x20 0x0 + 0x0e84 0x75 0x0 + 0x0e90 0x3f 0x0 + 0x115c 0x7f 0x0 + 0x1160 0xff 0x0 + 0x1164 0xbf 0x0 + 0x1168 0x3f 0x0 + 0x116c 0xd8 0x0 + 0x1170 0xdc 0x0 + 0x1174 0xdc 0x0 + 0x1178 0x5c 0x0 + 0x117c 0x34 0x0 + 0x1180 0xa6 0x0 + 0x1190 0x34 0x0 + 0x1194 0x38 0x0 + 0x10d8 0x0f 0x0 + 0x0e3c 0x12 0x0 + 0x0e40 0x01 0x0 + 0x10dc 0x00 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x1044 0xf0 0x0 + 0x11a4 0x38 0x0 + 0x10cc 0xf0 0x0 + 0x10f4 0x07 0x0 + 0x1008 0x09 0x0 + 0x1014 0x05 0x0 + 0x0654 0x00 0x0 + 0x06a8 0x0f 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x02dc 0x0d 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; status = "disabled"; }; From 8e5313f82ca3c0be88ce3475b80497fcfa3ddf4d Mon Sep 17 00:00:00 2001 From: Praveen koya Date: Fri, 18 Nov 2022 20:35:58 +0530 Subject: [PATCH 62/71] ARM: dts: qcom: use qupv3_se4_spi label to enable aon spi Move the aon-spi dt node out of soc and use qupv3_se4_spi label to enable aon-spi dt node. Set slatecom SPI speed as 40MHz. Change-Id: I517f5f3a0806396b86a40baa8fb4fe0aff014957 --- qcom/slate.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/qcom/slate.dtsi b/qcom/slate.dtsi index b6cfc1e9..c5352e3c 100644 --- a/qcom/slate.dtsi +++ b/qcom/slate.dtsi @@ -1,13 +1,11 @@ -&soc { - qupv3_se4_spi: spi@4a90000 { /* BLSP4 QUP3*/ +&qupv3_se4_spi { /* BLSP4 QUP3*/ status = "ok"; qcom,shared_ee; qcom,slate-spi { compatible = "qcom,slate-spi"; reg = <0>; - spi-max-frequency = <737000>; + spi-max-frequency = <40000000>; interrupt-parent = <&tlmm>; qcom,irq-gpio = <&tlmm 95 1>; }; - }; }; From f80ed7bfb62ffe93de4f35b9576ef51f7f54f63f Mon Sep 17 00:00:00 2001 From: Praveen koya Date: Fri, 18 Nov 2022 20:45:12 +0530 Subject: [PATCH 63/71] ARM: dts: qcom: Add aon interface node Add aon interface node to be used by monaco. Change-Id: I0606b810556506d8c9feadd1e72f112f9f11ec14 --- qcom/slate.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/slate.dtsi b/qcom/slate.dtsi index c5352e3c..4310bc42 100644 --- a/qcom/slate.dtsi +++ b/qcom/slate.dtsi @@ -9,3 +9,9 @@ qcom,irq-gpio = <&tlmm 95 1>; }; }; + +&soc { + qcom,slate-daemon { + compatible = "qcom,slate-daemon"; + }; +}; From 80c51c541c148add096db3d1952ae40f2c92616d Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Fri, 18 Nov 2022 02:04:49 -0800 Subject: [PATCH 64/71] Revert "ARM: dts: msm: skip qos for lemans" This reverts commit b2fd6db23b7fe072d8ab8c9e8289e374bfb59a52. Change-Id: I59ac26933387a50541ac4c8db0da5e0a22587cc9 --- qcom/lemans.dtsi | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index 148ace40..19ea4844 100644 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -938,7 +938,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; mc_virt: interconnect@1 { @@ -946,7 +945,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; config_noc: interconnect@014C0000 { @@ -955,7 +953,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; system_noc: interconnect@01680000 { @@ -964,7 +961,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; aggre1_noc:interconnect@016C0000 { @@ -973,7 +969,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, @@ -987,7 +982,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, <&rpmhcc RPMH_IPA_CLK>; }; @@ -998,7 +992,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; gpdsp_anoc: interconnect@01780000 { @@ -1007,7 +1000,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; mmss_noc: interconnect@017A0000 { @@ -1016,7 +1008,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; lpass_ag_noc: interconnect@03C40000 { @@ -1025,7 +1016,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; dc_noc: interconnect@090E0000 { @@ -1034,7 +1024,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; gem_noc: interconnect@09100000 { @@ -1044,7 +1033,6 @@ qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>; - qcom,skip-qos; }; nspa_noc: interconnect@260C0000 { @@ -1053,7 +1041,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; nspb_noc: interconnect@2A0C0000 { @@ -1062,7 +1049,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; vendor_hooks: qcom,cpu-vendor-hooks { From 1ac883623006e80157b106fd264a44b25f8fc581 Mon Sep 17 00:00:00 2001 From: Jyothi Kumar Seerapu Date: Tue, 8 Nov 2022 20:05:52 +0530 Subject: [PATCH 65/71] ARM: dts: msm: Make PCIe0 to enumerate with x2 lane for sdxpinn Some sdxpinn targets have fuse blown parts and so in those targets one PCIe lane got disabled for PCIe0 and such devices are enumerates with x1 lane width. Hence, updated in PHY settings for PCIe0 to make sure that device enumerate with x2 lane width for PCIe0 of all sdxpinn targets. Change-Id: I2fdac831e670c2573541cb2e53a8c0f252f7f6e5 --- qcom/sdxpinn-pcie.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxpinn-pcie.dtsi b/qcom/sdxpinn-pcie.dtsi index e1d95457..de5cfb7d 100644 --- a/qcom/sdxpinn-pcie.dtsi +++ b/qcom/sdxpinn-pcie.dtsi @@ -287,7 +287,7 @@ 0x1828 0x00 0x0 0x1c28 0x00 0x0 0x1e24 0x00 0x0 - 0x1e28 0x00 0x0 + 0x1e28 0x01 0x0 0x1200 0x00 0x0 0x1244 0x03 0x0>; From b66a818737ffa81cf6cefe64b9908f7015a49f3a Mon Sep 17 00:00:00 2001 From: Jyothi Kumar Seerapu Date: Fri, 11 Nov 2022 15:42:40 +0530 Subject: [PATCH 66/71] ARM: dts: msm: Add LTR threshold support for sdxpinn Added the multiplier for L1.2 LTR threshold value and L1.2 latency tolerance reporting value for sdxpinn. Change-Id: I9310efcbb3b09875118bf3ce376335884aaf6e55 --- qcom/sdxpinn-pcie.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/sdxpinn-pcie.dtsi b/qcom/sdxpinn-pcie.dtsi index e1d95457..ad075671 100644 --- a/qcom/sdxpinn-pcie.dtsi +++ b/qcom/sdxpinn-pcie.dtsi @@ -117,6 +117,8 @@ qcom,tpwr-on-value = <9>; qcom,eq-fmdc-t-min-phase23 = <1>; qcom,slv-addr-space-size = <0x4000000>; + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <150>; qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; qcom,target-link-speed = <3>; @@ -424,6 +426,8 @@ qcom,tpwr-on-value = <9>; qcom,eq-fmdc-t-min-phase23 = <1>; qcom,slv-addr-space-size = <0x4000000>; + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <150>; qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; @@ -679,6 +683,8 @@ qcom,tpwr-on-value = <9>; qcom,eq-fmdc-t-min-phase23 = <1>; qcom,slv-addr-space-size = <0x4000000>; + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <150>; qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; From 680058afe8649589e9895005b276214c8b6e55ed Mon Sep 17 00:00:00 2001 From: Jyothi Kumar Seerapu Date: Fri, 28 Oct 2022 19:23:14 +0530 Subject: [PATCH 67/71] ARM: dts: msm: Set QSERDES_COM_SYSCLK_EN to 0x8 for PCIe2 PHY for sdxpinn For PCIe 2 PHY setting of QSERDES_COM_SYSCLK_EN to 0x4 which is internal diff cml clock, PHY is not coming up and hence changed the PCIe 2 PHY setting of QSERDES_COM_SYSCLK_EN to 0x8 which is SE cmos clock. Corrected SLV_Q2A_AXI_CLK clock for PCIe2. Updated reset names of core and phy of PCIe0. Change-Id: Ib227f03e2ddc4c581d538152e54fe036aef29895 --- qcom/sdxpinn-pcie.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/sdxpinn-pcie.dtsi b/qcom/sdxpinn-pcie.dtsi index e1d95457..50fbdcc1 100644 --- a/qcom/sdxpinn-pcie.dtsi +++ b/qcom/sdxpinn-pcie.dtsi @@ -105,8 +105,8 @@ <0>, <0>, <0>, <0>; resets = <&gcc GCC_PCIE_BCR>, <&gcc GCC_PCIE_PHY_BCR>; - reset-names = "pcie_core_reset", - "pcie_phy_reset"; + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; qcom,smmu-sid-base = <0x0800>; iommu-map = <0x0 &apps_smmu 0x0800 0x1>, @@ -648,7 +648,7 @@ <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, <&gcc GCC_PCIE_2_SLV_AXI_CLK>, <&gcc GCC_PCIE_2_CLKREF_EN>, - <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, <&gcc GCC_PCIE_2_PIPE_DIV2_CLK>, <&gcc GCC_PCIE_2_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_2_PIPE_CLK_SRC>, @@ -718,7 +718,7 @@ 0x00e0 0x90 0x0 0x00e4 0x82 0x0 0x00f4 0x07 0x0 - 0x0110 0x04 0x0 + 0x0110 0x08 0x0 0x0120 0x42 0x0 0x0140 0x14 0x0 0x0164 0x34 0x0 From 0b617a81abbe2f4fbdaaae2cc8ad93ea8884d7bf Mon Sep 17 00:00:00 2001 From: Jyothi Kumar Seerapu Date: Fri, 18 Nov 2022 15:27:38 +0530 Subject: [PATCH 68/71] ARM: dts: msm: Set boot option 1 to enumeration request by WLAN for sdxpinn For WLAN attaches the enumeration request should be done by WLAN. And then PCIe Root complex will perform the enumeration process. Change-Id: Ic7f897c374cf78d91113cfcced8cf8abd10ac07c --- qcom/sdxpinn-pcie.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/sdxpinn-pcie.dtsi b/qcom/sdxpinn-pcie.dtsi index e1d95457..cab8014f 100644 --- a/qcom/sdxpinn-pcie.dtsi +++ b/qcom/sdxpinn-pcie.dtsi @@ -112,6 +112,7 @@ iommu-map = <0x0 &apps_smmu 0x0800 0x1>, <0x100 &apps_smmu 0x0801 0x1>; + qcom,boot-option = <0x1>; qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,tpwr-on-scale = <1>; qcom,tpwr-on-value = <9>; @@ -419,6 +420,7 @@ iommu-map = <0x0 &apps_smmu 0x0880 0x1>, <0x100 &apps_smmu 0x0881 0x1>; + qcom,boot-option = <0x1>; qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,tpwr-on-scale = <1>; qcom,tpwr-on-value = <9>; @@ -674,6 +676,7 @@ iommu-map = <0x0 &apps_smmu 0x0900 0x1>, <0x100 &apps_smmu 0x0901 0x1>; + qcom,boot-option = <0x1>; qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,tpwr-on-scale = <1>; qcom,tpwr-on-value = <9>; From 20ae3435656b324ddbcaf7c2b551fb82e293f9c5 Mon Sep 17 00:00:00 2001 From: vagdhan kumar kanukurthi Date: Tue, 22 Nov 2022 11:17:41 +0530 Subject: [PATCH 69/71] ARM: dts: qcom: Add the qrng node for the Auto VM direwolf platforms Add the qrng node for the Auto VM direwolf platform for generate random number. Change-Id: If05e6ae7a882d789fd7e5624186a1e4108d15acb --- qcom/direwolf-vm-la.dtsi | 4 ++++ qcom/direwolf-vm.dtsi | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/qcom/direwolf-vm-la.dtsi b/qcom/direwolf-vm-la.dtsi index 24f6fc98..c9f71ee7 100644 --- a/qcom/direwolf-vm-la.dtsi +++ b/qcom/direwolf-vm-la.dtsi @@ -19,3 +19,7 @@ memory-region = <&secure_display_memory>; }; }; + +&qcom_rng_ee3 { + status = "okay"; +}; diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 78ac42b8..09664bb0 100644 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -157,6 +157,24 @@ compatible = "qcom,iommu-dma"; memory-region = <&system_cma>; }; + + qcom_rng_ee3: qrng@10d3000 { + compatible = "qcom,msm-rng"; + reg = <0x10d3000 0x1000>; + qcom,no-qrng-config; + clocks = <&dummycc RPMH_HWKM_CLK>; + clock-names = "km_clk_src"; + status = "disabled"; + }; + + qcom_rng_ee4: qrng@10d4000 { + compatible = "qcom,msm-rng"; + reg = <0x10d4000 0x1000>; + qcom,no-qrng-config; + clocks = <&dummycc RPMH_HWKM_CLK>; + clock-names = "km_clk_src"; + status = "disabled"; + }; }; ®ulator { From 2d88f449591f3c93de8f2cc8035a3545f9b8dd09 Mon Sep 17 00:00:00 2001 From: LADI RAM SAI Date: Tue, 22 Nov 2022 15:09:07 +0530 Subject: [PATCH 70/71] ARM: dts: qcom: Remove delay in phy-init-seq of USB1 SS-PHY Remove delay in qmp-phy-init-seq of USB1 ssphy for auto sa8155 vm. Change-Id: I849e444c5e70070ed690cd5e26f7295e82bc1c26 --- qcom/sa8155-vm-usb.dtsi | 199 ++++++++++++++++++++-------------------- 1 file changed, 99 insertions(+), 100 deletions(-) diff --git a/qcom/sa8155-vm-usb.dtsi b/qcom/sa8155-vm-usb.dtsi index 63e5cef5..056154e0 100644 --- a/qcom/sa8155-vm-usb.dtsi +++ b/qcom/sa8155-vm-usb.dtsi @@ -184,106 +184,105 @@ qcom,vdd-max-load-uA = <47000>; core-supply = <&L8C>; qcom,qmp-phy-init-seq = - /* */ - ; + /* */ + ; qcom,qmp-phy-reg-offset = Date: Thu, 10 Nov 2022 16:07:04 +0800 Subject: [PATCH 71/71] ARM: dts: msm: add audio nodes on lemans Add pinctrl nodes for audio interfaces on lemans. Add audio used i2c and spi devices. Change-Id: Iee6294557a9765c9a2e911e03d0ad6ac62f7787c --- qcom/lemans-pinctrl.dtsi | 624 +++++++++++++++++++++++++++++++++++++++ qcom/lemans.dtsi | 2 + 2 files changed, 626 insertions(+) diff --git a/qcom/lemans-pinctrl.dtsi b/qcom/lemans-pinctrl.dtsi index c3153f08..a95e84b6 100644 --- a/qcom/lemans-pinctrl.dtsi +++ b/qcom/lemans-pinctrl.dtsi @@ -1578,4 +1578,628 @@ }; }; }; + + sec_tdm_sck { + sec_tdm_sck_sleep: sec_tdm_sck_sleep { + mux { + pins = "gpio106"; + function = "gpio"; + }; + + config { + pins = "gpio106"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_sck_active: sec_tdm_sck_active { + mux { + pins = "gpio106"; + function = "mi2s1_sck"; + }; + + config { + pins = "gpio106"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + sec_tdm_ws { + sec_tdm_ws_sleep: sec_tdm_ws_sleep { + mux { + pins = "gpio107"; + function = "gpio"; + }; + + config { + pins = "gpio107"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_ws_active: sec_tdm_ws_active { + mux { + pins = "gpio107"; + function = "mi2s1_ws"; + }; + + config { + pins = "gpio107"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + sec_tdm_din { + sec_tdm_din_sleep: sec_tdm_din_sleep { + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_din_active: sec_tdm_din_active { + mux { + pins = "gpio108"; + function = "mi2s1_data0"; + }; + + config { + pins = "gpio108"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_tdm_dout { + sec_tdm_dout_sleep: sec_tdm_dout_sleep { + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_dout_active: sec_tdm_dout_active { + mux { + pins = "gpio109"; + function = "mi2s1_data1"; + }; + + config { + pins = "gpio109"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_tdm_sck { + tert_tdm_sck_sleep: tert_tdm_sck_sleep { + mux { + pins = "gpio110"; + function = "gpio"; + }; + + config { + pins = "gpio110"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_sck_active: tert_tdm_sck_active { + mux { + pins = "gpio110"; + function = "mi2s2_sck"; + }; + + config { + pins = "gpio110"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_tdm_ws { + tert_tdm_ws_sleep: tert_tdm_ws_sleep { + mux { + pins = "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_ws_active: tert_tdm_ws_active { + mux { + pins = "gpio111"; + function = "mi2s2_ws"; + }; + + config { + pins = "gpio111"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_tdm_din { + tert_tdm_din_sleep: tert_tdm_din_sleep { + mux { + pins = "gpio112"; + function = "gpio"; + }; + + config { + pins = "gpio112"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_din_active: tert_tdm_din_active { + mux { + pins = "gpio112"; + function = "mi2s2_data0"; + }; + + config { + pins = "gpio112"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_tdm_dout { + tert_tdm_dout_sleep: tert_tdm_dout_sleep { + mux { + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_dout_active: tert_tdm_dout_active { + mux { + pins = "gpio113"; + function = "mi2s2_data1"; + }; + + config { + pins = "gpio113"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs0_i2s_sck { + hs0_i2s_sck_sleep: hs0_i2s_sck_sleep { + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs0_i2s_sck_active: hs0_i2s_sck_active { + mux { + pins = "gpio114"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio114"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs0_i2s_ws { + hs0_i2s_ws_sleep: hs0_i2s_ws_sleep { + mux { + pins = "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio115"; + drive-strength = <2>; /* 8 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs0_i2s_ws_active: hs0_i2s_ws_active { + mux { + pins = "gpio115"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio115"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs0_i2s_data0 { + hs0_i2s_data0_sleep: hs0_i2s_data0_sleep { + mux { + pins = "gpio116"; + function = "gpio"; + }; + + config { + pins = "gpio116"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs0_i2s_data0_active: hs0_i2s_data0_active { + mux { + pins = "gpio116"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio116"; + drive-strength = <8>; /* 2 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + hs0_i2s_data1 { + hs0_i2s_data1_sleep: hs0_i2s_data1_sleep { + mux { + pins = "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio117"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs0_i2s_data1_active: hs0_i2s_data1_active { + mux { + pins = "gpio117"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio117"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs1_i2s_sck { + hs1_i2s_sck_sleep: hs1_i2s_sck_sleep { + mux { + pins = "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio118"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs1_i2s_sck_active: hs1_i2s_sck_active { + mux { + pins = "gpio118"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio118"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs1_i2s_ws { + hs1_i2s_ws_sleep: hs1_i2s_ws_sleep { + mux { + pins = "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio119"; + drive-strength = <2>; /* 8 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs1_i2s_ws_active: hs1_i2s_ws_active { + mux { + pins = "gpio119"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio119"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs1_i2s_data0 { + hs1_i2s_data0_sleep: hs1_i2s_data0_sleep { + mux { + pins = "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio120"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs1_i2s_data0_active: hs1_i2s_data0_active { + mux { + pins = "gpio120"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio120"; + drive-strength = <8>; /* 2 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + hs1_i2s_data1 { + hs1_i2s_data1_sleep: hs1_i2s_data1_sleep { + mux { + pins = "gpio121"; + function = "gpio"; + }; + + config { + pins = "gpio121"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs1_i2s_data1_active: hs1_i2s_data1_active { + mux { + pins = "gpio121"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio121"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs2_i2s_sck { + hs2_i2s_sck_sleep: hs2_i2s_sck_sleep { + mux { + pins = "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio122"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs2_i2s_sck_active: hs2_i2s_sck_active { + mux { + pins = "gpio122"; + function = "hs2_mi2s"; + }; + + config { + pins = "gpio122"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs2_i2s_ws { + hs2_i2s_ws_sleep: hs2_i2s_ws_sleep { + mux { + pins = "gpio123"; + function = "gpio"; + }; + + config { + pins = "gpio123"; + drive-strength = <2>; /* 8 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs2_i2s_ws_active: hs2_i2s_ws_active { + mux { + pins = "gpio123"; + function = "hs2_mi2s"; + }; + + config { + pins = "gpio123"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs2_i2s_data0 { + hs2_i2s_data0_sleep: hs2_i2s_data0_sleep { + mux { + pins = "gpio124"; + function = "gpio"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs2_i2s_data0_active: hs2_i2s_data0_active { + mux { + pins = "gpio124"; + function = "hs2_mi2s"; + }; + + config { + pins = "gpio124"; + drive-strength = <8>; /* 2 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + hs2_i2s_data1 { + hs2_i2s_data1_sleep: hs2_i2s_data1_sleep { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs2_i2s_data1_active: hs2_i2s_data1_active { + mux { + pins = "gpio125"; + function = "hs2_mi2s"; + }; + + config { + pins = "gpio125"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + audio_internal_mclk1 { + audio_internal_mclk1_sleep: audio_internal_mclk1_sleep { + mux { + pins = "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio105"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + audio_internal_mclk1_active: audio_internal_mclk1_active { + mux { + pins = "gpio105"; + function = "mi2s_mclk0"; + }; + + config { + pins = "gpio105"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; }; diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index 148ace40..6fe85643 100644 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -29,6 +29,8 @@ aliases { serial0 = &qupv3_se10_2uart; ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + i2c4 = &qupv3_se11_i2c; + spi16 = &qupv3_se16_spi; }; soc: soc { };