diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi
index d7ad2098..2b6870ec 100644
--- a/qcom/cinder.dtsi
+++ b/qcom/cinder.dtsi
@@ -526,6 +526,21 @@
 		vdd_cx-supply = <&VDD_CX_LEVEL>;
 		clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
 		clock-names = "bi_tcxo", "sleep_clk";
+		protected-clocks = <GCC_AGGRE_NOC_ECPRI_DMA_CLK>,
+				<GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC>,
+				<GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC>,
+				<GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+				<GCC_DDRSS_ECPRI_DMA_CLK>,
+				<GCC_GEMNOC_PCIE_QX_CLK>,
+				<GCC_QMIP_ANOC_PCIE_CLK>,
+				<GCC_QMIP_ECPRI_DMA0_CLK>,
+				<GCC_QMIP_ECPRI_DMA1_CLK>,
+				<GCC_QMIP_ECPRI_GSI_CLK>,
+				<GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK>,
+				<GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK>,
+				<GCC_SNOC_CNOC_PCIE_QX_CLK>,
+				<GCC_SNOC_PCIE_SF_CENTER_QX_CLK>,
+				<GCC_SNOC_PCIE_SF_SOUTH_QX_CLK>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
@@ -539,16 +554,19 @@
 
 	/* GCC GDSCs */
 	gcc_pcie_0_gdsc: qcom,gdsc@11d004 {
+		reg = <0x11d004 0x4>;
 		compatible = "qcom,gdsc";
 		regulator-name = "gcc_pcie_0_gdsc";
 	};
 
 	gcc_pcie_0_phy_gdsc: qcom,gdsc@fc004 {
+		reg = <0xfc004 0x4>;
 		compatible = "qcom,gdsc";
 		regulator-name = "gcc_pcie_0_phy_gdsc";
 	};
 
 	gcc_usb30_prim_gdsc: qcom,gdsc@c9004 {
+		reg = <0xc9004 0x4>;
 		compatible = "qcom,gdsc";
 		regulator-name = "gcc_usb30_prim_gdsc";
 	};