From 560defa30a12be38fe659fba0a1eb30b4fdea3f6 Mon Sep 17 00:00:00 2001
From: Mrinmay Sarkar <msarkar@qti.qualcomm.com>
Date: Wed, 7 Sep 2022 19:18:37 +0530
Subject: [PATCH] ARM: dts: msm: update bw-scale DT property for gen3 targets

Adding mx_vreg_min frequency option in qcom,bw-scale DT properety
in gen3 targets.

Change-Id: I100f83bceda70ce3e5a4413b635e9995ed5b4949
---
 qcom/sa8195p-pcie.dtsi | 60 +++++++++++++++++++++++++++++++++---------
 qcom/sm8150-pcie.dtsi  | 32 +++++++++++++++++-----
 2 files changed, 74 insertions(+), 18 deletions(-)

diff --git a/qcom/sa8195p-pcie.dtsi b/qcom/sa8195p-pcie.dtsi
index 43bbd716..09960e47 100644
--- a/qcom/sa8195p-pcie.dtsi
+++ b/qcom/sa8195p-pcie.dtsi
@@ -175,9 +175,18 @@
 		qcom,smmu-sid-base = <0x1d80>;
 
 		dma-coherent;
-		qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
-				RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
-				RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_NOM
+				100000000>;
 
 		iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
 			<0x100 &apps_smmu 0x1d81 0x1>,
@@ -488,9 +497,18 @@
 		qcom,smmu-sid-base = <0x1c80>;
 
 		dma-coherent;
-		qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
-				RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
-				RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_NOM
+				100000000>;
 
 		iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
 			<0x100 &apps_smmu 0x1c81 0x1>,
@@ -801,9 +819,18 @@
 		qcom,smmu-sid-base = <0x1d00>;
 
 		dma-coherent;
-		qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
-				RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
-				RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_NOM
+				100000000>;
 
 		iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
 			<0x100 &apps_smmu 0x1d01 0x1>,
@@ -1244,9 +1271,18 @@
 		qcom,smmu-sid-base = <0x1e00>;
 
 		dma-coherent;
-		qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
-				RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
-				RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_NOM
+				100000000>;
 
 		iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
 			<0x100 &apps_smmu 0x1e01 0x1>,
diff --git a/qcom/sm8150-pcie.dtsi b/qcom/sm8150-pcie.dtsi
index 5c36f2c3..3bd56286 100644
--- a/qcom/sm8150-pcie.dtsi
+++ b/qcom/sm8150-pcie.dtsi
@@ -150,9 +150,19 @@
 		qcom,vreg-0p9-voltage-level = <880000 880000 24000>;
 		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
 						RPMH_REGULATOR_LEVEL_NOM 0>;
-		qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
-				RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
-				RPMH_REGULATOR_LEVEL_NOM 100000000>;
+
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_NOM
+				100000000>;
 
 		interconnect-names = "icc_path";
 		interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
@@ -473,9 +483,19 @@
 		qcom,vreg-0p9-voltage-level = <880000 880000 24000>;
 		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
 						RPMH_REGULATOR_LEVEL_NOM 0>;
-		qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
-				RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
-				RPMH_REGULATOR_LEVEL_NOM 100000000>;
+
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_NOM
+				100000000>;
 
 		interconnect-names = "icc_path";
 		interconnects = <&aggre2_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;