From 22675cb9123bd25ed8fbfea4eb33186b7ffe977c Mon Sep 17 00:00:00 2001 From: Can Guo Date: Sun, 15 May 2022 23:27:35 -0700 Subject: [PATCH] ARM: dts: msm: Add EP PCIe and MHI related DT entries on sdxpinn Add EP PCIe and MHI device related DT entries on sdxpinn to support EP PCIe and MHI functionalities. Change-Id: I97bcc66227d495b5c4c61ea6cb0e880dd4d82b11 --- qcom/sdxpinn-pinctrl.dtsi | 42 +++++++++++++++ qcom/sdxpinn-rumi.dtsi | 22 ++++++++ qcom/sdxpinn.dtsi | 105 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 169 insertions(+) diff --git a/qcom/sdxpinn-pinctrl.dtsi b/qcom/sdxpinn-pinctrl.dtsi index b7447048..fbe064c1 100644 --- a/qcom/sdxpinn-pinctrl.dtsi +++ b/qcom/sdxpinn-pinctrl.dtsi @@ -201,4 +201,46 @@ }; }; }; + + pcie_ep { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio43"; + function = "pcie0_clkreq_n"; + }; + + config { + pins = "gpio43"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio44"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio42"; + drive-strength = <2>; + bias-disable; + }; + }; + }; }; diff --git a/qcom/sdxpinn-rumi.dtsi b/qcom/sdxpinn-rumi.dtsi index 3d49e578..5366401c 100644 --- a/qcom/sdxpinn-rumi.dtsi +++ b/qcom/sdxpinn-rumi.dtsi @@ -113,3 +113,25 @@ dr_mode = "peripheral"; }; }; + +&pcie_ep { + reg = <0x48003800 0x10000>, + <0x48000000 0xf20>, + <0x48000f20 0xa8>, + <0x48001000 0x2000>, + <0x01bf0000 0x4000>, + <0x01bf7000 0x2000>, + <0x01bf4000 0x1000>, + <0x01bf7500 0x4>; + reg-names = "msi", "dm_core", "elbi", "iatu", + "parf", "phy", "mmio", "rumi"; + + qcom,pcie-link-speed = <1>; + qcom,tcsr-not-supported; + + status = "ok"; +}; + +&mhi_device { + status = "ok"; +}; diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi index e9adfb06..aacf2c66 100644 --- a/qcom/sdxpinn.dtsi +++ b/qcom/sdxpinn.dtsi @@ -3,6 +3,8 @@ #include #include #include +#include +#include / { model = "Qualcomm Technologies, Inc. SDXPINN"; @@ -649,6 +651,109 @@ thermal_zones: thermal-zones { }; + pcie_ep: qcom,pcie@0x48000000 { + compatible = "qcom,pcie-ep"; + reg = <0x48003800 0x1000>, + <0x48000000 0xf20>, + <0x48000f20 0xa8>, + <0x48001000 0x2000>, + <0x01bf0000 0x4000>, + <0x01bf7000 0x2000>, + <0x01bf4000 0x1000>, + <0x01fcb000 0x1000>, + <0x0c2fa000 0x4>; + reg-names = "msi", "dm_core", "elbi", "iatu", + "parf", "phy", "mmio", "tcsr_pcie_perst_en", + "aoss_cc_reset"; + + #address-cells = <0>; + interrupt-parent = <&pcie_ep>; + interrupts = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int_global"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default + &pcie_ep_perst_default + &pcie_ep_wake_default>; + clkreq-gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>; + perst-gpio = <&tlmm 44 GPIO_ACTIVE_HIGH>; + wake-gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>; + + gdsc-vdd-supply = <&gcc_pcie_gdsc>; + gdsc-phy-vdd-supply = <&gcc_pcie_phy_gdsc>; + vreg-1p8-supply = <&L1B>; + vreg-0p9-supply = <&L4B>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; + qcom,vreg-1p8-voltage-level = <1200000 1200000 30000>; + qcom,vreg-0p9-voltage-level = <912000 880000 177000>; + qcom,vreg-mx-voltage-level = ; + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_PIPE_CLK_SRC>, + <&pcie_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>; + + clock-names = "pcie_pipe_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_aux_clk", "pcie_ldo", + "pcie_sleep_clk", + "pcie_slv_q2a_axi_clk", + "pcie_pipe_clk_mux", + "pcie_pipe_clk_ext_src", + "pcie_0_ref_clk_src"; + + resets = <&gcc GCC_PCIE_BCR>, + <&gcc GCC_PCIE_PHY_BCR>; + + reset-names = "pcie_core_reset", + "pcie_phy_reset"; + qcom,pcie-vendor-id = /bits/ 16 <0x17cb>; + qcom,pcie-device-id = /bits/ 16 <0x0309>; + qcom,pcie-link-speed = <4>; + qcom,pcie-phy-ver = <7>; + qcom,pcie-active-config; + qcom,pcie-aggregated-irq; + qcom,pcie-mhi-a7-irq; + qcom,phy-status-reg2 = <0x1214>; + qcom,mhi-soc-reset-offset = <0xb01b8>; + qcom,aoss-rst-clr; + qcom,aux-clk = <0x13>; + + status = "disabled"; + }; + + mhi_device: mhi_dev@1bf4000 { + compatible = "qcom,msm-mhi-dev"; + reg = <0x1bf4000 0x1000>; + reg-names = "mhi_mmio_base"; + qcom,mhi-ep-msi = <0>; + qcom,mhi-version = <0x1000000>; + qcom,use-mhi-dma-software-channel; + interrupts = ; + interrupt-names = "mhi-device-inta"; + qcom,mhi-ifc-id = <0x030917cb>; + qcom,mhi-interrupt; + qcom,no-m0-timeout; + status = "disabled"; + }; + + mhi_net_device: qcom,mhi_net_dev { + compatible = "qcom,msm-mhi-dev-net"; + status = "disabled"; + }; + qcom,sps { compatible = "qcom,msm-sps-4k"; qcom,pipe-attr-ee;