diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt
index d1831e7b..f2a15e8c 100644
--- a/bindings/arm/msm/msm.txt
+++ b/bindings/arm/msm/msm.txt
@@ -107,6 +107,9 @@ SoCs:
 - SA410M
   compatible = "qcom,sa410m"
 
+- MONACO
+  compatible = "qcom,monaco", "qcom,monacop"
+
 Generic board variants:
 
 - CDP device:
diff --git a/bindings/bluetooth/btpower.txt b/bindings/bluetooth/btpower.txt
index 4c2b2df9..a73adc9a 100644
--- a/bindings/bluetooth/btpower.txt
+++ b/bindings/bluetooth/btpower.txt
@@ -10,6 +10,7 @@ Required properties:
 		qcom,wcn3990
 		qcom,qca6390
 		qcom,qca6490
+		qcom,qcc5100
 	- qcom,bt-reset-gpio: GPIO pin to bring BT Controller out of reset
 
 Optional properties:
diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt
index ff1d74b6..82981048 100644
--- a/bindings/clock/qcom,debugcc.txt
+++ b/bindings/clock/qcom,debugcc.txt
@@ -15,6 +15,7 @@ Required properties :
 			"qcom,cinder-debugcc"
 			"qcom,khaje-debugcc"
 			"qcom,sc8180x-debugcc"
+			"qcom,monaco-debugcc"
 
 - qcom,gcc: phandle to the GCC device node.
 - qcom,videocc: phandle to the Video CC device node.
diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt
index 7333746c..8582ae8a 100644
--- a/bindings/clock/qcom,dispcc.txt
+++ b/bindings/clock/qcom,dispcc.txt
@@ -9,13 +9,22 @@ Required properties :
 			"qcom,lahaina-dispcc"
 			"qcom,shima-dispcc"
 			"qcom,holi-dispcc"
-			"qcom,waipio-dispcc"
-			"qcom,diwali-dispcc"
-			"qcom,kalama-dispcc"
 			"qcom,sm8150-dispcc"
 			"qcom,sm8150-dispcc-v2"
-			"qcom,khaje-dispcc"
-			"qcom,sc8180x-dispcc"
+			"qcom,yupik-dispcc"
+			"qcom,scshrike-dispcc"
+			"qcom,scshrike-dispcc-v2"
+			"qcom,sm6150-dispcc"
+			"qcom,sa6155-dispcc"
+			"qcom,monaco-dispcc"
+			"qcom,blair-dispcc"
+			"qcom,scuba-dispcc"
+			"qcom,direwolf-dispcc0"
+			"qcom,direwolf-dispcc1"
+			"qcom,bengal-dispcc"
+			"qcom,lemans-dispcc0"
+			"qcom,lemans-dispcc1"
+			"qcom,kona-dispcc"
 
 - reg : shall contain base register location and length.
 - #clock-cells : from common clock binding, shall contain 1.
diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt
index 3c9b6d05..e1b5c818 100644
--- a/bindings/clock/qcom,gcc.txt
+++ b/bindings/clock/qcom,gcc.txt
@@ -38,6 +38,7 @@ Required properties :
 			"qcom,cinder-gcc"
 			"qcom,khaje-gcc"
 			"qcom,gcc-sc8180x"
+			"qcom,monaco-gcc"
 
 - reg : shall contain base register location and length
 - vdd_cx-supply: The vdd_cx logic rail supply.
diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt
index b73d61ae..ae2a9757 100644
--- a/bindings/clock/qcom,gpucc.txt
+++ b/bindings/clock/qcom,gpucc.txt
@@ -14,6 +14,7 @@ Required properties :
 		"qcom,sa8155-gpucc",
 		"qcom,khaje-gpucc",
 		"qcom,sc8180x-gpucc".
+		"qcom,monaco-gpucc",
 
 - reg: shall contain base register offset and size.
 - reg-names: names of registers listed in the same order as in the reg property.
diff --git a/bindings/clock/qcom,rpmcc.txt b/bindings/clock/qcom,rpmcc.txt
index 217e48e6..b6b4629f 100644
--- a/bindings/clock/qcom,rpmcc.txt
+++ b/bindings/clock/qcom,rpmcc.txt
@@ -27,6 +27,7 @@ Required properties :
 			"qcom,rpmcc-sdm660", "qcom,rpmcc"
 			"qcom,rpmcc-holi", "qcom,rpmcc"
 			"qcom,rpmcc-khaje", "qcom,rpmcc"
+			"qcom,rpmcc-monaco", "qcom,rpmcc"
 
 - #clock-cells : shall contain 1
 
diff --git a/bindings/interconnect/qcom,monaco.txt b/bindings/interconnect/qcom,monaco.txt
new file mode 100644
index 00000000..2ac33b98
--- /dev/null
+++ b/bindings/interconnect/qcom,monaco.txt
@@ -0,0 +1,46 @@
+QTI MONACO Network-On-Chip interconnect driver binding
+-----------------------------------------------------------
+
+Required properties :
+- compatible : shall contain only one of the following:
+			"qcom,monaco-bimc",
+			"qcom,monaco-system_noc",
+			"qcom,monaco-config_noc",
+			"qcom,monaco-clk_virt",
+			"qcom,monaco-mmnrt_virt",
+			"qcom,monaco-mmrt_virt",
+- #interconnect-cells : should contain 1
+
+reg : specifies the physical base address and size of registers
+clocks : list of phandles and specifiers to all interconnect bus clocks
+clock-names : clock names should include both "bus" and "bus_a"
+
+The following are optional properties:
+
+qcom,util-factor : Parameter that represents the DDR utilization factor
+		to be used in aggregation scheme. It is represented as
+		actual util-factor * 100.
+
+Examples:
+
+soc {
+	...
+	system_noc: interconnect@1880000 {
+		reg = <0x1880000 0x5e200>;
+		compatible = "qcom,monaco-system_noc";
+		qcom,util-factor = <142>;
+		#interconnect-cells = <1>;
+		clock-names = "bus", "bus_a";
+		clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
+			<&rpmcc RPM_SMD_SNOC_A_CLK>;
+	};
+
+	config_noc: interconnect@1900000 {
+		reg = <0x1900000 0xa400>;
+		compatible = "qcom,monaco-config_noc";
+		#interconnect-cells = <1>;
+		clock-names = "bus", "bus_a";
+		clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
+			<&rpmcc RPM_SMD_CNOC_A_CLK>;
+	};
+};
diff --git a/bindings/interrupt-controller/qcom,mpm.txt b/bindings/interrupt-controller/qcom,mpm.txt
new file mode 100644
index 00000000..90a85890
--- /dev/null
+++ b/bindings/interrupt-controller/qcom,mpm.txt
@@ -0,0 +1,77 @@
+QTI MPM interrupt controller
+MPM (MSM sleep Power Manager) is QTI's platform parent
+interrupt controller. It manages subsystem wakeups and
+resources during sleep. This driver marks the wakeup
+interrupts in APSS such that it monitors the interrupts
+when the system is asleep, wakes up the APSS when one
+of these interrupts occur and replays it to the subsystem
+interrupt controller after it becomes operational.
+
+Platform interrupt controller MPM is next in hierarchy,
+followed by others.
+
+This defines 2 interrupt controllers to monitor the
+interrupts when system is asleep:
+
+One to monitor the wakeup capable gic interrupts called
+wakegic.
+
+Properties:
+
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: Should contain "qcom,mpm-gic" and the respective
+	target compatible flag from below ones.
+		"qcom,mpm-gic-holi"
+		"qcom,mpm-gic-scuba"
+		"qcom,mpm-gic-sdxnightjar"
+		"qcom,mpm-gic-monaco"
+		"qcom,mpm-gic-qcs405"
+		"qcom,mpm-gic-bengal"
+
+- interrupts:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: should specify the IRQ used by remote processor to
+	wakeup APSS.
+
+- interrupt-parent:
+	Usage: required
+	Value type: <phandle>
+	Definition: Specifies the interrupt parent necessary for
+	hierarchical domain to operate.
+
+- interrupt-controller:
+	Usage: required
+	Value type: <bool>
+	Definition: Identifies the node as an interrupt controller.
+
+- reg:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: Specifies the base physical address to trigger an
+	interrupt into remote processor.
+
+-reg-names:
+	Usage: required
+	Value type: <string>, <string>
+	Definition: Specifies the address field names.
+
+- qcom,num-mpm-irqs:
+	Usage: optional
+	Value type: <value>
+	Defination: Specifies the number of interrupts supported.
+
+Example:
+
+wakegic: wake-gic@7781b8 {
+	compatible = "qcom,mpm", "qcom,mpm-gic-holi";
+	interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
+	reg = <0x601d4 0x1000>,
+	    <0xb011008 0x4>;  /* MSM_APCS_GCC_BASE 4K */
+	reg-names = "vmpm", "ipc";
+	interrupt-controller;
+	interrupt-parent = <&intc>;
+	#interrupt-cells = <3>;
+};
diff --git a/bindings/mailbox/qcom,apcs-kpss-global.yaml b/bindings/mailbox/qcom,apcs-kpss-global.yaml
index 447a6d16..8fc5c0c2 100644
--- a/bindings/mailbox/qcom,apcs-kpss-global.yaml
+++ b/bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -32,6 +32,7 @@ properties:
       - qcom,sm8150-apss-shared
       - qcom,sm8150-spcs-global
       - qcom,bengal-apcs-hmss-global
+      - qcom,monaco-apcs-hmss-global
   reg:
     maxItems: 1
 
diff --git a/bindings/pinctrl/qcom,monaco-pinctrl.yaml b/bindings/pinctrl/qcom,monaco-pinctrl.yaml
new file mode 100644
index 00000000..5093b6b4
--- /dev/null
+++ b/bindings/pinctrl/qcom,monaco-pinctrl.yaml
@@ -0,0 +1,187 @@
+Qualcomm Technologies, Inc. MONACO TLMM block
+
+This binding describes the Top Level Mode Multiplexer block found in the
+MONACO platform.
+
+- compatible:
+      Usage: required
+      Value type: <string>
+      Definition: must be "qcom,monaco-pinctrl"
+
+- reg:
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: the base address and size of the TLMM register space.
+
+- interrupts:
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: should specify the TLMM summary IRQ.
+
+- interrupt-controller:
+      Usage: required
+      Value type: <none>
+      Definition: identifies this node as an interrupt controller
+
+- #interrupt-cells:
+      Usage: required
+      Value type: <u32>
+      Definition: must be 2. Specifying the pin number and flags, as defined
+                  in <dt-bindings/interrupt-controller/irq.h>
+
+- gpio-controller:
+      Usage: required
+      Value type: <none>
+      Definition: identifies this node as a gpio controller
+
+- #gpio-cells:
+      Usage: required
+      Value type: <u32>
+      Definition: must be 2. Specifying the pin number and flags, as defined
+                  in <dt-bindings/gpio/gpio.h>
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+
+PIN CONFIGURATION NODES:
+
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+- pins:
+	Usage: required
+	Value type: <string-array>
+	Definition: List of gpio pins affected by the properties specified in
+		    this subnode.
+
+		    Valid pins are:
+		      gpio0-gpio112
+		        Supports mux, bias and drive-strength
+
+		      sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
+		      sdc2_data sdc1_rclk
+		        Supports bias and drive-strength
+
+- function:
+	Usage: required
+	Value type: <string>
+	Definition: Specify the alternative function to be configured for the
+		    specified pins. Functions are only valid for gpio pins.
+		    Valid values are:
+
+		    blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
+		    bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
+		    qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
+		    dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
+		    blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
+		    mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
+		    atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
+		    cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
+		    pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
+		    qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
+		    qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
+		    atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
+		    atest_usb20, atest_char0, dac_calib10, qdss_stm10,
+		    qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
+		    blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
+		    qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
+		    qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
+		    dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
+		    qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
+		    dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
+		    dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
+		    dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
+		    dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
+		    sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
+		    qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
+		    uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
+		    blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
+		    qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
+		    blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
+		    cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
+		    blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
+		    qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
+		    isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
+		    qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
+		    sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
+		    gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
+		    qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
+		    tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
+		    qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
+		    sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
+		    sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
+		    ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
+		    blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
+		    pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
+		    qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
+		    qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
+		    gpio
+
+- bias-disable:
+	Usage: optional
+	Value type: <none>
+	Definition: The specified pins should be configured as no pull.
+
+- bias-pull-down:
+	Usage: optional
+	Value type: <none>
+	Definition: The specified pins should be configured as pull down.
+
+- bias-pull-up:
+	Usage: optional
+	Value type: <none>
+	Definition: The specified pins should be configured as pull up.
+
+- output-high:
+	Usage: optional
+	Value type: <none>
+	Definition: The specified pins are configured in output mode, driven
+		    high.
+		    Not valid for sdc pins.
+
+- output-low:
+	Usage: optional
+	Value type: <none>
+	Definition: The specified pins are configured in output mode, driven
+		    low.
+		    Not valid for sdc pins.
+
+- drive-strength:
+	Usage: optional
+	Value type: <u32>
+	Definition: Selects the drive strength for the specified pins, in mA.
+		    Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+
+Example:
+
+    tlmm: pinctrl@500000 {
+      compatible = "qcom,monaco-pinctrl";
+      reg = <0x500000 0x300000>;
+      interrupts = <0 227 0>;
+      gpio-controller;
+      #gpio-cells = <2>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+    };
diff --git a/bindings/pinctrl/qcom,pmic-gpio.txt b/bindings/pinctrl/qcom,pmic-gpio.txt
index 200e5059..83877faf 100644
--- a/bindings/pinctrl/qcom,pmic-gpio.txt
+++ b/bindings/pinctrl/qcom,pmic-gpio.txt
@@ -51,6 +51,7 @@ PMIC's from Qualcomm.
 		    "qcom,pm8550vs-gpio"
 		    "qcom,pmk8550-gpio"
 		    "qcom,pmr735d-gpio"
+		    "qcom,pm5100-gpio"
 
 		    And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
 		    if the device is on an spmi bus or an ssbi bus respectively
@@ -155,6 +156,7 @@ to specify in a pin configuration subnode:
 		    gpio1-gpio6 for pm8550vs
 		    gpio1-gpio6 for pmk8550
 		    gpio1-gpio2 for pmr735d
+		    gpio1-gpio16 for pm5100
 
 - function:
 	Usage: required
diff --git a/bindings/power/supply/qcom/qcom,qbg.yaml b/bindings/power/supply/qcom/qcom,qbg.yaml
new file mode 100644
index 00000000..d5543d89
--- /dev/null
+++ b/bindings/power/supply/qcom/qcom,qbg.yaml
@@ -0,0 +1,120 @@
+Qualcomm Technologies, Inc. Battery Gauge (QBG) binding
+
+description: |
+  Qualcomm Technologies, Inc. Battery Gauge (QBG) uses the periodic samples of
+  battery voltage and current to determine the battery state-of-charge (SOC)
+  and supports other battery management features.
+
+properties:
+  compatible:
+    const: qcom,qbg
+
+  reg:
+    description: Base address of QBG MAIN peripheral.
+    maxItems: 1
+
+  interrupts:
+    description: Specifies the interrupts for nvmem devices used by QBG.
+    maxItems: 1
+
+  interrupt-names:
+    description: Specifies the interrupt names for nvmem devices used by QBG.
+    minItems: 1
+    items:
+      - const: qbg-sdam
+    $ref: /schemas/types.yaml#/definitions/string-array
+
+  qcom,num-data-sdams:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Number of SDAMs used for storing QBG FIFO data.
+
+  qcom,sdam-base:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Base address of QBG SDAM peripheral.
+
+  qcom,vbat-cutoff-mv:
+    allOf:
+      - $ref: "/schemas/types.yaml#/definitions/uint32"
+    description: The battery voltage threshold (in mV) at which the battery
+      power cuts off. The SOC is forced to 0 when battery voltage reaches
+      this value.
+    default: 3100
+
+  qcom,ibat-cutoff-ma:
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32
+    description: The battery current threshold (in mA) at which the battery
+      power cuts off. The SOC is forced to 0 when battery current reaches
+      this value.
+    default: 150
+
+  qcom,vph-min-mv:
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32
+    description: Minimum sustainable system power (in mV).
+    default: 2700
+
+  qcom,iterm-ma:
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32
+    description: The battery current (in mA) at which the QBG algorithm
+      converges the SOC to 100% during charging and can be used to terminate
+      charging.
+    default: 100
+
+  qcom,rconn-mohm:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Resistance of the battery connector in mOhms.
+
+  nvmem-cell-names:
+    minItems: 2
+    maxItems: 3
+    items:
+      - const: qbg_debug_mask_low
+      - const: qbg_debug_mask_high
+      - const: skip_esr_state
+
+  nvmem-cells:
+   minItems: 2
+   minItems: 3
+   description: |
+     Use nvmem cell device to indicate SDAM register.
+       qbg_debug_mask_low/qbg_debug_mask_high used to store the qbg debug mask
+       skip_esr_state used to get GPS de-modulating status
+
+required:
+  - compatible
+  - reg
+  - interrupt-names
+  - interrupts
+  - qcom,num-data-sdams
+  - qcom,sdam-base
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    spmi_bus {
+      #address-cells = <2>;
+      #size-cells = <0>;
+      interrupt-controller;
+      #interrupt-cells = <4>;
+
+      qcom,pm5100@0 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        qbg@4f00 {
+          compatible = "qcom,qbg";
+          reg = <0x4f00>;
+          #address-cells = <1>;
+          #size-cells = <1>;
+          interrupt-names = "qbg-sdam";
+          interrupts = <0x0 0x76 0x1 IRQ_TYPE_EDGE_RISING>;
+          qcom,num-data-sdams = <6>;
+          qcom,sdam-base = <0x7600>;
+          nvmem-cell-names = "qbg_debug_mask_low", "qbg_debug_mask_high";
+          nvmem-cells = <&qbg_debug_mask_low>, <&qbg_debug_mask_high>;
+        };
+      };
+    };
+...
diff --git a/bindings/power/supply/qcom/qpnp-smblite.txt b/bindings/power/supply/qcom/qpnp-smblite.txt
new file mode 100644
index 00000000..8f37a327
--- /dev/null
+++ b/bindings/power/supply/qcom/qpnp-smblite.txt
@@ -0,0 +1,379 @@
+Qualcomm Technologies, Inc. SMBLITE Charger Specific Bindings
+
+SMBLITE Charger is an efficient programmable battery charger capable of charging a
+lithium-ion battery over micro-USB or USB Type-C.
+
+=======================
+Required Node Structure
+=======================
+
+SMBLITE Charger must be described in two levels of devices nodes.
+
+===================================
+First Level Node - SMBLITE Charger
+===================================
+
+Charger specific properties:
+- compatible
+  Usage:      required
+  Value type: <string>
+  Definition: "qcom,qpnp-smblite" for SMBLITE on PM2250.
+	      "qcom,qpnp-pm5100-smblite" for SMBLITE on PM5100.
+
+- qcom,pmic-revid
+  Usage:      required
+  Value type: phandle
+  Definition: Should specify the phandle of PMI's revid module. This is used to
+		identify the PMI subtype.
+
+- io-channels
+- io-channel-names
+  Usage:      optional
+  Value type: <phandle>
+  Definition: For details about IIO bindings see:
+		Documentation/devicetree/bindings/iio/iio-bindings.txt
+
+- qcom,batteryless-platform
+  Usage:      optional
+  Value type: <empty>
+  Definition: Boolean flag which indicates that the platform does not have a
+		battery, and therefore charging should be disabled. In
+		addition battery properties will be faked such that the device
+		assumes normal operation.
+
+- qcom,fcc-max-ua
+  Usage:      optional
+  Value type: <u32>
+  Definition: Specifies the maximum fast charge current in micro-amps in
+		battery profile.
+		If the value is not present, 1Amp is used as default.
+
+- qcom,fv-max-uv
+  Usage:      optional
+  Value type: <u32>
+  Definition: Specifies the maximum float voltage in micro-volts in
+		battery profile.
+		If the value is not present, 4.35V is used as default.
+
+- qcom,usb-icl-ua
+  Usage:      optional
+  Value type: <u32>
+  Definition: Specifies the USB input current limit in micro-amps.
+		 If the value is not present, 1.5Amps is used as default.
+
+- qcom,thermal-mitigation
+  Usage:      optional
+  Value type: Array of <u32>
+  Definition: Array of fast charge current limit values for
+		different system thermal mitigation levels.
+		This should be a flat array that denotes the
+		maximum charge current in mA for each thermal
+		level.
+
+- qcom,chg-inhibit-threshold-mv
+  Usage:      optional
+  Value type: <u32>
+  Definition: Charge inhibit threshold in milli-volts. Charging will be
+		inhibited when the battery voltage is within this threshold
+		from Vfloat at charger insertion. If this is not specified
+		then charge inhibit will be disabled by default.
+		Allowed values are: 50, 100, 200, 300.
+
+- qcom,chg-term-src
+  Usage:      optional
+  Value type: <u32>
+  Definition: Specify either the ADC or analog comparators to be used in order
+		to set threshold values for charge termination current.
+		0 - Unspecified
+		1 - Select ADC comparator
+		2 - Select ANALOG comparator
+
+- qcom,chg-term-current-ma
+  Usage:      optional
+  Value type: <u32>
+  Definition: When ADC comparator is selected as qcom,chg-term-src, this
+		parameter should be set to the desired upper threshold.
+
+- qcom,chg-term-base-current-ma
+  Usage:      optional
+  Value type: <u32>
+  Definition: When ADC comparator is selected as qcom,chg-term-src, this
+		parameter should be set to the desired lower threshold.
+
+- qcom,auto-recharge-soc
+  Usage:      optional
+  Value type: <u32>
+  Definition: Specifies the SOC threshold at which the charger will
+		restart charging after termination. The value specified
+		ranges from 0 - 100. The feature is enabled if this
+		property is specified with a valid SOC value.
+
+- qcom,auto-recharge-vbat-mv
+  Usage:      optional
+  Value type: <u32>
+  Definition: Specifies the battery voltage threshold at which the charger
+		will restart charging after termination. The value specified
+		is in milli-volts.
+
+- qcom,suspend-input-on-debug-batt
+  Usage:      optional
+  Value type: <empty>
+  Definition: Boolean flag which when present enables input suspend for
+		debug battery.
+
+- qcom,fake-chg-status-on-debug-batt
+  Usage:      optional
+  Value type: <empty>
+  Definition: Boolean flag which when present shows charging status as
+		unknown for debug battery. This needs to be specified only if
+		the device needs to be kept powered on always with
+		"svc power stayon true".
+
+- qcom,typec-legacy-rp-icl
+  Usage:       optional
+  Value type:  bool
+  Definition:  Boolean property to enable setting ICL based on Rp for
+		Type-C non-compliant legacy cables.
+
+- qcom,wd-bark-time-secs
+  Usage:      optional
+  Value type: <u32>
+  Definition: WD bark-timeout in seconds. The possible values are
+		16, 32, 64, 128. If not defined it defaults to 64.
+
+- qcom,battery-data
+  Usage:      optional
+  Value type: <phandle>
+  Definition: Specifies the phandle of the node which contains the battery
+		profiles supported on the device.
+
+- qcom,flash-derating-soc
+  Usage:      optional
+  Value type: <u32>
+  Definition: SOC threshold in percentage below which hardware will start
+		derating flash. This is only applicable to certain PMICs like
+		PMI632 which has SCHGM_FLASH peripheral.
+
+- qcom,flash-disable-soc
+  Usage:      optional
+  Value type: <u32>
+  Definition: SOC threshold in percentage below which hardware will disable
+		flash. This is only applicable to certain PMICs like PMI632
+		which has SCHGM_FLASH peripheral.
+
+- qcom,headroom-mode
+  Usage:      optional
+  Value type: <u32>
+  Definition: Specifies flash hardware headroom management policy. The
+		possible values are:
+		<0>: Fixed mode, constant 5V at flash input.
+		<1>: Adaptive mode allows charger output voltage to be
+		dynamically controlled by the flash module based on the
+		required flash headroom.
+		This is only applicable to certain PMICs like PMI632 which
+		has SCHGM_FLASH peripheral.
+
+- nvmem-cell-names
+  Usage:      optional
+  Value type: <string>
+  Definition: The nvmem cell device name of the SDAM register used to store
+		the charger debug mask. It must be "charger_debug_mask".
+
+- nvmem-cells
+  Usage:      optional
+  Value type: <phandle>
+  Definition: Phandle of the nvmem cell device used to store the charger debug
+		mask. Please refer to nvmem bindings as described in
+		bindings/nvmem/nvmem.txt.
+
+- qcom,fcc-stepping-enable
+  Usage:      optional
+  Value type: bool
+  Definition: Boolean flag which when present enables stepwise change in FCC.
+		The default stepping rate is 100mA/sec.
+
+- qcom,disable-suspend-on-collapse
+  Usage:      optional
+  Value type: bool
+  Definition: Boolean flag which when present disables suspend on collapse
+		feature of charger hardware.
+
+- qcom,fcc-step-delay-ms
+  Usage:      optional
+  Value type: <u32>
+  Definition: Specifies the delay between each step of FCC stepper algorithm.
+		If left unspecified, the default value is 1 Sec.
+
+- qcom,fcc-step-size-ua
+  Usage:      optional
+  Value type: <u32>
+  Definition: Specifies the step size of each step of FCC stepper algorithm.
+		If left unspecified, the default value is 100mA.
+
+- qcom,fc-step-start-ua
+  Usage:     optional
+  Value type: <u32>
+  Definition: Specifies the initial current of FCC stepper algorithm.
+		If left unspecified, the default value is 500mA.
+
+- qcom,concurrency-mode-enable
+ Usage:      optional
+ Value type: bool
+ Definition: Boolean flag to control charger concurrency mode. Its supported
+		only on PM5100, By default this feature is disabled.
+
+- qcom,remote-fg
+ Usage:      optional
+ Value type: bool
+ Definition: Boolean flag to determine if FG is running on different processor.
+		Its supported only on PM5100, By default this feature is disabled.
+
+- qcom,float-option
+  Usage:      optional
+  Value type: <u32>
+  Definition: Configures how the charger behaves when a float charger is
+	      detected by APSD.
+	        1 - Treat as a DCP.
+	        2 - Treat as a SDP.
+	        3 - Disable charging.
+	        4 - Suspend USB input.
+
+=================================================
+Second Level Nodes - SMBLITE Charger Peripherals
+=================================================
+
+Peripheral specific properties:
+- reg
+  Usage:      required
+  Value type: <prop-encoded-array>
+  Definition: Address and size of the peripheral's register block.
+
+- interrupts
+  Usage:      required
+  Value type: <prop-encoded-array>
+  Definition: Peripheral interrupt specifier.
+
+- interrupt-names
+  Usage:      required
+  Value type: <stringlist>
+  Definition: Interrupt names.  This list must match up 1-to-1 with the
+	      interrupts specified in the 'interrupts' property.
+
+=======
+Example
+=======
+
+pm2250_charger: qcom,qpnp-smblite {
+	compatible = "qcom,qpnp-smblite";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	#cooling-cells = <2>;
+
+	nvmem-cell-names = "charger_debug_mask";
+	nvmem-cells = <&charger_debug_mask>;
+
+	qcom,pmic-revid = <&pm2250_revid>;
+	qcom,chgr@1000 {
+		reg = <0x1000 0x100>;
+		interrupts =
+			<0x0 0x10 0x1 IRQ_TYPE_EDGE_RISING>,
+			<0x0 0x10 0x0 IRQ_TYPE_EDGE_RISING>,
+			<0x0 0x10 0x4 IRQ_TYPE_EDGE_RISING>,
+			<0x0 0x10 0x7 IRQ_TYPE_EDGE_RISING>;
+
+		interrupt-names = "chgr-error",
+			"chg-state-change",
+			"buck-oc",
+			"vph-ov";
+	};
+
+	qcom,dcdc@1100 {
+		reg = <0x1100 0x100>;
+		interrupts =
+			<0x0 0x11 0x0 IRQ_TYPE_EDGE_RISING>,
+			<0x0 0x11 0x1 IRQ_TYPE_EDGE_RISING>,
+			<0x0 0x11 0x2 IRQ_TYPE_EDGE_RISING>,
+			<0x0 0x11 0x6 IRQ_TYPE_EDGE_RISING>,
+			<0x0 0x11 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+		interrupt-names = "otg-fail",
+			"otg-fault",
+			"skip-mode",
+			"input-current-limiting",
+			"switcher-power-ok";
+	};
+
+	qcom,batif@1200 {
+		reg = <0x1200 0x100>;
+		interrupts =
+			<0x0 0x12 0x0 IRQ_TYPE_EDGE_BOTH>,
+			<0x0 0x12 0x1 IRQ_TYPE_EDGE_BOTH>,
+			<0x0 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
+			<0x0 0x12 0x3 IRQ_TYPE_EDGE_BOTH>,
+			<0x0 0x12 0x4 IRQ_TYPE_EDGE_RISING>;
+
+		interrupt-names = "bat-temp",
+			"bat-therm-or-id-missing",
+			"bat-low",
+			"bat-ov",
+			"bsm-active";
+	};
+
+	qcom,usb@1300 {
+		reg = <0x1300 0x100>;
+		interrupts =
+			<0x0 0x13 0x0 IRQ_TYPE_EDGE_BOTH>,
+			<0x0 0x13 0x1 IRQ_TYPE_EDGE_BOTH>,
+			<0x0 0x13 0x2 IRQ_TYPE_EDGE_BOTH>,
+			<0x0 0x13 0x3 IRQ_TYPE_EDGE_BOTH>,
+			<0x0 0x13 0x4 IRQ_TYPE_EDGE_RISING>,
+			<0x0 0x13 0x6 IRQ_TYPE_EDGE_RISING>;
+
+		interrupt-names = "usbin-plugin",
+			"usbin-collapse",
+			"usbin-uv",
+			"usbin-ov",
+			"usbin-gtvt",
+			"usbin-icl-change";
+	};
+
+	qcom,typec@1500 {
+		reg = <0x1500 0x100>;
+		interrupts =
+			<0x0 0x15 0x0 IRQ_TYPE_EDGE_BOTH>,
+			<0x0 0x15 0x1 IRQ_TYPE_EDGE_BOTH>,
+			<0x0 0x15 0x2 IRQ_TYPE_EDGE_RISING>,
+			<0x0 0x15 0x4 IRQ_TYPE_EDGE_BOTH>,
+			<0x0 0x15 0x5 IRQ_TYPE_EDGE_RISING>,
+			<0x0 0x15 0x6 IRQ_TYPE_EDGE_RISING>,
+			<0x0 0x15 0x7 IRQ_TYPE_EDGE_RISING>;
+
+		interrupt-names = "typec-or-rid-detect-change",
+			"typec-vpd-detect",
+			"typec-cc-state-change",
+			"typec-vbus-change",
+			"typec-attach-detach",
+			"typec-legacy-cable-detect",
+			"typec-try-snk-src-detect";
+	};
+
+	qcom,misc@1600 {
+		reg = <0x1600 0x100>;
+		interrupts =
+			<0x0 0x16 0x0 IRQ_TYPE_EDGE_RISING>,
+			<0x0 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
+			<0x0 0x16 0x2 IRQ_TYPE_EDGE_RISING>,
+			<0x0 0x16 0x3 IRQ_TYPE_EDGE_RISING>,
+			<0x0 0x16 0x4 IRQ_TYPE_EDGE_RISING>,
+			<0x0 0x16 0x5 IRQ_TYPE_EDGE_RISING>,
+			<0x0 0x16 0x6 IRQ_TYPE_EDGE_BOTH>;
+
+		interrupt-names = "wdog-snarl",
+			"wdog-bark",
+			"aicl-fail",
+			"aicl-done",
+			"imp-trigger",
+			"all-chnl-cond-done",
+			"temp-change";
+	};
+};
diff --git a/bindings/soc/qcom/qcom,power-state.txt b/bindings/soc/qcom/qcom,power-state.txt
new file mode 100644
index 00000000..e0900417
--- /dev/null
+++ b/bindings/soc/qcom/qcom,power-state.txt
@@ -0,0 +1,20 @@
+* Qualcomm Technologies, Inc. Power State Driver
+
+This binding describes the Qualcomm Technologies, Inc. Power State Driver. Power
+State creates power_state device node for user space communication. User space
+client can open device node for communication and driver accordingly handles the
+request.
+
+Required Properties:
+
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: must be "qcom,power-state"
+
+Example:
+
+	qcom,power-state {
+		compatible = "qcom,power-state";
+	};
+
diff --git a/bindings/thermal/qcom,bcl-off-cdev.txt b/bindings/thermal/qcom,bcl-off-cdev.txt
new file mode 100644
index 00000000..0751f83d
--- /dev/null
+++ b/bindings/thermal/qcom,bcl-off-cdev.txt
@@ -0,0 +1,37 @@
+Qualcomm Technologies, Inc. BCL OFF cooling device
+
+The BCL OFF cooling device, will be used to disable PMIC bcl.
+This cooling device will be called when modem RF calibration
+is performed using external power supply.
+
+When external power supply is used for RF calibration, ibat current
+can cross the battery specs and can trigger batfet issues. So pmic bcl
+should be disabled as it is for protection for battery not external
+power supply.
+
+
+Required Parameters:
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: should be "qcom,bcl-off"
+
+- reg:
+	Usage: optional
+	Value type: <a b>
+	Definition: where 'a' is the starting register address of the PMIC
+	peripheral and 'b' is the size of the peripheral address space.
+
+- #cooling-cells:
+	Usage: required
+	Value type: <integer>
+	Definition: Must be 2. This is required by of-thermal and refer the doc
+		<devicetree/bindings/thermal/thermal.txt> for more details.
+
+Example:
+
+	bcl_off: bcl-off {
+		compatible = "qcom,bcl-off";
+		reg = <0x4700 0x100>;
+		#cooling-cells = <2>;
+	};
diff --git a/qcom/Makefile b/qcom/Makefile
index c50f3a10..297ca423 100644
--- a/qcom/Makefile
+++ b/qcom/Makefile
@@ -83,6 +83,18 @@ khaje-dtb-$(CONFIG_ARCH_KHAJE) += \
 khaje-overlays-dtb-$(CONFIG_ARCH_KHAJE) += $(KHAJE_BOARDS) $(KHAJE_BASE_DTB)
 dtb-y += $(khaje-dtb-y)
 
+MONACO_BASE_DTB += monaco.dtb monacop.dtb
+
+MONACO_BOARDS += \
+        monaco-idp-v1-overlay.dtbo \
+        monaco-idp-v2-overlay.dtbo \
+        monaco-idp-v3-overlay.dtbo
+
+monaco-dtb-$(CONFIG_ARCH_MONACO) += \
+        $(call add-overlays, $(MONACO_BOARDS) ,$(MONACO_BASE_DTB))
+monaco-overlays-dtb-$(CONFIG_ARCH_MONACO) += $(MONACO_BOARDS) $(MONACO_BASE_DTB)
+dtb-y += $(monaco-dtb-y)
+
 cinder-dtb-$(CONFIG_ARCH_CINDER) += cinder-ru-rumi.dtb \
 	cinder-du-rumi.dtb \
 	cinder-ru-idp.dtb \
diff --git a/qcom/monaco-coresight.dtsi b/qcom/monaco-coresight.dtsi
new file mode 100644
index 00000000..df3db582
--- /dev/null
+++ b/qcom/monaco-coresight.dtsi
@@ -0,0 +1,1840 @@
+&soc {
+	hwevent {
+		compatible = "qcom,coresight-hwevent";
+
+		coresight-name = "coresight-hwevent";
+		coresight-csr = <&csr>;
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	apss_tgu: tgu@9900000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b999>;
+		reg = <0x09900000 0x1000>;
+		reg-names = "tgu-base";
+		tgu-steps = <3>;
+		tgu-conditions = <4>;
+		tgu-regs = <8>;
+		tgu-timer-counters = <3>;
+		interrupts = <0 53 1>, <0 54 1>, <0 55 1>, <0 56 1>;
+		coresight-name = "coresight-tgu-apss";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	csr: csr@8001000 {
+		compatible = "qcom,coresight-csr";
+		reg = <0x8001000 0x1000>;
+		reg-names = "csr-base";
+
+		coresight-name = "coresight-csr";
+		qcom,usb-bam-support;
+		qcom,hwctrl-set-support;
+		qcom,set-byte-cntr-support;
+		qcom,perflsheot-set-support;
+
+		qcom,blk-size = <1>;
+		qcom,flushperiod = <8>;
+	};
+
+	swao_csr: csr@8a03000 {
+		compatible = "qcom,coresight-csr";
+		reg = <0x8a03000 0x1000>;
+		reg-names = "csr-base";
+
+		coresight-name = "coresight-swao-csr";
+
+		qcom,timestamp-support;
+		qcom,aodbg-csr-support;
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		qcom,blk-size = <1>;
+	};
+
+	stm: stm@8002000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb962>;
+
+		reg = <0x8002000 0x1000>,
+		      <0xe280000 0x180000>;
+		reg-names = "stm-base", "stm-stimulus-base";
+
+		coresight-name = "coresight-stm";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				stm_out_funnel_in0: endpoint {
+					remote-endpoint = <&funnel_in0_in_stm>;
+				};
+			};
+		};
+	};
+
+	tpdm_center: tpdm@8b58000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x8b58000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-center";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+		out-ports {
+			port {
+				tpdm_dl_ct_out_tpda0: endpoint {
+					remote-endpoint =
+					<&tpda0_in_tpdm_dl_ct>;
+				};
+			};
+		};
+	};
+
+	tpdm_gpu: tpdm@8940000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x8940000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-gpu";
+
+		status = "disabled";
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+		out-ports {
+			port {
+				tpdm_gpu_out_funnel_gpu: endpoint {
+					remote-endpoint =
+					<&funnel_gpu_in_tpdm_gpu>;
+				};
+			};
+		};
+	};
+
+	modem_rfxe: modem_rfxe {
+		compatible = "qcom,coresight-dummy";
+
+		coresight-name = "coresight-modem-rfxe";
+		qcom,dummy-source;
+		out-ports {
+			port {
+				modem_rxfe_out_funnel_in1: endpoint {
+					remote-endpoint =
+					<&funnel_in1_in_modem_rxfe>;
+				};
+			};
+		};
+	};
+
+	audio_etm0: audio_etm0 {
+		compatible = "qcom,coresight-remote-etm";
+		coresight-name = "coresight-audio-etm0";
+
+		qcom,inst-id = <5>;
+		out-ports {
+			port {
+				audio_etm0_out_funnel_lpass: endpoint {
+					remote-endpoint =
+					<&funnel_lpass_in_audio_etm0>;
+				};
+			};
+		};
+	};
+
+	snoc: snoc {
+		compatible = "qcom,coresight-dummy";
+		coresight-name = "coresight-snoc";
+
+		qcom,dummy-source;
+
+		out-ports {
+			port {
+				snoc_out_funnel_in0: endpoint {
+					remote-endpoint =
+					<&funnel_in0_in_snoc>;
+				};
+			};
+		};
+	};
+
+	tpdm_lpass: tpdm@8a26000 {
+		compatible = "qcom,coresight-dummy";
+
+		coresight-name = "coresight-tpdm-lpass";
+		qcom,dummy-source;
+		out-ports {
+			port {
+				tpdm_lpass_out_funnel_lpass: endpoint {
+					remote-endpoint =
+					<&funnel_lpass_in_tpdm_lpass>;
+				};
+			};
+		};
+	};
+
+	tpdm_ddr0: tpdm@8a50000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x8a50000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-ddr";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		status = "disabled";
+		out-ports {
+			port {
+				tpdm_ddr0_out_funnel_ddr: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_in_tpdm_ddr0>;
+				};
+			};
+		};
+	};
+
+	tpdm_ddr1: tpdm@8a51000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x8a51000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-shrm";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		status = "disabled";
+		out-ports {
+			port {
+				tpdm_ddr1_out_funnel_ddr: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_in_tpdm_ddr1>;
+				};
+			};
+		};
+	};
+
+	tpdm_vsense: tpdm@8840000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x8840000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-vsense";
+
+		status = "disabled";
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+		out-ports {
+			port {
+				tpdm_vsense_out_tpda15: endpoint {
+					remote-endpoint =
+					<&tpda15_in_tpdm_vsense>;
+				};
+			};
+		};
+	};
+
+	tpdm_dcc: tpdm@8870000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x8870000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-dcc";
+
+		qcom,hw-enable-check;
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		qcom,cmb-msr-skip;
+		out-ports {
+			port {
+				tpdm_dcc_out_tpda12: endpoint {
+					remote-endpoint =
+					<&tpda12_in_tpdm_dcc>;
+				};
+			};
+		};
+	};
+
+	tpdm_prng: tpdm@884c000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x884c000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-prng";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		qcom,cmb-msr-skip;
+		out-ports {
+			port {
+				tpdm_prng_out_tpda14: endpoint {
+					remote-endpoint =
+					<&tpda14_in_tpdm_prng>;
+				};
+			};
+		};
+	};
+
+	tpdm_qm: tpdm@89d0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x89d0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-qm";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+		out-ports {
+			port {
+				tpdm_qm_out_tpda16: endpoint {
+					remote-endpoint =
+					<&tpda16_in_tpdm_qm>;
+				};
+			};
+		};
+	};
+
+	tpdm_west: tpdm@8a58000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x8a58000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-west";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+		out-ports {
+			port {
+				tpdm_west_out_tpda17: endpoint {
+					remote-endpoint =
+					<&tpda17_in_tpdm_west>;
+				};
+			};
+		};
+	};
+
+	tpdm_pimem: tpdm@8850000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x8850000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-pimem";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		qcom,cmb-msr-skip;
+		out-ports {
+			port {
+				tpdm_pimem_out_tpda21: endpoint {
+					remote-endpoint =
+					<&tpda21_in_tpdm_pimem>;
+				};
+			};
+		};
+	};
+
+	tpdm_mapss: tpdm@8a01000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x8a01000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-mapss";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		qcom,cmb-msr-skip;
+		out-ports {
+			port {
+				tpdm_mapss_out_tpda_mapss: endpoint {
+					remote-endpoint =
+					<&tpda_mapss_in_tpdm_mapss>;
+				};
+			};
+		};
+	};
+
+	tpdm_sdcc_2: tpdm@89b9000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x89b9000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-sdcc-2";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		qcom,cmb-msr-skip;
+		status = "disabled";
+		out-ports {
+			port {
+				tpdm_sdcc2_out_tpda20: endpoint {
+					remote-endpoint =
+					<&tpda20_in_tpdm_sdcc2>;
+				};
+			};
+		};
+	};
+
+	tpdm_sdcc_1: tpdm@89b8000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x89b8000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-sdcc-1";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		qcom,cmb-msr-skip;
+		status = "disabled";
+		out-ports {
+			port {
+				tpdm_sdcc1_out_tpda19: endpoint {
+					remote-endpoint =
+					<&tpda19_in_tpdm_sdcc1>;
+				};
+			};
+		};
+	};
+
+	tpdm_spdm: tpdm@800f000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x800f000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-spdm";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		qcom,cmb-msr-skip;
+		out-ports {
+			port {
+				tpdm_spdm_out_tpda18: endpoint {
+					remote-endpoint =
+					<&tpda18_in_tpdm_spdm>;
+				};
+			};
+		};
+	};
+
+	tpdm_wcss: tpdm@899c000 {
+		compatible = "qcom,coresight-dummy";
+		coresight-name = "coresight-tpdm-wcss";
+		qcom,dummy-source;
+
+		out-ports {
+			port {
+				tpdm_wcss_out_funnel_wcss: endpoint {
+					remote-endpoint =
+					<&funnel_wcss_in_tpdm_wcss>;
+				};
+			};
+		};
+	};
+
+	funnel_wcss: funnel@899e000 {
+		compatible = "arm,coresight-static-funnel";
+		coresight-name = "coresight-funnel-wcss";
+
+		out-ports {
+			port {
+				funnel_wcss_out_funnel_in1: endpoint {
+					remote-endpoint =
+					<&funnel_in1_in_funnel_wcss>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@1 {
+				reg = <1>;
+				funnel_wcss_in_tpdm_wcss: endpoint {
+					remote-endpoint =
+					<&tpdm_wcss_out_funnel_wcss>;
+				};
+			};
+		};
+	};
+
+	modem_etm0: modem_etm0 {
+		compatible = "qcom,coresight-remote-etm";
+		coresight-name = "coresight-modem-etm0";
+
+		qcom,inst-id = <2>;
+
+		out-ports {
+			port {
+				modem_etm0_out_funnel_in1: endpoint {
+					remote-endpoint =
+					<&funnel_in1_in_modem_etm0>;
+				};
+			};
+		};
+	};
+
+	etm0: etm@9040000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+		reg = <0x9040000 0x1000>;
+		cpu = <&CPU0>;
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm0";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+		out-ports {
+			port {
+				etm0_out_funnel_apss0: endpoint {
+					remote-endpoint =
+					<&funnel_apss0_in_etm0>;
+				};
+			};
+		};
+	};
+
+	etm1: etm@9140000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+		reg = <0x9140000 0x1000>;
+		cpu = <&CPU1>;
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm1";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+		out-ports {
+			port {
+				etm1_out_funnel_apss0: endpoint {
+					remote-endpoint =
+					<&funnel_apss0_in_etm1>;
+				};
+			};
+		};
+	};
+
+	etm2: etm@9240000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+		reg = <0x9240000 0x1000>;
+		cpu = <&CPU2>;
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm2";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+		out-ports {
+			port {
+				etm2_out_funnel_apss0: endpoint {
+					remote-endpoint =
+					<&funnel_apss0_in_etm2>;
+				};
+			};
+		};
+	};
+
+	etm3: etm@9340000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+		reg = <0x9340000 0x1000>;
+		cpu = <&CPU3>;
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm3";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+		out-ports {
+			port {
+				etm3_out_funnel_apss0: endpoint {
+					remote-endpoint =
+					<&funnel_apss0_in_etm3>;
+				};
+			};
+		};
+	};
+
+	tpdm_actpm: tpd@9830000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x9830000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-actpm";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		qcom,cmb-msr-skip;
+		out-ports {
+			port {
+				tpdm_actpm_out_tpda_actpm: endpoint {
+					remote-endpoint =
+					<&tpda_actpm_in_tpdm_actpm>;
+				};
+			};
+		};
+	};
+
+	tpdm_llm_silver: tpdm@98a0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x98a0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-llm-silver";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		qcom,cmb-msr-cnt = <12>;
+		out-ports {
+			port {
+				tpdm_llm_silver_out_tpda_llm_silver: endpoint {
+					remote-endpoint =
+					<&tpda_llm_silver_in_tpdm_llm_silver>;
+				};
+			};
+		};
+	};
+
+	tpdm_apss: tpdm@9860000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x9860000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-apss";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+		out-ports {
+			port {
+				tpdm_apss_out_tpda_apss: endpoint {
+					remote-endpoint =
+					<&tpda_apss_in_tpdm_apss>;
+				};
+			};
+		};
+	};
+
+	funnel_apss0: funnel@9800000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x9800000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-apss0";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				funnel_apss0_out_funnel_in1: endpoint {
+					remote-endpoint =
+					<&funnel_in1_in_funnel_apss0>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_apss0_in_etm0: endpoint {
+					remote-endpoint =
+					<&etm0_out_funnel_apss0>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_apss0_in_etm1: endpoint {
+					remote-endpoint =
+					<&etm1_out_funnel_apss0>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				funnel_apss0_in_etm2: endpoint {
+					remote-endpoint =
+					<&etm2_out_funnel_apss0>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				funnel_apss0_in_etm3: endpoint {
+					remote-endpoint =
+					<&etm3_out_funnel_apss0>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				funnel_apss0_in_tpda_actpm: endpoint {
+					remote-endpoint =
+					<&tpda_actpm_out_funnel_apss0>;
+				};
+			};
+
+			port@5 {
+				reg = <5>;
+				funnel_apss0_in_tpda_llm_silver: endpoint {
+					remote-endpoint =
+					<&tpda_llm_silver_out_funnel_apss0>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				funnel_apss0_in_tpda_apss: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&tpda_apss_out_funnel_apss0>;
+				};
+			};
+		};
+	};
+
+	tpda_actpm: tpda@9832000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x9832000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-actpm";
+
+		qcom,tpda-atid = <77>;
+		qcom,cmb-elem-size = <0 32>;
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpda_actpm_out_funnel_apss0: endpoint {
+					remote-endpoint =
+					<&funnel_apss0_in_tpda_actpm>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				tpda_actpm_in_tpdm_actpm: endpoint {
+					remote-endpoint =
+					<&tpdm_actpm_out_tpda_actpm>;
+				};
+			};
+		};
+	};
+
+	tpda_apss: tpda@9862000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x9862000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-apss";
+
+		qcom,tpda-atid = <66>;
+		qcom,dsb-elem-size = <0 32>;
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpda_apss_out_funnel_apss0: endpoint {
+					remote-endpoint =
+					<&funnel_apss0_in_tpda_apss>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				tpda_apss_in_tpdm_apss: endpoint {
+					remote-endpoint =
+					<&tpdm_apss_out_tpda_apss>;
+				};
+			};
+		};
+	};
+
+
+	tpda_llm_silver: tpda@98c0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x98c0000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-llm-silver";
+
+		qcom,tpda-atid = <72>;
+		qcom,cmb-elem-size = <0 32>;
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpda_llm_silver_out_funnel_apss0: endpoint {
+					remote-endpoint =
+					<&funnel_apss0_in_tpda_llm_silver>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				tpda_llm_silver_in_tpdm_llm_silver: endpoint {
+					remote-endpoint =
+					<&tpdm_llm_silver_out_tpda_llm_silver>;
+				};
+			};
+		};
+	};
+
+	tpda_mapss: tpda@8a04000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x8a04000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-mapss";
+
+		qcom,tpda-atid = <76>;
+		qcom,cmb-elem-size = <0 32>;
+		qcom,dsb-elem-size = <0 32>;
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpda_mapss_out_funnel_in1: endpoint {
+					remote-endpoint =
+					<&funnel_in1_in_tpda_mapss>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tpda_mapss_in_tpdm_mapss: endpoint {
+					remote-endpoint =
+					<&tpdm_mapss_out_tpda_mapss>;
+				};
+			};
+
+		};
+	};
+
+
+	funnel_gpu: funnel@8944000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x8944000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-gpu";
+		status = "disabled";
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				funnel_gpu_out_tpda1: endpoint {
+					remote-endpoint =
+					<&tpda1_in_funnel_gpu>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				funnel_gpu_in_tpdm_gpu: endpoint {
+					remote-endpoint =
+					<&tpdm_gpu_out_funnel_gpu>;
+				};
+			};
+
+		};
+	};
+
+	tpda: tpda@8004000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x8004000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda";
+
+		qcom,tpda-atid = <65>;
+		qcom,dsb-elem-size = <0 32>,
+						<1 32>,
+						<16 32>,
+						<17 32>;
+
+		qcom,cmb-elem-size = <6 32>,
+						<7 32>,
+						<12 32>,
+						<14 32>,
+						<15 32>,
+						<18 32>,
+						<19 32>,
+						<20 32>,
+						<21 32>;
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpda_out_funnel_qatb: endpoint {
+					remote-endpoint =
+					<&funnel_qatb_in_tpda>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tpda0_in_tpdm_dl_ct: endpoint {
+					remote-endpoint =
+					<&tpdm_dl_ct_out_tpda0>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				tpda1_in_funnel_gpu: endpoint {
+					remote-endpoint =
+					<&funnel_gpu_out_tpda1>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				tpda6_in_funnel_ddr: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_out_tpda6>;
+				};
+			};
+
+			port@7 {
+				reg = <7>;
+				tpda7_in_funnel_ddr: endpoint {
+					remote-endpoint =
+					<&funnel_ddr_out_tpda7>;
+				};
+			};
+
+			port@12 {
+				reg = <12>;
+				tpda12_in_tpdm_dcc: endpoint {
+					remote-endpoint =
+					<&tpdm_dcc_out_tpda12>;
+				};
+			};
+
+			port@14 {
+				reg = <14>;
+				tpda14_in_tpdm_prng: endpoint {
+					remote-endpoint =
+					<&tpdm_prng_out_tpda14>;
+				};
+			};
+
+			port@15 {
+				reg = <15>;
+				tpda15_in_tpdm_vsense: endpoint {
+					remote-endpoint =
+					<&tpdm_vsense_out_tpda15>;
+				};
+			};
+
+			port@16 {
+				reg = <16>;
+				tpda16_in_tpdm_qm: endpoint {
+					remote-endpoint =
+					<&tpdm_qm_out_tpda16>;
+				};
+			};
+
+			port@17 {
+				reg = <17>;
+				tpda17_in_tpdm_west: endpoint {
+					remote-endpoint =
+					<&tpdm_west_out_tpda17>;
+				};
+			};
+
+			port@18 {
+				reg = <18>;
+				tpda18_in_tpdm_spdm: endpoint {
+					remote-endpoint =
+					<&tpdm_spdm_out_tpda18>;
+				};
+			};
+
+			port@19 {
+				reg = <19>;
+				tpda19_in_tpdm_sdcc1: endpoint {
+					remote-endpoint =
+					<&tpdm_sdcc1_out_tpda19>;
+				};
+			};
+
+			port@20 {
+				reg = <20>;
+				tpda20_in_tpdm_sdcc2: endpoint {
+					remote-endpoint =
+					<&tpdm_sdcc2_out_tpda20>;
+				};
+			};
+
+			port@21 {
+				reg = <21>;
+				tpda21_in_tpdm_pimem: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&tpdm_pimem_out_tpda21>;
+				};
+			};
+		};
+	};
+
+	funnel_qatb: funnel@8005000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x8005000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-qatb";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				funnel_qatb_out_funnel_in0: endpoint {
+					remote-endpoint =
+					<&funnel_in0_in_funnel_qatb>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				funnel_qatb_in_tpda: endpoint {
+					remote-endpoint =
+					<&tpda_out_funnel_qatb>;
+				};
+			};
+
+			port@5 {
+				reg = <5>;
+				funnel_qatb_in_funnel_lpass: endpoint {
+					remote-endpoint =
+					<&funnel_lpass_out_funnel_qatb>;
+				};
+			};
+		};
+	};
+
+	funnel_in0: funnel@8041000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x8041000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-in0";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				funnel_in0_out_funnel_merg: endpoint {
+					remote-endpoint =
+					<&funnel_merg_in_funnel_in0>;
+				};
+			};
+		};
+
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@5 {
+				reg = <5>;
+				funnel_in0_in_snoc: endpoint {
+					remote-endpoint =
+					<&snoc_out_funnel_in0>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				funnel_in0_in_funnel_qatb: endpoint {
+					remote-endpoint =
+					<&funnel_qatb_out_funnel_in0>;
+				};
+			};
+
+			port@7 {
+				reg = <7>;
+				funnel_in0_in_stm: endpoint {
+					remote-endpoint =
+					<&stm_out_funnel_in0>;
+				};
+			};
+
+		};
+	};
+
+	funnel_in1: funnel@8042000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x8042000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-in1";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				funnel_in1_out_funnel_merg: endpoint {
+					remote-endpoint =
+					<&funnel_merg_in_funnel_in1>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				funnel_in1_in_tpda_mapss: endpoint {
+					remote-endpoint =
+					<&tpda_mapss_out_funnel_in1>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				funnel_in1_in_modem_rxfe: endpoint {
+					remote-endpoint =
+					<&modem_rxfe_out_funnel_in1>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				funnel_in1_in_funnel_wcss: endpoint {
+					remote-endpoint =
+					<&funnel_wcss_out_funnel_in1>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				funnel_in1_in_modem_etm0: endpoint {
+					remote-endpoint =
+					<&modem_etm0_out_funnel_in1>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				funnel_in1_in_funnel_apss0: endpoint {
+					remote-endpoint =
+					<&funnel_apss0_out_funnel_in1>;
+				};
+			};
+
+		};
+	};
+
+	funnel_lpass: funnel@8a24000 {
+		compatible = "arm,coresight-static-funnel";
+		coresight-name = "coresight-funnel-lpass";
+
+		out-ports {
+			port {
+				funnel_lpass_out_funnel_qatb: endpoint {
+					remote-endpoint =
+					<&funnel_qatb_in_funnel_lpass>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_lpass_in_audio_etm0: endpoint {
+					remote-endpoint =
+					<&audio_etm0_out_funnel_lpass>;
+				};
+			};
+
+			port@5 {
+				reg = <5>;
+				funnel_lpass_in_tpdm_lpass: endpoint {
+					remote-endpoint =
+					<&tpdm_lpass_out_funnel_lpass>;
+				};
+			};
+		};
+	};
+
+	funnel_ddr: funnel@8a57000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x08a57000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-ddr";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+		out-ports {
+			port@0 {
+				reg = <0>;
+				funnel_ddr_out_tpda6: endpoint {
+					remote-endpoint =
+					<&tpda6_in_funnel_ddr>;
+					source = <&tpdm_ddr0>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_ddr_out_tpda7: endpoint {
+					remote-endpoint =
+					<&tpda7_in_funnel_ddr>;
+					source = <&tpdm_ddr1>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@ {
+				reg = <0>;
+				funnel_ddr_in_tpdm_ddr0: endpoint {
+					remote-endpoint =
+					<&tpdm_ddr0_out_funnel_ddr>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_ddr_in_tpdm_ddr1: endpoint {
+					remote-endpoint =
+					<&tpdm_ddr1_out_funnel_ddr>;
+				};
+			};
+
+		};
+	};
+
+	funnel_merg: funnel@8045000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x8045000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-merg";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				funnel_merg_out_tmc_etf: endpoint {
+					remote-endpoint =
+					<&tmc_etf_in_funnel_merg>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				funnel_merg_in_funnel_in0: endpoint {
+					remote-endpoint =
+					<&funnel_in0_out_funnel_merg>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_merg_in_funnel_in1: endpoint {
+					remote-endpoint =
+					<&funnel_in1_out_funnel_merg>;
+				};
+			};
+
+		};
+	};
+
+	tmc_etf: tmc@8047000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb961>;
+		reg = <0x8047000 0x1000>;
+		reg-names = "tmc-base";
+
+		coresight-name = "coresight-tmc-etf";
+
+		coresight-ctis = <&cti0 &cti6>;
+		cti-flush-trig-num = <1>;
+		cti-reset-trig-num = <5>;
+
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tmc_etf_out_replicator_qdss: endpoint {
+					remote-endpoint =
+					<&replicator_qdss_in_tmc_etf>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				tmc_etf_in_funnel_merg: endpoint {
+					remote-endpoint =
+					<&funnel_merg_out_tmc_etf>;
+				};
+			};
+		};
+	};
+
+	replicator_qdss: replicator@8046000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb909>;
+		reg = <0x8046000 0x1000>;
+		reg-names = "replicator-base";
+
+		coresight-name = "coresight-replicator-qdss";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				replicator_qdss_in_tmc_etf: endpoint {
+					remote-endpoint =
+					<&tmc_etf_out_replicator_qdss>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				replicator_qdss_out_tmc_etr: endpoint {
+					remote-endpoint =
+					<&tmc_etr_in_replicator_qdss>;
+				};
+			};
+		};
+	};
+
+	tmc_etr: tmc@8048000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb961>;
+		reg = <0x8048000 0x1000>,
+			<0x8064000 0x15000>;
+		reg-names = "tmc-base","bam-base";
+
+		coresight-name = "coresight-tmc-etr";
+
+		iommus = <&apps_smmu 0x0180 0>,
+			<&apps_smmu 0x0160 0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		arm,buffer-size = <0x400000>;
+		arm,scatter-gather;
+
+		coresight-ctis = <&cti0 &cti6>;
+		cti-flush-trig-num = <3>;
+		cti-reset-trig-num = <5>;
+
+		coresight-csr = <&csr>;
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		interrupts = <GIC_SPI 429 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "byte-cntr-irq";
+		qcom,sw-usb;
+		qcom,iommu-dma = "bypass";
+		qcom,iommu-dma-addr-pool = <0x0 0xffc00000>;
+
+		in-ports {
+			port {
+				tmc_etr_in_replicator_qdss: endpoint {
+					remote-endpoint =
+					<&replicator_qdss_out_tmc_etr>;
+				};
+			};
+		};
+	};
+
+	cti_cortex_m3: cti@8b30000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8b30000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-cortex_m3";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_apss_cti0: cti@98e0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x98e0000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-apss-cti0";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_apss_cti1: cti@98f0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x98f0000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-apss-cti1";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_wcss_cti0: cti@89a4000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x89a4000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-wcss-cti0";
+
+		status = "disabled";
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_wcss_cti1: cti@89a5000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x89a5000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-wcss-cti1";
+
+		status = "disabled";
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_wcss_cti2: cti@89a6000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x89a6000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-wcss-cti2";
+
+		status = "disabled";
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_lpass_lpi: cti@8a21000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8a21000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-lpass-lpi";
+
+		status = "disabled";
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_lpass_q6: cti@8a2b000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8a2b000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-lpass-q6";
+
+		status = "disabled";
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_mss_q6: cti@8833000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8833000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-mss-q6";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_isdb_gpu: cti@8941000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8941000 0x1000>;
+		reg-names = "cti-base";
+		coresight-name = "coresight-cti-isdb-gpu";
+
+		status = "disabled";
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_mapss: cti@8a02000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8a02000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-mapss";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_dlct_cti0: cti@8b59000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8b59000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-dlct-cti0";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_dlct_cti1: cti@8b5a000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8b5a000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-dlct-cti1";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_dlct_cti2: cti@8b5b000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8b5b000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-dlct-cti2";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_dlct_cti3: cti@8b5c000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8b5c000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-dlct-cti3";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti0: cti@8010000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8010000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti0";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti1: cti@8011000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8011000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti1";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti2: cti@8012000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8012000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti2";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		//qcom,cti-gpio-trigout = <0>;
+		//pinctrl-names = "cti-trigout-pctrl";
+		//pinctrl-0 = <&trigout_a>;
+
+	};
+
+	cti3: cti@8013000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8013000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti3";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti4: cti@8014000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8014000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti4";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti5: cti@8015000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8015000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti5";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti6: cti@8016000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8016000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti6";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti7: cti@8017000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8017000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti7";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti8: cti@8018000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8018000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti8";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti9: cti@8019000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8019000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti9";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti10: cti@801a000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x801a000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti10";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti11: cti@801b000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x801b000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti11";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti12: cti@801c000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x801c000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti12";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti13: cti@801d000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x801d000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti13";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti14: cti@801e000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x801e000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti14";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+
+	cti15: cti@801f000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x801f000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti15";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+};
+
diff --git a/qcom/monaco-dma-heaps.dtsi b/qcom/monaco-dma-heaps.dtsi
new file mode 100644
index 00000000..07330735
--- /dev/null
+++ b/qcom/monaco-dma-heaps.dtsi
@@ -0,0 +1,31 @@
+#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h>
+
+&soc {
+	qcom,dma-heaps {
+		compatible = "qcom,dma-heaps";
+
+		qcom,qseecom {
+			qcom,dma-heap-name = "qcom,qseecom";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&qseecom_mem>;
+		};
+
+		qcom,qseecom_ta {
+			qcom,dma-heap-name = "qcom,qseecom-ta";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&qseecom_ta_mem>;
+		};
+
+		qcom,secure_display {
+			qcom,dma-heap-name = "qcom,secure-display";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&secure_display_memory>;
+		};
+
+		qcom,user_contig {
+			qcom,dma-heap-name = "qcom,user-contig";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&user_contig_mem>;
+		};
+	};
+};
diff --git a/qcom/monaco-gdsc.dtsi b/qcom/monaco-gdsc.dtsi
new file mode 100644
index 00000000..5fbaf12b
--- /dev/null
+++ b/qcom/monaco-gdsc.dtsi
@@ -0,0 +1,93 @@
+&soc {
+	/* GDSCs in GCC */
+	gcc_camss_top_gdsc: qcom,gdsc@1458004 {
+		compatible = "qcom,gdsc";
+		reg = <0x1458004 0x4>;
+		regulator-name = "gcc_camss_top_gdsc";
+		status = "disabled";
+	};
+
+	gcc_usb20_prim_gdsc: qcom,gdsc@141c004 {
+		compatible = "qcom,gdsc";
+		reg = <0x141c004 0x4>;
+		regulator-name = "gcc_usb20_prim_gdsc";
+		status = "disabled";
+	};
+
+	gcc_vcodec0_gdsc: qcom,gdsc@14580ac {
+		compatible = "qcom,gdsc";
+		reg = <0x14580ac 0x4>;
+		regulator-name = "gcc_vcodec0_gdsc";
+		status = "disabled";
+	};
+
+	gcc_venus_gdsc: qcom,gdsc@1458088 {
+		compatible = "qcom,gdsc";
+		reg = <0x1458088 0x4>;
+		regulator-name = "gcc_venus_gdsc";
+		status = "disabled";
+	};
+
+	hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 {
+		compatible = "qcom,gdsc";
+		reg = <0x147d078 0x4>;
+		regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc";
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 {
+		compatible = "qcom,gdsc";
+		reg = <0x147d074 0x4>;
+		regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc";
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	/* GDSCs in DISPCC */
+	mdss_core_gdsc: qcom,gdsc@5f03000 {
+		compatible = "qcom,gdsc";
+		reg = <0x5f03000 0x4>;
+		regulator-name = "mdss_core_gdsc";
+		proxy-supply = <&mdss_core_gdsc>;
+		qcom,proxy-consumer-enable;
+		status = "disabled";
+	};
+
+	/* GDSCs in GPUCC */
+	gpu_gx_sw_reset: syscon@5994008 {
+		compatible = "syscon";
+		reg = <0x5994008 0x4>;
+	};
+
+	gpu_cx_hw_ctrl: syscon@5994540 {
+		compatible = "syscon";
+		reg = <0x5994540 0x4>;
+	};
+
+	gpu_gx_domain_addr: syscon@5994508 {
+		compatible = "syscon";
+		reg = <0x5994508 0x4>;
+	};
+
+	gpu_cx_gdsc: qcom,gdsc@5994064 {
+		compatible = "qcom,gdsc";
+		reg = <0x5994064 0x4>;
+		regulator-name = "gpu_cx_gdsc";
+		hw-ctl-addr = <&gpu_cx_hw_ctrl>;
+		qcom,gds-timeout = <500>;
+		qcom,clk-dis-wait-val = <8>;
+		qcom,no-status-check-on-disable;
+		status = "disabled";
+	};
+
+	gpu_gx_gdsc: qcom,gdsc@599400c {
+		compatible = "qcom,gdsc";
+		reg = <0x599400c 0x4>;
+		regulator-name = "gpu_gx_gdsc";
+		sw-reset = <&gpu_gx_sw_reset>;
+		domain-addr = <&gpu_gx_domain_addr>;
+		qcom,reset-aon-logic;
+		status = "disabled";
+	};
+};
diff --git a/qcom/monaco-haptics-fifo-data.dtsi b/qcom/monaco-haptics-fifo-data.dtsi
new file mode 100644
index 00000000..ad4fbf0d
--- /dev/null
+++ b/qcom/monaco-haptics-fifo-data.dtsi
@@ -0,0 +1,299 @@
+#include <dt-bindings/input/qcom,hv-haptics.h>
+
+&pm5100_haptics {
+	effect_6 {
+		qcom,effect-id = <17>;
+		qcom,wf-vmax-mv = <4800>;
+		qcom,wf-fifo-data = [
+			00 00 00 00 00 00 00 00 00 00
+			00 01 01 01 01 01 01 01 01 01
+			02 02 02 02 02 03 03 03 04 04
+			04 05 05 05 06 06 07 08 08 09
+			0a 0b 0c 0c 0d 0e 0f 0f 0f 0f
+			0f 0f 0e 0e 0d 0c 0b 0a 09 08
+			06 05 03 01 00 ff fd fa f8 f6
+			f3 f1 ee ec e9 e6 e3 e0 dc d9
+			d5 d1 cd c8 c4 bf bb b9 b7 b6
+			b7 b8 ba bd c1 c5 cb d1 d7 de
+			e5 ed f5 fd 04 0d 15 1e 26 2e
+			36 3d 44 4b 51 56 5b 5f 62 64
+			65 65 64 63 5f 5b 56 50 4a 45
+			3f 3a 34 2f 29 24 1f 1a 14 0f
+			0a 05 00 fc f8 f3 ef ea e6 e2
+			df dc d9 d6 d4 d3 d2 d1 d1 d1
+			d2 d4 d7 da de e2 e8 ee f6 fd
+			02 08 0d 12 16 1a 1d 20 23 26
+			28 2a 2b 2d 2e 2f 30 30 30 31
+			31 31 31 30 30 2f 2f 2e 2d 2c
+			2c 2b 2a 29 28 26 25 24 23 22
+			21 20 1e 1d 1c 1b 1a 19 17 16
+			15 14 13 12 11 10 0f 0e 0d 0c
+			0b 0a 0a 09 08 07 07 06 05 04
+			04 03 03 02 02 01 01 00 00 00
+			00 00 ff ff ff ff fe fe fe fe
+			fd fd fd fd fd fd fd fd fd fc
+			fc fc fc fc fc fc fc fc fc fc
+			fc fd fd fd fd fd fd fd fd fd
+			fd fd fd fd fd fe fe fe fe fe
+			fe fe fe fe fe fe ff ff ff ff
+			ff ff ff ff ff ff ff ff ff ff
+			00 00 00 00 00 00 00 00 00 00
+			00 01 01 01 01 01 01 01 01 01
+			02 02 02 02 02 03 03 03 04 04
+			04 05 05 05 06 06 07 08 08 09
+			0a 0b 0c 0c 0d 0e 0f 0f 0f 0f
+			0f 0f 0e 0e 0d 0c 0b 0a 09 08
+			06 05 03 01 00 ff fd fa f8 f6
+			f3 f1 ee ec e9 e6 e3 e0 dc d9
+			d5 d1 cd c8 c4 bf bb b9 b7 b6
+			b7 b8 ba bd c1 c5 cb d1 d7 de
+			e5 ed f5 fd 04 0d 15 1e 26 2e
+			36 3d 44 4b 51 56 5b 5f 62 64
+			65 65 64 63 5f 5b 56 50 4a 45
+			3f 3a 34 2f 29 24 1f 1a 14 0f
+			0a 05 00 fc f8 f3 ef ea e6 e2
+			df dc d9 d6 d4 d3 d2 d1 d1 d1
+			d2 d4 d7 da de e2 e8 ee f6 fd
+			02 08 0d 12 16 1a 1d 20 23 26
+			28 2a 2b 2d 2e 2f 30 30 30 31
+			31 31 31 30 30 2f 2f 2e 2d 2c
+			2c 2b 2a 29 28 26 25 24 23 22
+			21 20 1e 1d 1c 1b 1a 19 17 16
+			15 14 13 12 11 10 0f 0e 0d 0c
+			0b 0a 0a 09 08 07 07 06 05 04
+			04 03 03 02 02 01 01 00 00 00
+			00 00 ff ff ff ff fe fe fe fe
+			fd fd fd fd fd fd fd fd fd fc
+			fc fc fc fc fc fc fc fc fc fc
+			fc fd fd fd fd fd fd fd fd fd
+			fd fd fd fd fd fe fe fe fe fe
+			fe fe fe fe fe fe ff ff ff ff
+			ff ff ff ff ff ff ff ff ff ff
+			];
+			qcom,wf-fifo-period = <S_PERIOD_T_LRA_X_8>;
+			qcom,wf-brake-disable;
+			qcom,wf-auto-res-disable;
+	};
+
+	effect_7 {
+		qcom,effect-id = <18>;
+		qcom,wf-vmax-mv = <4800>;
+		qcom,wf-fifo-data = [
+			00 00 00 00 00 00 00 00 00 00
+			00 01 01 01 01 01 01 01 01 01
+			02 02 02 02 02 03 03 03 04 04
+			04 05 05 05 06 06 07 08 08 09
+			0a 0b 0c 0c 0d 0e 0f 0f 0f 0f
+			0f 0f 0e 0e 0d 0c 0b 0a 09 08
+			06 05 03 01 00 ff fd fa f8 f6
+			f3 f1 ee ec e9 e6 e3 e0 dc d9
+			d5 d1 cd c8 c4 bf bb b9 b7 b6
+			b7 b8 ba bd c1 c5 cb d1 d7 de
+			e5 ed f5 fd 04 0d 15 1e 26 2e
+			36 3d 44 4b 51 56 5b 5f 62 64
+			65 65 64 63 5f 5b 56 50 4a 45
+			3f 3a 34 2f 29 24 1f 1a 14 0f
+			0a 05 00 fc f8 f3 ef ea e6 e2
+			df dc d9 d6 d4 d3 d2 d1 d1 d1
+			d2 d4 d7 da de e2 e8 ee f6 fd
+			02 08 0d 12 16 1a 1d 20 23 26
+			28 2a 2b 2d 2e 2f 30 30 30 31
+			31 31 31 30 30 2f 2f 2e 2d 2c
+			2c 2b 2a 29 28 26 25 24 23 22
+			21 20 1e 1d 1c 1b 1a 19 17 16
+			15 14 13 12 11 10 0f 0e 0d 0c
+			0b 0a 0a 09 08 07 07 06 05 04
+			04 03 03 02 02 01 01 00 00 00
+			00 00 ff ff ff ff fe fe fe fe
+			fd fd fd fd fd fd fd fd fd fc
+			fc fc fc fc fc fc fc fc fc fc
+			fc fd fd fd fd fd fd fd fd fd
+			fd fd fd fd fd fe fe fe fe fe
+			fe fe fe fe fe fe ff ff ff ff
+			ff ff ff ff ff ff ff ff ff ff
+			00 00 00 00 00 00 00 00 00 00
+			00 01 01 01 01 01 01 01 01 01
+			02 02 02 02 02 03 03 03 04 04
+			04 05 05 05 06 06 07 08 08 09
+			0a 0b 0c 0c 0d 0e 0f 0f 0f 0f
+			0f 0f 0e 0e 0d 0c 0b 0a 09 08
+			06 05 03 01 00 ff fd fa f8 f6
+			f3 f1 ee ec e9 e6 e3 e0 dc d9
+			d5 d1 cd c8 c4 bf bb b9 b7 b6
+			b7 b8 ba bd c1 c5 cb d1 d7 de
+			e5 ed f5 fd 04 0d 15 1e 26 2e
+			36 3d 44 4b 51 56 5b 5f 62 64
+			65 65 64 63 5f 5b 56 50 4a 45
+			3f 3a 34 2f 29 24 1f 1a 14 0f
+			0a 05 00 fc f8 f3 ef ea e6 e2
+			df dc d9 d6 d4 d3 d2 d1 d1 d1
+			d2 d4 d7 da de e2 e8 ee f6 fd
+			02 08 0d 12 16 1a 1d 20 23 26
+			28 2a 2b 2d 2e 2f 30 30 30 31
+			31 31 31 30 30 2f 2f 2e 2d 2c
+			2c 2b 2a 29 28 26 25 24 23 22
+			21 20 1e 1d 1c 1b 1a 19 17 16
+			15 14 13 12 11 10 0f 0e 0d 0c
+			0b 0a 0a 09 08 07 07 06 05 04
+			04 03 03 02 02 01 01 00 00 00
+			00 00 ff ff ff ff fe fe fe fe
+			fd fd fd fd fd fd fd fd fd fc
+			fc fc fc fc fc fc fc fc fc fc
+			fc fd fd fd fd fd fd fd fd fd
+			fd fd fd fd fd fe fe fe fe fe
+			fe fe fe fe fe fe ff ff ff ff
+			ff ff ff ff ff ff ff ff ff ff
+			];
+			qcom,wf-fifo-period = <S_PERIOD_T_LRA_X_8>;
+			qcom,wf-brake-disable;
+			qcom,wf-auto-res-disable;
+	};
+
+	effect_8 {
+		qcom,effect-id = <19>;
+		qcom,wf-vmax-mv = <4800>;
+		qcom,wf-fifo-data = [
+			00 00 00 00 00 00 00 00 00 00
+			00 01 01 01 01 01 01 01 01 01
+			02 02 02 02 02 03 03 03 04 04
+			04 05 05 05 06 06 07 08 08 09
+			0a 0b 0c 0c 0d 0e 0f 0f 0f 0f
+			0f 0f 0e 0e 0d 0c 0b 0a 09 08
+			06 05 03 01 00 ff fd fa f8 f6
+			f3 f1 ee ec e9 e6 e3 e0 dc d9
+			d5 d1 cd c8 c4 bf bb b9 b7 b6
+			b7 b8 ba bd c1 c5 cb d1 d7 de
+			e5 ed f5 fd 04 0d 15 1e 26 2e
+			36 3d 44 4b 51 56 5b 5f 62 64
+			65 65 64 63 5f 5b 56 50 4a 45
+			3f 3a 34 2f 29 24 1f 1a 14 0f
+			0a 05 00 fc f8 f3 ef ea e6 e2
+			df dc d9 d6 d4 d3 d2 d1 d1 d1
+			d2 d4 d7 da de e2 e8 ee f6 fd
+			02 08 0d 12 16 1a 1d 20 23 26
+			28 2a 2b 2d 2e 2f 30 30 30 31
+			31 31 31 30 30 2f 2f 2e 2d 2c
+			2c 2b 2a 29 28 26 25 24 23 22
+			21 20 1e 1d 1c 1b 1a 19 17 16
+			15 14 13 12 11 10 0f 0e 0d 0c
+			0b 0a 0a 09 08 07 07 06 05 04
+			04 03 03 02 02 01 01 00 00 00
+			00 00 ff ff ff ff fe fe fe fe
+			fd fd fd fd fd fd fd fd fd fc
+			fc fc fc fc fc fc fc fc fc fc
+			fc fd fd fd fd fd fd fd fd fd
+			fd fd fd fd fd fe fe fe fe fe
+			fe fe fe fe fe fe ff ff ff ff
+			ff ff ff ff ff ff ff ff ff ff
+			00 00 00 00 00 00 00 00 00 00
+			00 01 01 01 01 01 01 01 01 01
+			02 02 02 02 02 03 03 03 04 04
+			04 05 05 05 06 06 07 08 08 09
+			0a 0b 0c 0c 0d 0e 0f 0f 0f 0f
+			0f 0f 0e 0e 0d 0c 0b 0a 09 08
+			06 05 03 01 00 ff fd fa f8 f6
+			f3 f1 ee ec e9 e6 e3 e0 dc d9
+			d5 d1 cd c8 c4 bf bb b9 b7 b6
+			b7 b8 ba bd c1 c5 cb d1 d7 de
+			e5 ed f5 fd 04 0d 15 1e 26 2e
+			36 3d 44 4b 51 56 5b 5f 62 64
+			65 65 64 63 5f 5b 56 50 4a 45
+			3f 3a 34 2f 29 24 1f 1a 14 0f
+			0a 05 00 fc f8 f3 ef ea e6 e2
+			df dc d9 d6 d4 d3 d2 d1 d1 d1
+			d2 d4 d7 da de e2 e8 ee f6 fd
+			02 08 0d 12 16 1a 1d 20 23 26
+			28 2a 2b 2d 2e 2f 30 30 30 31
+			31 31 31 30 30 2f 2f 2e 2d 2c
+			2c 2b 2a 29 28 26 25 24 23 22
+			21 20 1e 1d 1c 1b 1a 19 17 16
+			15 14 13 12 11 10 0f 0e 0d 0c
+			0b 0a 0a 09 08 07 07 06 05 04
+			04 03 03 02 02 01 01 00 00 00
+			00 00 ff ff ff ff fe fe fe fe
+			fd fd fd fd fd fd fd fd fd fc
+			fc fc fc fc fc fc fc fc fc fc
+			fc fd fd fd fd fd fd fd fd fd
+			fd fd fd fd fd fe fe fe fe fe
+			fe fe fe fe fe fe ff ff ff ff
+			ff ff ff ff ff ff ff ff ff ff
+			];
+			qcom,wf-fifo-period = <S_PERIOD_T_LRA_X_8>;
+			qcom,wf-brake-disable;
+			qcom,wf-auto-res-disable;
+	};
+
+	effect_9 {
+		qcom,effect-id = <20>;
+		qcom,wf-vmax-mv = <4800>;
+		qcom,wf-fifo-data = [
+			00 00 00 00 00 00 00 00 00 00
+			00 01 01 01 01 01 01 01 01 01
+			02 02 02 02 02 03 03 03 04 04
+			04 05 05 05 06 06 07 08 08 09
+			0a 0b 0c 0c 0d 0e 0f 0f 0f 0f
+			0f 0f 0e 0e 0d 0c 0b 0a 09 08
+			06 05 03 01 00 ff fd fa f8 f6
+			f3 f1 ee ec e9 e6 e3 e0 dc d9
+			d5 d1 cd c8 c4 bf bb b9 b7 b6
+			b7 b8 ba bd c1 c5 cb d1 d7 de
+			e5 ed f5 fd 04 0d 15 1e 26 2e
+			36 3d 44 4b 51 56 5b 5f 62 64
+			65 65 64 63 5f 5b 56 50 4a 45
+			3f 3a 34 2f 29 24 1f 1a 14 0f
+			0a 05 00 fc f8 f3 ef ea e6 e2
+			df dc d9 d6 d4 d3 d2 d1 d1 d1
+			d2 d4 d7 da de e2 e8 ee f6 fd
+			02 08 0d 12 16 1a 1d 20 23 26
+			28 2a 2b 2d 2e 2f 30 30 30 31
+			31 31 31 30 30 2f 2f 2e 2d 2c
+			2c 2b 2a 29 28 26 25 24 23 22
+			21 20 1e 1d 1c 1b 1a 19 17 16
+			15 14 13 12 11 10 0f 0e 0d 0c
+			0b 0a 0a 09 08 07 07 06 05 04
+			04 03 03 02 02 01 01 00 00 00
+			00 00 ff ff ff ff fe fe fe fe
+			fd fd fd fd fd fd fd fd fd fc
+			fc fc fc fc fc fc fc fc fc fc
+			fc fd fd fd fd fd fd fd fd fd
+			fd fd fd fd fd fe fe fe fe fe
+			fe fe fe fe fe fe ff ff ff ff
+			ff ff ff ff ff ff ff ff ff ff
+			00 00 00 00 00 00 00 00 00 00
+			00 01 01 01 01 01 01 01 01 01
+			02 02 02 02 02 03 03 03 04 04
+			04 05 05 05 06 06 07 08 08 09
+			0a 0b 0c 0c 0d 0e 0f 0f 0f 0f
+			0f 0f 0e 0e 0d 0c 0b 0a 09 08
+			06 05 03 01 00 ff fd fa f8 f6
+			f3 f1 ee ec e9 e6 e3 e0 dc d9
+			d5 d1 cd c8 c4 bf bb b9 b7 b6
+			b7 b8 ba bd c1 c5 cb d1 d7 de
+			e5 ed f5 fd 04 0d 15 1e 26 2e
+			36 3d 44 4b 51 56 5b 5f 62 64
+			65 65 64 63 5f 5b 56 50 4a 45
+			3f 3a 34 2f 29 24 1f 1a 14 0f
+			0a 05 00 fc f8 f3 ef ea e6 e2
+			df dc d9 d6 d4 d3 d2 d1 d1 d1
+			d2 d4 d7 da de e2 e8 ee f6 fd
+			02 08 0d 12 16 1a 1d 20 23 26
+			28 2a 2b 2d 2e 2f 30 30 30 31
+			31 31 31 30 30 2f 2f 2e 2d 2c
+			2c 2b 2a 29 28 26 25 24 23 22
+			21 20 1e 1d 1c 1b 1a 19 17 16
+			15 14 13 12 11 10 0f 0e 0d 0c
+			0b 0a 0a 09 08 07 07 06 05 04
+			04 03 03 02 02 01 01 00 00 00
+			00 00 ff ff ff ff fe fe fe fe
+			fd fd fd fd fd fd fd fd fd fc
+			fc fc fc fc fc fc fc fc fc fc
+			fc fd fd fd fd fd fd fd fd fd
+			fd fd fd fd fd fe fe fe fe fe
+			fe fe fe fe fe fe ff ff ff ff
+			ff ff ff ff ff ff ff ff ff ff
+			];
+			qcom,wf-fifo-period = <S_PERIOD_T_LRA_X_8>;
+			qcom,wf-brake-disable;
+			qcom,wf-auto-res-disable;
+	};
+};
diff --git a/qcom/monaco-idp-v1-common.dtsi b/qcom/monaco-idp-v1-common.dtsi
new file mode 100644
index 00000000..186e1158
--- /dev/null
+++ b/qcom/monaco-idp-v1-common.dtsi
@@ -0,0 +1,17 @@
+#include "monaco-thermal-overlay.dtsi"
+#include "monaco-haptics-fifo-data.dtsi"
+
+&pm5100_sdam_2 {
+	hap_cl_brake: cl_brake@7c {
+		reg = <0x7c 0x1>;
+		bits = <0 8>;
+	};
+};
+
+&pm5100_haptics {
+	nvmem-cell-names = "hap_cl_brake";
+	nvmem-cells = <&hap_cl_brake>;
+	nvmem-names = "hap_cfg_sdam";
+	nvmem = <&pm5100_sdam_23>;
+	status = "okay";
+};
diff --git a/qcom/monaco-idp-v1-overlay.dts b/qcom/monaco-idp-v1-overlay.dts
new file mode 100644
index 00000000..2d46bdbd
--- /dev/null
+++ b/qcom/monaco-idp-v1-overlay.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+#include "monaco-idp-v1.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco IDP V1.0";
+	qcom,board-id = <0x010022 0x0>;
+};
diff --git a/qcom/monaco-idp-v1.dtsi b/qcom/monaco-idp-v1.dtsi
new file mode 100644
index 00000000..a0efbd95
--- /dev/null
+++ b/qcom/monaco-idp-v1.dtsi
@@ -0,0 +1,63 @@
+#include "monaco-idp-v1-common.dtsi"
+#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm5100.h>
+#include <dt-bindings/iio/qti_power_supply_iio.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+
+&sdhc_1 {
+	status = "ok";
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc1_on>;
+	pinctrl-1 = <&sdc1_off>;
+
+	vdd-supply = <&L25A>;
+	qcom,vdd-voltage-level = <3080000 3080000>;
+	qcom,vdd-current-level = <0 250000>;
+
+	vdd-io-supply = <&L15A>;
+	qcom,vdd-io-always-on;
+	qcom,vdd-io-lpm-sup;
+	qcom,vdd-io-voltage-level = <1800000 1800000>;
+	qcom,vdd-io-current-level = <0 250000>;
+};
+
+&soc {
+	bluetooth: bt_wcn3990 {
+		compatible = "qcom,qcc5100";
+
+		status = "ok";
+	};
+};
+
+&pm5100_charger {
+	qcom,remote-fg;
+	#io-channel-cells = <1>;
+	io-channels = <&pm5100_adc PM5100_ADC5_GEN3_USB_SNS_V_16>,
+		      <&pm5100_adc PM5100_ADC5_GEN3_USB_IN_I>,
+		      <&pm5100_adc PM5100_ADC5_GEN3_CHG_TEMP>,
+		      <&pm5100_adc PM5100_ADC5_GEN3_DIE_TEMP>,
+		      <&pm5100_adc PM5100_ADC5_GEN3_VPH_PWR>,
+		      <&pm5100_adc PM5100_ADC5_GEN3_BAT_ID_100K_PU>,
+		      <&pm5100_adc PM5100_ADC5_GEN3_BATT_THM_100K_PU>,
+		      <&pm5100_adc PM5100_ADC5_GEN3_VBAT_SNS_QBG>;
+
+	io-channel-names = "usb_in_voltage",
+			   "usb_in_current",
+			   "chg_temp",
+			   "die_temp",
+			   "vph_voltage",
+			   "batt-id",
+			   "batt-temp",
+			   "batt-volt";
+};
+
+&pm5100_gpios {
+	nfc_clk {
+		nfc_clk_default: nfc_clk_default {
+		pins = "gpio4";
+		function = "normal";
+		input-enable;
+		power-source = <1>;
+		};
+	};
+};
diff --git a/qcom/monaco-idp-v2-overlay.dts b/qcom/monaco-idp-v2-overlay.dts
new file mode 100644
index 00000000..24f7976e
--- /dev/null
+++ b/qcom/monaco-idp-v2-overlay.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+#include "monaco-idp-v2.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco IDP V2.0";
+	qcom,board-id = <0x020022 0x0>;
+};
diff --git a/qcom/monaco-idp-v2.dtsi b/qcom/monaco-idp-v2.dtsi
new file mode 100644
index 00000000..6fea5bc4
--- /dev/null
+++ b/qcom/monaco-idp-v2.dtsi
@@ -0,0 +1 @@
+#include "monaco-idp-v1.dtsi"
diff --git a/qcom/monaco-idp-v3-overlay.dts b/qcom/monaco-idp-v3-overlay.dts
new file mode 100644
index 00000000..b0b0726b
--- /dev/null
+++ b/qcom/monaco-idp-v3-overlay.dts
@@ -0,0 +1,8 @@
+/dts-v1/;
+/plugin/;
+
+#include "monaco-idp-v3.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco IDP V3.0";
+	qcom,board-id = <0x030022 0x0>;
+};
diff --git a/qcom/monaco-idp-v3.dtsi b/qcom/monaco-idp-v3.dtsi
new file mode 100644
index 00000000..6fea5bc4
--- /dev/null
+++ b/qcom/monaco-idp-v3.dtsi
@@ -0,0 +1 @@
+#include "monaco-idp-v1.dtsi"
diff --git a/qcom/monaco-pinctrl.dtsi b/qcom/monaco-pinctrl.dtsi
new file mode 100644
index 00000000..5709e882
--- /dev/null
+++ b/qcom/monaco-pinctrl.dtsi
@@ -0,0 +1,1193 @@
+&soc {
+	tlmm: pinctrl@500000 {
+		compatible = "qcom,monaco-pinctrl";
+		reg = <0x500000 0x300000>;
+		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		wakeup-parent = <&wakegic>;
+
+		qupv3_se6_2uart_pins: qupv3_se6_2uart_pins {
+			qupv3_se6_2uart_active: qupv3_se6_2uart_active {
+				mux {
+					pins = "gpio30", "gpio31";
+					function = "qup06";
+				};
+
+				config {
+					pins = "gpio30", "gpio31";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se6_2uart_sleep: qupv3_se6_2uart_sleep {
+				mux {
+					pins = "gpio30", "gpio31";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio30", "gpio31";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+		};
+
+		qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
+			qupv3_se0_i2c_active: qupv3_se0_i2c_active {
+				mux {
+					pins = "gpio4", "gpio5";
+					function = "qup00";
+				};
+
+				config {
+					pins = "gpio4", "gpio5";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
+				mux {
+					pins = "gpio4", "gpio5";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio4", "gpio5";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		nfc {
+			nfc_int_active: nfc_int_active {
+				/* active state */
+				mux {
+					/* NFC Read Interrupt */
+					pins = "gpio7";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio7";
+					drive-strength = <2>; /* 2 MA */
+					bias-pull-up;
+				};
+			};
+
+			nfc_int_suspend: nfc_int_suspend {
+				/* sleep state */
+				mux {
+					/* NFC Read Interrupt */
+					pins = "gpio7";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio7";
+					drive-strength = <2>; /* 2 MA */
+					bias-pull-up;
+				};
+			};
+
+			nfc_enable_active: nfc_enable_active {
+				/* active state */
+				mux {
+					/* Enable, Firmware gpios */
+					pins = "gpio6", "gpio8";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio6", "gpio8";
+					drive-strength = <2>; /* 2 MA */
+					bias-pull-up;
+				};
+			};
+
+			nfc_enable_suspend: nfc_enable_suspend {
+				/* sleep state */
+				mux {
+					/* Enable, Firmware gpios */
+					pins = "gpio6", "gpio8";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio6", "gpio8";
+					drive-strength = <2>; /* 2 MA */
+					bias-disable;
+				};
+			};
+		};
+
+		qupv3_se0_spi_pins: qupv3_se0_spi_pins {
+			qupv3_se0_spi_active: qupv3_se0_spi_active {
+				mux {
+					pins = "gpio4", "gpio5",
+							"gpio6", "gpio7";
+					function = "qup00";
+				};
+
+				config {
+					pins = "gpio4", "gpio5",
+							"gpio6", "gpio7";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
+				mux {
+					pins = "gpio4", "gpio5",
+							"gpio6", "gpio7";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio4", "gpio5",
+							"gpio6", "gpio7";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+		};
+
+		qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
+			qupv3_se1_i2c_active: qupv3_se1_i2c_active {
+				mux {
+					pins = "gpio10", "gpio11";
+					function = "qup01";
+				};
+
+				config {
+					pins = "gpio10", "gpio11";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
+				mux {
+					pins = "gpio10", "gpio11";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio10", "gpio11";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		qupv3_se1_spi_pins: qupv3_se1_spi_pins {
+			qupv3_se1_spi_active: qupv3_se1_spi_active {
+				mux {
+					pins = "gpio10", "gpio11",
+							"gpio12", "gpio13";
+					function = "qup01";
+				};
+
+				config {
+					pins = "gpio10", "gpio11",
+							"gpio12", "gpio13";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
+				mux {
+					pins = "gpio10", "gpio11",
+							"gpio12", "gpio13";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio10", "gpio11",
+							"gpio12", "gpio13";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+		};
+
+		qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
+			qupv3_se2_i2c_active: qupv3_se2_i2c_active {
+				mux {
+					pins = "gpio0", "gpio1";
+					function = "qup02";
+				};
+
+				config {
+					pins = "gpio0", "gpio1";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
+				mux {
+					pins = "gpio0", "gpio1";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio0", "gpio1";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		qupv3_se2_spi_pins: qupv3_se2_spi_pins {
+			qupv3_se2_spi_active: qupv3_se2_spi_active {
+				mux {
+					pins = "gpio0", "gpio1",
+							"gpio2", "gpio3";
+					function = "qup02";
+				};
+
+				config {
+					pins = "gpio0", "gpio1",
+							"gpio2", "gpio3";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
+				mux {
+					pins = "gpio0", "gpio1",
+							"gpio2", "gpio3";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio0", "gpio1",
+							"gpio2", "gpio3";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+		};
+
+		qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
+			qupv3_se3_i2c_active: qupv3_se3_i2c_active {
+				mux {
+					pins = "gpio14", "gpio15";
+					function = "qup03";
+				};
+
+				config {
+					pins = "gpio14", "gpio15";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
+				mux {
+					pins = "gpio14", "gpio15";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio14", "gpio15";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		qupv3_se3_spi_pins: qupv3_se3_spi_pins {
+			qupv3_se3_spi_active: qupv3_se3_spi_active {
+				mux {
+					pins = "gpio14", "gpio15",
+							"gpio16", "gpio17";
+					function = "qup03";
+				};
+
+				config {
+					pins = "gpio14", "gpio15",
+							"gpio16", "gpio17";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
+				mux {
+					pins = "gpio14", "gpio15",
+							"gpio16", "gpio17";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio14", "gpio15",
+							"gpio16", "gpio17";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+		};
+
+		qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
+			qupv3_se4_i2c_active: qupv3_se4_i2c_active {
+				mux {
+					pins = "gpio20", "gpio21";
+					function = "qup04";
+				};
+
+				config {
+					pins = "gpio20", "gpio21";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
+				mux {
+					pins = "gpio20", "gpio21";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio20", "gpio21";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		qupv3_se4_spi_pins: qupv3_se4_spi_pins {
+			qupv3_se4_spi_active: qupv3_se4_spi_active {
+				mux {
+					pins = "gpio20", "gpio21",
+							"gpio22";
+					function = "qup04";
+				};
+
+				config {
+					pins = "gpio20", "gpio21",
+							"gpio22";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
+				mux {
+					pins = "gpio20", "gpio21",
+							"gpio22";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio20", "gpio21",
+							"gpio22";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se4_spi_cs0_active: qupv3_se4_spi_cs0_active {
+				mux {
+					pins = "gpio23";
+					function = "qup04";
+				};
+
+				config {
+					pins = "gpio23";
+					drive-strength = <6>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se4_spi_cs0_sleep: qupv3_se4_spi_cs0_sleep {
+				mux {
+					pins = "gpio23";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio23";
+					drive-strength = <6>;
+					bias-pull-up;
+				};
+			};
+		};
+
+		qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
+			qupv3_se5_i2c_active: qupv3_se5_i2c_active {
+				mux {
+					pins = "gpio26", "gpio27";
+					function = "qup05";
+				};
+
+				config {
+					pins = "gpio26", "gpio27";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
+				mux {
+					pins = "gpio26", "gpio27";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio26", "gpio27";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		qupv3_se5_spi_pins: qupv3_se5_spi_pins {
+			qupv3_se5_spi_active: qupv3_se5_spi_active {
+				mux {
+					pins = "gpio26", "gpio27",
+							"gpio28", "gpio29";
+					function = "qup05";
+				};
+
+				config {
+					pins = "gpio26", "gpio27",
+							"gpio28", "gpio29";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
+				mux {
+					pins = "gpio26", "gpio27",
+							"gpio28", "gpio29";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio26", "gpio27",
+							"gpio28", "gpio29";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+		};
+
+		qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
+			qupv3_se6_i2c_active: qupv3_se6_i2c_active {
+				mux {
+					pins = "gpio24", "gpio25";
+					function = "qup06";
+				};
+
+				config {
+					pins = "gpio24", "gpio25";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
+				mux {
+					pins = "gpio24", "gpio25";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio24", "gpio25";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		qupv3_se6_spi_pins: qupv3_se6_spi_pins {
+			qupv3_se6_spi_active: qupv3_se6_spi_active {
+				mux {
+					pins = "gpio24", "gpio25",
+							"gpio30", "gpio31";
+					function = "qup06";
+				};
+
+				config {
+					pins = "gpio24", "gpio25",
+							"gpio30", "gpio31";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
+				mux {
+					pins = "gpio24", "gpio25",
+							"gpio30", "gpio31";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio24", "gpio25",
+							"gpio30", "gpio31";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+		};
+
+		qupv3_se7_i2c_pins_a: qupv3_se7_i2c_pins_a {
+			qupv3_se7_i2c_active_L0_a: qupv3_se7_i2c_active_L0_a {
+				mux {
+					pins = "gpio101";
+					function = "QUP0_L0";
+				};
+
+				config {
+					pins = "gpio101";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+
+			};
+
+			qupv3_se7_i2c_active_L1_a: qupv3_se7_i2c_active_L1_a {
+				mux {
+					pins = "gpio102";
+					function = "QUP0_L1";
+				};
+
+				config {
+					pins = "gpio102";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se7_i2c_sleep_a: qupv3_se7_i2c_sleep_a {
+				mux {
+					pins = "gpio101", "gpio102";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio101", "gpio102";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		qupv3_se7_spi_pins_a: qupv3_se7_spi_pins_a {
+			qupv3_se7_spi_active_L0_a: qupv3_se7_spi_active_L0_a {
+				mux {
+					pins = "gpio101";
+					function = "QUP0_L0";
+				};
+
+				config {
+					pins = "gpio101";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se7_spi_active_L1_a: qupv3_se7_spi_active_L1_a {
+				mux {
+					pins = "gpio102";
+					function = "QUP0_L1";
+				};
+
+				config {
+					pins = "gpio102";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se7_spi_active_L2_a: qupv3_se7_spi_active_L2_a {
+				mux {
+					pins = "gpio104";
+					function = "QUP0_L2";
+				};
+
+				config {
+					pins = "gpio104";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se7_spi_active_L3_a: qupv3_se7_spi_active_L3_a {
+				mux {
+					pins = "gpio105";
+					function = "QUP0_L3";
+				};
+
+				config {
+					pins = "gpio105";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se7_spi_sleep_a: qupv3_se7_spi_sleep_a {
+				mux {
+					pins = "gpio101", "gpio102",
+							"gpio104", "gpio105";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio101", "gpio102",
+							"gpio104", "gpio105";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+		};
+
+		qupv3_se7_i2c_pins_b: qupv3_se7_i2c_pins_b {
+			qupv3_se7_i2c_active_L0_b: qupv3_se7_i2c_active_L0_b {
+				mux {
+					pins = "gpio104";
+					function = "QUP0_L0";
+				};
+
+				config {
+					pins = "gpio104";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+
+			};
+
+			qupv3_se7_i2c_active_L1_b: qupv3_se7_i2c_active_L1_b {
+				mux {
+					pins = "gpio105";
+					function = "QUP0_L1";
+				};
+
+				config {
+					pins = "gpio105";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se7_i2c_sleep_b: qupv3_se7_i2c_sleep_b {
+				mux {
+					pins = "gpio104", "gpio105";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio104", "gpio105";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		qupv3_se7_spi_pins_b: qupv3_se7_spi_pins_b {
+			qupv3_se7_spi_active_L0_b: qupv3_se7_spi_active_L0_b {
+				mux {
+					pins = "gpio104";
+					function = "QUP0_L0";
+				};
+
+				config {
+					pins = "gpio104";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se7_spi_active_L1_b: qupv3_se7_spi_active_L1_b {
+				mux {
+					pins = "gpio105";
+					function = "QUP0_L1";
+				};
+
+				config {
+					pins = "gpio105";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se7_spi_active_L2_b: qupv3_se7_spi_active_L2_b {
+				mux {
+					pins = "gpio101";
+					function = "QUP0_L2";
+				};
+
+				config {
+					pins = "gpio101";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se7_spi_active_L3_b: qupv3_se7_spi_active_L3_b {
+				mux {
+					pins = "gpio102";
+					function = "QUP0_L3";
+				};
+
+				config {
+					pins = "gpio102";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se7_spi_sleep_b: qupv3_se7_spi_sleep_b {
+				mux {
+					pins = "gpio104", "gpio105",
+							"gpio101", "gpio102";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio104", "gpio105",
+							"gpio101", "gpio102";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+		};
+
+		qupv3_se5_4uart_pins: qupv3_se5_4uart_pins {
+			qupv3_se5_default_ctsrtsrx:
+				qupv3_se5_default_ctsrtsrx {
+				mux {
+					pins = "gpio26", "gpio27", "gpio29";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio26", "gpio27", "gpio29";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+
+			qupv3_se5_default_tx: qupv3_se5_default_tx {
+				mux {
+					pins = "gpio28";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio28";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se5_ctsrx: qupv3_se5_ctsrx {
+				mux {
+					pins = "gpio26", "gpio29";
+					function = "qup05";
+				};
+
+				config {
+					pins = "gpio26", "gpio29";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se5_rts: qupv3_se5_rts {
+				mux {
+					pins = "gpio27";
+					function = "qup05";
+				};
+
+				config {
+					pins = "gpio27";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+
+			qupv3_se5_tx: qupv3_se5_tx {
+				mux {
+					pins = "gpio28";
+					function = "qup05";
+				};
+
+				config {
+					pins = "gpio28";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+		};
+
+		/* WSA speaker reset pin1 */
+		spkr_1_sd_n {
+			spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
+				mux {
+					pins = "gpio80";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio80";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;
+					input-enable;
+				};
+			};
+
+			spkr_1_sd_n_active: spkr_1_sd_n_active {
+				mux {
+					pins = "gpio80";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio80";
+					drive-strength = <16>;   /* 16 mA */
+					bias-disable;
+					output-high;
+				};
+			};
+		};
+
+		cci0_suspend: cci0_suspend {
+			mux {
+				/* CLK, DATA*/
+				pins = "gpio38", "gpio37";
+				function = "cci_i2c";
+			};
+
+			config {
+				pins = "gpio38", "gpio37";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable; /* No PULL */
+			};
+		};
+
+		cci0_active: cci0_active {
+			mux {
+				/* CLK, DATA*/
+				pins = "gpio38", "gpio37";
+				function = "cci_i2c";
+			};
+
+			config {
+				pins = "gpio38", "gpio37";
+				bias-pull-up; /* PULL UP*/
+				drive-strength = <2>; /* 2 MA */
+			};
+		};
+
+		cci1_suspend: cci1_suspend {
+			mux {
+				/* CLK, DATA*/
+				pins = "gpio40", "gpio39";
+				function = "cci_i2c";
+			};
+
+			config {
+				pins = "gpio40", "gpio39";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable; /* No PULL */
+			};
+		};
+
+		cci1_active: cci1_active {
+			mux {
+				/* CLK, DATA*/
+				pins = "gpio40", "gpio39";
+				function = "cci_i2c";
+			};
+
+			config {
+				pins = "gpio40", "gpio39";
+				bias-pull-up; /* PULL UP*/
+				drive-strength = <2>; /* 2 MA */
+			};
+		};
+
+		cam_sensor_mclk0_active: cam_sensor_mclk0_active {
+			/* MCLK 0*/
+			mux {
+				pins = "gpio32";
+				function = "cam_mclk";
+			};
+
+			config {
+				pins = "gpio32";
+				bias-disable; /* No PULL */
+				drive-strength = <2>; /* 2 MA */
+			};
+		};
+
+		cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
+			/* MCLK 0*/
+			mux {
+				pins = "gpio32";
+				function = "cam_mclk";
+			};
+
+			config {
+				pins = "gpio32";
+				bias-pull-down; /* PULL DOWN */
+				drive-strength = <2>; /* 2 MA */
+			};
+		};
+
+		cam_sensor_mclk1_active: cam_sensor_mclk1_active {
+			/* MCLK 1*/
+			mux {
+				pins = "gpio33";
+				function = "cam_mclk";
+			};
+
+			config {
+				pins = "gpio33";
+				bias-disable; /* No PULL */
+				drive-strength = <2>; /* 2 MA */
+			};
+		};
+
+		cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
+			/* MCLK 1*/
+			mux {
+				pins = "gpio33";
+				function = "cam_mclk";
+			};
+
+			config {
+				pins = "gpio33";
+				bias-pull-down; /* PULL DOWN */
+				drive-strength = <2>; /* 2 MA */
+			};
+		};
+
+		cam_sensor_rear0_reset_active: cam_sensor_rear0_reset_active {
+			/* RESET0 */
+			mux {
+				pins = "gpio35";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio35";
+				bias-disable; /* No PULL */
+				drive-strength = <2>; /* 2 MA */
+			};
+		};
+
+		cam_sensor_rear0_reset_suspend: cam_sensor_rear0_reset_suspend {
+			/* RESET0 */
+			mux {
+				pins = "gpio35";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio35";
+				bias-pull-down; /* PULL DOWN */
+				drive-strength = <2>; /* 2 MA */
+				output-low;
+			};
+		};
+
+		cam_sensor_front0_reset_active: cam_sensor_front0_reset_active {
+			/* RESET0 */
+			mux {
+				pins = "gpio36";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio36";
+				bias-disable; /* No PULL */
+				drive-strength = <2>; /* 2 MA */
+			};
+		};
+
+		cam_sensor_front0_reset_suspend: cam_sensor_front0_reset_suspend {
+			/* RESET0 */
+			mux {
+				pins = "gpio36";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio36";
+				bias-pull-down; /* PULL DOWN */
+				drive-strength = <2>; /* 2 MA */
+				output-low;
+			};
+		};
+
+		/* SDC pin type */
+		sdc1_on: sdc1_on {
+			clk {
+				pins = "sdc1_clk";
+				bias-disable;
+				drive-strength = <8>;
+			};
+
+			cmd {
+				pins = "sdc1_cmd";
+				bias-pull-up;
+				drive-strength = <8>;
+			};
+
+			data {
+				pins = "sdc1_data";
+				bias-pull-up;
+				drive-strength = <8>;
+			};
+
+			rclk {
+				pins = "sdc1_rclk";
+				bias-pull-down;
+			};
+		};
+
+		sdc1_off: sdc1_off {
+			clk {
+				pins = "sdc1_clk";
+				bias-disable;
+				drive-strength = <2>;
+			};
+
+			cmd {
+				pins = "sdc1_cmd";
+				bias-pull-up;
+				drive-strength = <2>;
+			};
+
+			data {
+				pins = "sdc1_data";
+				bias-pull-up;
+				drive-strength = <2>;
+			};
+
+			rclk {
+				pins = "sdc1_rclk";
+				bias-pull-down;
+			};
+		};
+
+		pmx_ts_int_active {
+			ts_int_active: ts_int_active {
+				mux {
+					pins = "gpio13";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio13";
+					drive-strength = <8>;
+					bias-pull-up;
+				};
+			};
+		};
+
+		pmx_ts_int_suspend {
+			ts_int_suspend: ts_int_suspend {
+				mux {
+					pins = "gpio13";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio13";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+		};
+
+		pmx_ts_reset_active {
+			ts_reset_active: ts_reset_active {
+				mux {
+					pins = "gpio12";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio12";
+					drive-strength = <8>;
+					bias-pull-up;
+				};
+			};
+		};
+
+		pmx_ts_reset_suspend {
+			ts_reset_suspend: ts_reset_suspend {
+				mux {
+					pins = "gpio12";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio12";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+		};
+
+		pmx_ts_release {
+			ts_release: ts_release {
+				mux {
+					pins = "gpio13", "gpio12";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio13", "gpio12";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+		};
+
+		pmx_sde_te {
+			sde_te_active: sde_te_active {
+				mux {
+					pins = "gpio73";
+					function = "mdp_vsync";
+				};
+
+				config {
+					pins = "gpio73";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+
+			sde_te_suspend: sde_te_suspend {
+				mux {
+					pins = "gpio73";
+					function = "mdp_vsync";
+				};
+
+				config {
+					pins = "gpio73";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+		};
+	};
+};
diff --git a/qcom/monaco-pmic.dtsi b/qcom/monaco-pmic.dtsi
new file mode 100644
index 00000000..bda28b85
--- /dev/null
+++ b/qcom/monaco-pmic.dtsi
@@ -0,0 +1,188 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/iio/qti_power_supply_iio.h>
+
+&pm5100_gpios {
+	key_vol_up {
+		key_vol_up_default: key_vol_up_default {
+			pins = "gpio9";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+			power-source = <1>;
+		};
+	};
+
+	pmx_sde: pmx_sde {
+		sde_dsi_active: sde_dsi_active {
+			pinconf {
+				pins = "gpio1", "gpio2";
+				function = "normal";
+				qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+				bias-disable;
+				output-high;
+			};
+		};
+
+		sde_dsi_suspend: sde_dsi_suspend {
+			pinconf {
+				pins = "gpio1", "gpio2";
+				function = "normal";
+				qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+				bias-pull-down;
+				output-low;
+			};
+		};
+	};
+};
+
+&soc {
+	gpio_keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_vol_up_default>;
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&pm5100_gpios 9 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEUP>;
+			gpio-key,wakeup;
+			debounce-interval = <15>;
+			linux,can-disable;
+		};
+	};
+};
+
+&pm5100_adc {
+	#thermal-sensor-cells = <1>;
+	status = "ok";
+
+	pm5100_xo_therm {
+		qcom,adc-tm-type = <1>;
+	};
+
+	pm5100_pa_therm_0 {
+		reg = <PM5100_ADC5_GEN3_AMUX4_THM_100K_PU>;
+		label = "pm5100_pa_therm_0";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		qcom,adc-tm-type = <1>;
+	};
+
+	pm5100_quiet_therm {
+		reg = <PM5100_ADC5_GEN3_AMUX5_THM_100K_PU>;
+		label = "pm5100_quiet_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		qcom,adc-tm-type = <1>;
+	};
+
+	pm5100_msm_therm {
+		reg = <PM5100_ADC5_GEN3_AMUX6_THM_100K_PU>;
+		label = "pm5100_msm_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		qcom,adc-tm-type = <1>;
+	};
+
+	pm5100_bat_id {
+		qcom,hw-settle-time = <16000>;
+	};
+};
+
+&thermal_zones {
+	xo-therm-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX1_THM_100K_PU>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	pa-therm0-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX4_THM_100K_PU>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	quiet-therm-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX5_THM_100K_PU>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdm-skin-therm-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX6_THM_100K_PU>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+};
+
+&soc {
+	reboot_reason {
+		compatible = "qcom,reboot-reason";
+		nvmem-cells = <&restart_reason>;
+		nvmem-cell-names = "restart_reason";
+	};
+
+	monaco_batterydata: qcom,battery-data {
+		qcom,batt-id-range-pct = <15>;
+	};
+};
+
+&pm5100_charger {
+	status = "okay";
+	qcom,battery-data = <&monaco_batterydata>;
+	dpdm-supply = <&usb2_phy0>;
+	nvmem-cell-names = "charger_debug_mask";
+	nvmem-cells = <&charger_debug_mask>;
+	qcom,auto-recharge-soc = <98>;
+	qcom,suspend-input-on-debug-batt;
+	qcom,chg-term-src = <1>;
+	qcom,chg-term-current-ma = <(-20)>;
+	qcom,fcc-stepping-enable;
+	qcom,fcc-step-delay-ms = <1000>;
+	qcom,fcc-step-size-ua = <100000>;
+	qcom,fcc-step-start-ua = <200000>;
+	qcom,concurrency-mode-supported;
+};
diff --git a/qcom/monaco-regulators.dtsi b/qcom/monaco-regulators.dtsi
new file mode 100644
index 00000000..ee9b490a
--- /dev/null
+++ b/qcom/monaco-regulators.dtsi
@@ -0,0 +1,547 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+
+&rpm_bus {
+	/* PM5100 L1 - VDD_CX supply */
+	rpm-regulator-smpa1 {
+		status = "okay";
+		qcom,resource-name = "rwcx";
+		qcom,resource-id = <0>;
+		proxy-supply = <&VDD_CX_LEVEL>;
+		VDD_CX_LEVEL:
+		S1A_LEVEL: pm5100_s1_level: regulator-s1-level {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_s1_level";
+			qcom,set = <3>;
+			regulator-min-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,init-voltage-level =
+				<RPM_SMD_REGULATOR_LEVEL_TURBO>;
+			qcom,proxy-consumer-enable;
+			qcom,proxy-consumer-voltage =
+				<RPM_SMD_REGULATOR_LEVEL_TURBO
+				 RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-level;
+		};
+
+		VDD_CX_FLOOR_LEVEL:
+		S1A_FLOOR_LEVEL:
+		pm5100_s1_floor_level: regulator-s1-floor-level {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_s1_floor_level";
+			qcom,set = <3>;
+			regulator-min-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-floor-level;
+			qcom,always-send-voltage;
+		};
+
+		VDD_CX_LEVEL_AO:
+		S1A_LEVEL_AO: pm5100_s1_level_ao: regulator-s1-level-ao {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_s1_level_ao";
+			qcom,set = <1>;
+			regulator-min-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+					<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-level;
+		};
+
+		cx_cdev: cx-cdev-lvl {
+			compatible = "qcom,regulator-cooling-device";
+			regulator-cdev-supply = <&VDD_CX_FLOOR_LEVEL>;
+			regulator-levels = <RPM_SMD_REGULATOR_LEVEL_NONE
+					RPM_SMD_REGULATOR_LEVEL_NOM>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	rpm-regulator-smpa3 {
+		status = "okay";
+		S3A: pm5100_s3: regulator-s3 {
+			regulator-min-microvolt = <1144000>;
+			regulator-max-microvolt = <1320000>;
+			qcom,init-voltage = <1320000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-smpa4 {
+		status = "okay";
+		S4A: pm5100_s4: regulator-s4 {
+			regulator-min-microvolt = <1816000>;
+			regulator-max-microvolt = <1904000>;
+			qcom,init-voltage = <1904000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-smpa5 {
+		status = "okay";
+		S5A: pm5100_s5: regulator-s5 {
+			regulator-min-microvolt = <664000>;
+			regulator-max-microvolt = <1000000>;
+			qcom,init-voltage = <952000>;
+			status = "okay";
+		};
+	};
+
+	/* VDD_LPI_CX supply */
+	rpm-regulator-ldoa4 {
+		status = "okay";
+		qcom,resource-name = "rwlc";
+		qcom,resource-id = <0>;
+		VDD_LPI_CX_LEVEL:
+		L4A_LEVEL: pm5100_l4_level: regulator-l4-level {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l4_level";
+			qcom,set = <3>;
+			regulator-min-microvolt =
+				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-level;
+		};
+	};
+
+	/* VDD_LPI_MX supply */
+	rpm-regulator-ldoa5 {
+		status = "okay";
+		qcom,resource-name = "rwlm";
+		qcom,resource-id = <0>;
+		VDD_LPI_MX_LEVEL:
+		L5A_LEVEL: pm5100_l5_level: regulator-l5-level {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l5_level";
+			qcom,set = <3>;
+			regulator-min-microvolt =
+				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-level;
+		};
+	};
+
+	rpm-regulator-ldoa1 {
+		status = "okay";
+		L1A: pm5100_l1: regulator-l1 {
+			regulator-min-microvolt = <504000>;
+			regulator-max-microvolt = <752000>;
+			qcom,init-voltage = <504000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa2 {
+		status = "okay";
+		L2A: pm5100_l2: regulator-l2 {
+			regulator-min-microvolt = <312000>;
+			regulator-max-microvolt = <888000>;
+			qcom,init-voltage = <824000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa3 {
+		status = "okay";
+		qcom,resource-name = "rwmx";
+		qcom,resource-id = <0>;
+		proxy-supply = <&VDD_MXA_LEVEL>;
+
+		VDD_MX_LEVEL:
+		VDD_MXA_LEVEL:
+		VDD_EBI_LEVEL:
+		L3A_LEVEL:
+		pm5100_l3_level: regulator-pm5100-l3-level {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l3_level";
+			qcom,set = <3>;
+			regulator-min-microvolt =
+				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,proxy-consumer-enable;
+			qcom,proxy-consumer-voltage =
+				<RPM_SMD_REGULATOR_LEVEL_TURBO
+				 RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-level;
+		};
+
+		VDD_MX_LEVEL_AO:
+		VDD_MXA_LEVEL_AO:
+		VDD_EBI_LEVEL_AO:
+		L3A_LEVEL_AO:
+		pm5100_l3_level_ao: regulator-pm5100-l3-level-ao {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l3_level_ao";
+			qcom,set = <1>;
+			regulator-min-microvolt =
+				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt =
+				<RPM_SMD_REGULATOR_LEVEL_BINNING>;
+			qcom,use-voltage-level;
+		};
+
+		mx_cdev: mx-cdev-lvl {
+			compatible = "qcom,regulator-cooling-device";
+			regulator-cdev-supply = <&VDD_MXA_LEVEL>;
+			regulator-levels = <RPM_SMD_REGULATOR_LEVEL_NONE
+					RPM_SMD_REGULATOR_LEVEL_NOM>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	rpm-regulator-ldoa7 {
+		status = "okay";
+		L7A: pm5100_l7: regulator-l7 {
+			regulator-min-microvolt = <624000>;
+			regulator-max-microvolt = <624000>;
+			qcom,init-voltage = <624000>;
+			status = "okay";
+		};
+	};
+
+	/* WCSS_CX and WCSS_MX */
+	rpm-regulator-ldoa8 {
+		status = "okay";
+		qcom,supported-modes =
+			<RPM_SMD_REGULATOR_MODE_RET
+			RPM_SMD_REGULATOR_MODE_LPM
+			RPM_SMD_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000 30000>;
+		WCSS_CX:
+		WCSS_MX:
+		L8A: pm5100_l8: regulator-l8 {
+			regulator-min-microvolt = <312000>;
+			regulator-max-microvolt = <752000>;
+			qcom,init-voltage = <752000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa9 {
+		status = "okay";
+		L9A: pm5100_l9: regulator-l9 {
+			regulator-min-microvolt = <1232000>;
+			regulator-max-microvolt = <1232000>;
+			qcom,init-voltage = <1232000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa10 {
+		status = "okay";
+		L10A: pm5100_l10: regulator-l10 {
+			regulator-min-microvolt = <1128000>;
+			regulator-max-microvolt = <1128000>;
+			qcom,init-voltage = <1128000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa11 {
+		status = "okay";
+		L11A: pm5100_l11: regulator-l11 {
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1000000>;
+			qcom,init-voltage = <1000000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa12 {
+		status = "okay";
+		L12A: pm5100_l12: regulator-l12 {
+			regulator-min-microvolt = <904000>;
+			regulator-max-microvolt = <904000>;
+			qcom,init-voltage = <904000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa13 {
+		status = "okay";
+		qcom,supported-modes =
+			<RPM_SMD_REGULATOR_MODE_RET
+			RPM_SMD_REGULATOR_MODE_LPM
+			RPM_SMD_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000 30000>;
+		L13A: pm5100_l13: regulator-l13 {
+			regulator-min-microvolt = <1304000>;
+			regulator-max-microvolt = <1304000>;
+			qcom,init-voltage = <1304000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa14 {
+		status = "okay";
+		L14A: pm5100_l14: regulator-l14 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa15 {
+		status = "okay";
+		L15A: pm5100_l15: regulator-l15 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa16 {
+		status = "okay";
+		L16A: pm5100_l16: regulator-l16 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa17 {
+		status = "okay";
+		L17A: pm5100_l17: regulator-l17 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa18 {
+		status = "okay";
+		L18A: pm5100_l18: regulator-l18 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa19 {
+		status = "okay";
+		L19A: pm5100_l19: regulator-l19 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa20 {
+		status = "okay";
+		L20A: pm5100_l20: regulator-l20 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa21 {
+		status = "okay";
+		L21A: pm5100_l21: regulator-l21 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa22 {
+		status = "okay";
+		L22A: pm5100_l22: regulator-l22 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa23 {
+		status = "okay";
+		L23A: pm5100_l23: regulator-l23 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa24 {
+		status = "okay";
+		L24A: pm5100_l24: regulator-l24 {
+			regulator-min-microvolt = <3304000>;
+			regulator-max-microvolt = <3304000>;
+			qcom,init-voltage = <3304000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa25 {
+		status = "okay";
+		L25A: pm5100_l25: regulator-l25 {
+			parent-supply = <&L12A>;
+			regulator-min-microvolt = <3080000>;
+			regulator-max-microvolt = <3080000>;
+			qcom,init-voltage = <3080000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa26 {
+		status = "okay";
+		L26A: pm5100_l26: regulator-l26 {
+			regulator-min-microvolt = <3304000>;
+			regulator-max-microvolt = <3304000>;
+			qcom,init-voltage = <3304000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa27 {
+		status = "okay";
+		L27A: pm5100_l27: regulator-l27 {
+			regulator-min-microvolt = <2704000>;
+			regulator-max-microvolt = <2704000>;
+			qcom,init-voltage = <2704000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa28 {
+		status = "okay";
+		L28A: pm5100_l28: regulator-l28 {
+			regulator-min-microvolt = <2904000>;
+			regulator-max-microvolt = <2904000>;
+			qcom,init-voltage = <2904000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldoa29 {
+		status = "okay";
+		L29A: pm5100_l29: regulator-l29 {
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			qcom,init-voltage = <2800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-boba {
+		status = "okay";
+		qcom,supported-modes =
+			<RPM_SMD_REGULATOR_MODE_PASS
+			RPM_SMD_REGULATOR_MODE_LPM
+			RPM_SMD_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1000000 2000000>;
+
+		BOB: pm5100a_bob: regulator-pm5100a-bob {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <4800000>;
+			qcom,init-voltage = <3300000>;
+			qcom,init-bob-mode = <RPM_SMD_REGULATOR_MODE_PASS>;
+			status = "okay";
+		};
+
+		BOB_AO: pm5100a_bob_ao: regulator-pm5100a-bob-ao {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <4800000>;
+			qcom,init-voltage = <3300000>;
+			qcom,init-bob-mode = <RPM_SMD_REGULATOR_MODE_AUTO>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldom1 {
+		status = "okay";
+		L1C: pm8010_l1: regulator-l1 {
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1200000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldom2 {
+		status = "okay";
+		L2C: pm8010_l2: regulator-l2 {
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1200000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldom3 {
+		status = "okay";
+		L3C: pm8010_l3: regulator-l3 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldom4 {
+		status = "okay";
+		L4C: pm8010_l4: regulator-l4 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldom5 {
+		status = "okay";
+		L5C: pm8010_l5: regulator-l5 {
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			qcom,init-voltage = <2800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldom6 {
+		status = "okay";
+		L6C: pm8010_l6: regulator-l6 {
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			qcom,init-voltage = <2800000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-ldom7 {
+		status = "okay";
+		L7C: pm8010_l7: regulator-l7 {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			qcom,init-voltage = <3000000>;
+			status = "okay";
+		};
+	};
+
+	rpm-regulator-chg-boost {
+		status = "okay";
+		SPKR_BOOST: pm5100_chg_boost: regulator-chg-boost {
+			regulator-min-microvolt = <4100000>;
+			regulator-max-microvolt = <5600000>;
+			qcom,init-voltage = <4100000>;
+			status = "okay";
+		};
+	};
+};
diff --git a/qcom/monaco-thermal-overlay.dtsi b/qcom/monaco-thermal-overlay.dtsi
new file mode 100644
index 00000000..eba02e00
--- /dev/null
+++ b/qcom/monaco-thermal-overlay.dtsi
@@ -0,0 +1,106 @@
+#include <dt-bindings/thermal/thermal_qti.h>
+
+&thermal_zones {
+	pm5100-tz {
+		cooling-maps {
+			trip0_cpu0 {
+				trip = <&pm5100_trip0>;
+				cooling-device =
+					<&CPU0 (THERMAL_MAX_LIMIT-2)
+						(THERMAL_MAX_LIMIT-2)>;
+			};
+
+			trip1_cpu2 {
+				trip = <&pm5100_trip0>;
+				cooling-device = <&cpu2_isolate 1 1>;
+			};
+
+			trip1_cpu3 {
+				trip = <&pm5100_trip0>;
+				cooling-device = <&cpu3_isolate 1 1>;
+			};
+		};
+	};
+
+	pm5100-bcl-lvl0 {
+		cooling-maps {
+			cpu0_cdev {
+				trip = <&bcl_lvl0>;
+				cooling-device =
+					<&CPU0 (THERMAL_MAX_LIMIT-1)
+						(THERMAL_MAX_LIMIT-1)>;
+			};
+
+			cpu2_cdev {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&cpu2_isolate 1 1>;
+			};
+
+			cpu3_cdev {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&cpu3_isolate 1 1>;
+			};
+
+			gpu_cdev {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-2)
+							(THERMAL_MAX_LIMIT-2)>;
+			};
+		};
+	};
+
+	pm5100-bcl-lvl1 {
+		cooling-maps {
+			cpu0_cdev {
+				trip = <&bcl_lvl1>;
+				cooling-device =
+					<&CPU0 (THERMAL_MAX_LIMIT-1)
+						(THERMAL_MAX_LIMIT-1)>;
+			};
+
+			cpu1_cdev {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&cpu1_isolate 1 1>;
+			};
+
+			gpu_cdev {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+		};
+	};
+
+	pm5100-bcl-lvl2 {
+		cooling-maps {
+			/* Need to update once we get fine tuned data */
+		};
+	};
+
+	socd {
+		cooling-maps {
+			soc_cpu0 {
+				trip = <&socd_trip>;
+				cooling-device =
+					<&CPU0 (THERMAL_MAX_LIMIT-2)
+						(THERMAL_MAX_LIMIT-2)>;
+			};
+
+			soc_cpu2 {
+				trip = <&socd_trip>;
+				cooling-device = <&cpu2_isolate 1 1>;
+			};
+
+			soc_cpu3 {
+				trip = <&socd_trip>;
+				cooling-device = <&cpu3_isolate 1 1>;
+			};
+
+			gpu_cdev {
+				trip = <&socd_trip>;
+				cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-2)
+							(THERMAL_MAX_LIMIT-2)>;
+			};
+		};
+	};
+};
diff --git a/qcom/monaco-thermal.dtsi b/qcom/monaco-thermal.dtsi
new file mode 100644
index 00000000..233a7f76
--- /dev/null
+++ b/qcom/monaco-thermal.dtsi
@@ -0,0 +1,485 @@
+#include <dt-bindings/thermal/thermal_qti.h>
+
+&cpufreq_hw {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	lmh_dcvs0: qcom,limits-dcvs@f550800 {
+		compatible = "qcom,msm-hw-limits";
+		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,affinity = <0>;
+		reg = <0xf550800 0x1000>,
+			<0xf521000 0x1000>;
+		qcom,no-cooling-device-register;
+	};
+
+	qcom,cpu-isolation {
+		compatible = "qcom,cpu-isolate";
+		cpu0_isolate: cpu0-isolate {
+			qcom,cpu = <&CPU0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu1_isolate: cpu1-isolate {
+			qcom,cpu = <&CPU1>;
+			#cooling-cells = <2>;
+		};
+
+		cpu2_isolate: cpu2-isolate {
+			qcom,cpu = <&CPU2>;
+			#cooling-cells = <2>;
+		};
+
+		cpu3_isolate: cpu3-isolate {
+			qcom,cpu = <&CPU3>;
+			#cooling-cells = <2>;
+		};
+	};
+};
+
+&soc {
+	tsens0:tsens@4410000 {
+		compatible = "qcom,tsens26xx";
+		reg = <0x04410000 0x20>,
+			<0x04411000 0x140>;
+		reg-names = "tsens_srot_physical",
+				"tsens_tm_physical";
+		interrupts-extended = <&intc 0 275 IRQ_TYPE_LEVEL_HIGH>,
+				<&intc 0 190 IRQ_TYPE_LEVEL_HIGH>,
+				<&wakegic 89 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "tsens-upper-lower",
+				"tsens-critical",
+				"tsens-0C";
+		tsens-reinit-wa;
+		0C-sensor-num = <16>;
+		#thermal-sensor-cells = <1>;
+	};
+
+	qmi-tmd-devices {
+		compatible = "qcom,qmi-cooling-devices";
+
+		modem {
+			qcom,instance-id = <QMI_MODEM_INST_ID>;
+
+			modem_pa: modem_pa {
+				qcom,qmi-dev-name = "pa";
+				#cooling-cells = <2>;
+			};
+
+			modem_tj: modem_tj {
+				qcom,qmi-dev-name = "modem";
+				#cooling-cells = <2>;
+			};
+
+			modem_skin: modem_skin {
+				qcom,qmi-dev-name = "modem_skin";
+				#cooling-cells = <2>;
+			};
+
+			modem_wlan: modem_wlan {
+				qcom,qmi-dev-name = "wlan";
+				#cooling-cells = <2>;
+			};
+
+			modem_tmd_rf_cal: modem_tmd_rf_cal {
+				qcom,qmi-dev-name = "tmd_rf_cal";
+				#cooling-cells = <2>;
+			};
+		};
+
+		adsp {
+			qcom,instance-id = <QMI_ADSP_INST_ID>;
+
+			adsp_vdd: adsp_vdd {
+				qcom,qmi-dev-name = "cpuv_restriction_cold";
+				#cooling-cells = <2>;
+			};
+		};
+	};
+
+	qmi_sensor: qmi-ts-sensors {
+		compatible = "qcom,qmi-sensors";
+		#thermal-sensor-cells = <1>;
+
+		modem {
+			qcom,instance-id = <QMI_MODEM_INST_ID>;
+			qcom,qmi-sensor-names = "rf_cal";
+		};
+	};
+
+	lmh_cpu_vdd: qcom,lmh-cpu-vdd@f550800 {
+		compatible = "qcom,lmh-cpu-vdd";
+		reg =  <0xf550800 0x1000>;
+		#cooling-cells = <2>;
+	};
+};
+
+&thermal_zones {
+	gpu-step {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&tsens0 6>;
+		trips {
+			gpu_step_trip: gpu-trip {
+				temperature = <85000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			gpu_cx_mon: gpu-cx-mon {
+				temperature = <90000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+		};
+
+		cooling-maps {
+			gpu-cdev {
+				trip = <&gpu_step_trip>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+
+			gpu-cx-cdev0 {
+				trip = <&gpu_cx_mon>;
+				cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+
+			gpu-cx-cdev1 {
+				trip = <&gpu_cx_mon>;
+				cooling-device = <&modem_tj 3 3>;
+			};
+		};
+	};
+
+	cpuss-0-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&tsens0 2>;
+		trips {
+			cpu0_2_config: cpu-0-2-config {
+				temperature = <100000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu0_cdev {
+				trip = <&cpu0_2_config>;
+				cooling-device = <&cpu0_isolate 1 1>;
+			};
+
+			cpu2_cdev {
+				trip = <&cpu0_2_config>;
+				cooling-device = <&cpu2_isolate 1 1>;
+			};
+		};
+	};
+
+	cpuss-1-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&tsens0 3>;
+		trips {
+			cpu1_3_config: cpu-1-3-config {
+				temperature = <100000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu1_cdev {
+				trip = <&cpu1_3_config>;
+				cooling-device = <&cpu1_isolate 1 1>;
+			};
+
+			cpu3_cdev {
+				trip = <&cpu1_3_config>;
+				cooling-device = <&cpu3_isolate 1 1>;
+			};
+		};
+	};
+
+	mdm-0-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&tsens0 4>;
+		trips {
+			mdm0_cx_mon: mdm0-cx-mon {
+				temperature = <90000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			mdm0-cx-cdev0 {
+				trip = <&mdm0_cx_mon>;
+				cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+
+			mdm0-cx-cdev1 {
+				trip = <&mdm0_cx_mon>;
+				cooling-device = <&modem_tj 3 3>;
+			};
+		};
+	};
+
+	mdm-1-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&tsens0 5>;
+		trips {
+			mdm1_cx_mon: mdm1-cx-mon {
+				temperature = <90000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			mdm1-cx-cdev0 {
+				trip = <&mdm1_cx_mon>;
+				cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+
+			mdm1-cx-cdev1 {
+				trip = <&mdm1_cx_mon>;
+				cooling-device = <&modem_tj 3 3>;
+			};
+		};
+	};
+
+	mapss-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens0 0>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	wlan-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens0 1>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpuss-0-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens0 2>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpuss-1-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens0 3>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	mdm-0-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens0 4>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	mdm-1-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens0 5>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	gpu-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens0 6>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	camera-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens0 7>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
+	zeroc-0-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 16>;
+		thermal-governor = "step_wise";
+		trips {
+			zeroc_0_trip: active-config0 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			lmh_cpu_cdev {
+				trip = <&zeroc_0_trip>;
+				cooling-device = <&lmh_cpu_vdd 1 1>;
+			};
+
+			cx_vdd_cdev {
+				trip = <&zeroc_0_trip>;
+				cooling-device = <&cx_cdev 1 1>;
+			};
+
+			mx_vdd_cdev {
+				trip = <&zeroc_0_trip>;
+				cooling-device = <&mx_cdev 1 1>;
+			};
+
+			adsp_vdd_cdev {
+				trip = <&zeroc_0_trip>;
+				cooling-device = <&adsp_vdd 1 1>;
+			};
+		};
+	};
+
+	rf_cal {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID)>;
+		thermal-governor = "step_wise";
+		trips {
+			rf_cal_trip: rf-cal-config {
+				temperature = <2000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			bcl_off_cdev {
+				trip = <&rf_cal_trip>;
+				cooling-device = <&bcl_off 1 1>;
+			};
+
+			tmd_rf_cal_cdev {
+				trip = <&rf_cal_trip>;
+				cooling-device = <&modem_tmd_rf_cal 1 1>;
+			};
+		};
+	};
+};
diff --git a/qcom/monaco-usb.dtsi b/qcom/monaco-usb.dtsi
new file mode 100644
index 00000000..93f83c5d
--- /dev/null
+++ b/qcom/monaco-usb.dtsi
@@ -0,0 +1,140 @@
+#include <dt-bindings/clock/qcom,gcc-monaco.h>
+#include <dt-bindings/interconnect/qcom,monaco.h>
+
+&soc {
+	/* Primary USB port related controller */
+	usb0: hsusb@4e00000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0x4e00000 0x100000>;
+		reg-names = "core_base";
+
+		iommus = <&apps_smmu 0x120 0x0>;
+		qcom,iommu-dma = "atomic";
+		qcom,iommu-dma-addr-pool = <0x50000000 0x60000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		dma-ranges;
+
+		interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pwr_event_irq", "hs_phy_irq";
+
+		clocks = <&gcc GCC_USB20_MASTER_CLK>,
+			<&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
+			<&gcc GCC_SYS_NOC_USB2_PRIM_AXI_CLK>,
+			<&gcc GCC_USB2_PRIM_CLKREF_CLK>,
+			<&gcc GCC_USB20_SLEEP_CLK>,
+			<&gcc GCC_USB20_MOCK_UTMI_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+				"xo", "sleep_clk", "utmi_clk";
+
+		resets = <&gcc GCC_USB20_PRIM_BCR>;
+		reset-names = "core_reset";
+
+		USB3_GDSC-supply = <&gcc_usb20_prim_gdsc>;
+		dpdm-supply = <&usb2_phy0>;
+		qcom,usb-charger;
+		extcon = <&eud>;
+
+		qcom,core-clk-rate = <60000000>;
+		qcom,default-bus-vote = <2>; /* use svs bus voting */
+
+		interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
+		interconnects = <&system_noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
+				<&system_noc MASTER_USB3 &config_noc SLAVE_IPA_CFG>,
+				<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>;
+
+		qcom,interconnect-values-svs = /* SVS Votes */
+						<30000 70000>,
+						<0 2400>,
+						<0 40000>;
+
+		qcom,num-gsi-evt-buffs = <0x3>;
+		qcom,gsi-reg-offset =
+			<0x0fc /* GSI_GENERAL_CFG */
+			0x110 /* GSI_DBL_ADDR_L */
+			0x120 /* GSI_DBL_ADDR_H */
+			0x130 /* GSI_RING_BASE_ADDR_L */
+			0x144 /* GSI_RING_BASE_ADDR_H */
+			0x1a4>; /* GSI_IF_STS */
+		qcom,dwc-usb3-msm-tx-fifo-size = <10488>;
+
+		dwc3@4e00000 {
+			compatible = "snps,dwc3";
+			reg = <0x4e00000 0xcd00>;
+			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+			usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
+			tx-fifo-resize;
+			linux,sysdev_is_parent;
+			snps,disable-clk-gating;
+			snps,is-utmi-l1-suspend;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_enblslpm_quirk;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			maximum-speed = "high-speed";
+			max-num-endpoints = /bits/ 8 <16>;
+			dr_mode = "otg";
+		};
+
+		qcom,usbbam@0x04f04000 {
+			compatible = "qcom,usb-bam-msm";
+			reg = <0x04f04000 0x17000>;
+			interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
+
+			qcom,usb-bam-fifo-baseaddr = <0xc121000>;
+			qcom,usb-bam-num-pipes = <4>;
+			qcom,disable-clk-gating;
+			qcom,usb-bam-override-threshold = <0x4001>;
+			qcom,usb-bam-max-mbps-highspeed = <400>;
+			qcom,reset-bam-on-connect;
+
+			qcom,pipe0 {
+				label = "hsusb-qdss-in-0";
+				qcom,usb-bam-mem-type = <2>;
+				qcom,dir = <1>;
+				qcom,pipe-num = <0>;
+				qcom,peer-bam = <0>;
+				qcom,peer-bam-physical-address = <0x08064000>;
+				qcom,src-bam-pipe-index = <0>;
+				qcom,dst-bam-pipe-index = <0>;
+				qcom,data-fifo-offset = <0x0>;
+				qcom,data-fifo-size = <0x1800>;
+				qcom,descriptor-fifo-offset = <0x1800>;
+				qcom,descriptor-fifo-size = <0x800>;
+			};
+		};
+	};
+
+	/* Primary USB port related High Speed PHY */
+	usb2_phy0: hsphy@1613000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x1613000 0x120>,
+			<0x01612000 0x4>;
+		reg-names = "hsusb_phy_base",
+			"eud_enable_reg";
+
+		vdd-supply = <&L12A>;
+		vdda18-supply = <&L14A>;
+		vdda33-supply = <&L25A>;
+		qcom,vdd-voltage-level = <0 904000 904000>;
+
+		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+		clock-names = "ref_clk_src";
+
+		resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+		reset-names = "phy_reset";
+		qcom,param-override-seq =
+			<0x63 0x6c	/* override_x0 */
+			 0xC8 0x70	/* override_x1 */
+			 0x17 0x74>;	/* override x2 */
+	};
+
+	usb_nop_phy: usb_nop_phy {
+		compatible = "usb-nop-xceiv";
+	};
+
+};
diff --git a/qcom/monaco.dts b/qcom/monaco.dts
new file mode 100644
index 00000000..c9446f70
--- /dev/null
+++ b/qcom/monaco.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "monaco.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco SoC";
+	compatible = "qcom,monaco";
+	qcom,board-id = <0 0>;
+};
diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi
new file mode 100644
index 00000000..c6098997
--- /dev/null
+++ b/qcom/monaco.dtsi
@@ -0,0 +1,1276 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,dispcc-monaco.h>
+#include <dt-bindings/clock/qcom,gcc-monaco.h>
+#include <dt-bindings/clock/qcom,gpucc-monaco.h>
+#include <dt-bindings/soc/qcom,dcc_v2.h>
+#include <dt-bindings/interconnect/qcom,monaco.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco";
+	compatible = "qcom,monaco";
+	qcom,msm-id = <486 0x10000>;
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+	memory { device_type = "memory"; reg = <0 0 0 0>; };
+
+	aliases {
+		sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/
+	};
+
+	firmware: firmware {};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			d-cache-size = <0x8000>;
+			i-cache-size = <0x8000>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			next-level-cache = <&L2_0>;
+			qcom,freq-domain = <&cpufreq_hw 0 4>;
+			qcom,lmh-dcvs = <&lmh_dcvs0>;
+			#cooling-cells = <2>;
+			L2_0: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-size = <0x80000>;
+			      cache-level = <2>;
+			};
+
+			L1_I_0: l1-icache {
+			      compatible = "arm,arch-cache";
+			};
+
+			L1_D_0: l1-dcache {
+			      compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+			d-cache-size = <0x8000>;
+			i-cache-size = <0x8000>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			qcom,freq-domain = <&cpufreq_hw 0 4>;
+			next-level-cache = <&L2_0>;
+			qcom,lmh-dcvs = <&lmh_dcvs0>;
+
+			L1_I_1: l1-icache {
+			      compatible = "arm,arch-cache";
+			};
+
+			L1_D_1: l1-dcache {
+			      compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+			d-cache-size = <0x8000>;
+			i-cache-size = <0x8000>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			qcom,freq-domain = <&cpufreq_hw 0 4>;
+			next-level-cache = <&L2_0>;
+			qcom,lmh-dcvs = <&lmh_dcvs0>;
+
+			L1_I_2: l1-icache {
+			      compatible = "arm,arch-cache";
+			};
+
+			L1_D_2: l1-dcache {
+			      compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+			d-cache-size = <0x8000>;
+			i-cache-size = <0x8000>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			qcom,freq-domain = <&cpufreq_hw 0 4>;
+			next-level-cache = <&L2_0>;
+			qcom,lmh-dcvs = <&lmh_dcvs0>;
+
+			L1_I_3: l1-icache {
+			      compatible = "arm,arch-cache";
+			};
+
+			L1_D_3: l1-dcache {
+			      compatible = "arm,arch-cache";
+			};
+
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+
+				core3 {
+					cpu = <&CPU3>;
+				};
+			};
+		};
+	};
+
+	soc: soc { };
+
+	chosen {
+		bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		oda_region: oda_region@45700000 {
+			no-map;
+			reg = <0x0 0x45700000 0x0 0x300000>;
+		};
+
+		deepsleep_region: deepsleep_region@45A00000 {
+			no-map;
+			reg = <0x0 0x45A00000 0x0 0x100000>;
+		};
+
+		hyp_region: hyp_region@45B00000 {
+			no-map;
+			reg = <0x0 0x45B00000 0x0 0x300000>;
+		};
+
+		xbl_aop_mem: xbl_aop_mem@45e00000 {
+			no-map;
+			reg = <0x0 0x45e00000 0x0 0x11B000>;
+		};
+
+		sec_apps_mem: sec_apps_region@45fff000 {
+			no-map;
+			reg = <0x0 0x45fff000 0x0 0x1000>;
+		};
+
+		smem_region: smem@46000000 {
+			no-map;
+			reg = <0x0 0x46000000 0x0 0x200000>;
+		};
+
+		wlan_msa_mem: wlan_msa_region@46200000 {
+			no-map;
+			reg = <0x0 0x46200000 0x0 0x100000>;
+		};
+
+		pil_modem_mem: modem_region@4ab00000 {
+			no-map;
+			reg = <0x0 0x4ab00000 0x0 0x5E00000>;
+		};
+
+		pil_video_mem: pil_video_region@50900000 {
+			no-map;
+			reg = <0x0 0x50900000 0x0 0x500000>;
+		};
+
+		pil_adsp_mem: adsp_regions@50E00000 {
+			no-map;
+			reg = <0x0 0x50E00000 0x0 0x1900000>;
+		};
+
+		pil_ipa_fw_mem: ips_fw_region@52700000 {
+			no-map;
+			reg = <0x0 0x52700000 0x0 0x10000>;
+		};
+
+		pil_ipa_gsi_mem: ipa_gsi_region@52710000 {
+			no-map;
+			reg = <0x0 0x52710000 0x0 0x5000>;
+		};
+
+		pil_gpu_mem: gpu_region@52715000 {
+			no-map;
+			reg = <0x0 0x52715000 0x0 0x2000>;
+		};
+
+		stats_region: stats_region@60000000 {
+			no-map;
+			reg = <0x0 0x60000000 0x0 0x100000>;
+		};
+
+		removed_region: removed_region@60100000 {
+			no-map;
+			reg = <0x0 0x60100000 0x0 0x1E00000>;
+		};
+
+		dump_mem: mem_dump_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			size = <0 0x800000>;
+		};
+
+		user_contig_mem: user_contig_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x1000000>;
+		};
+
+		qseecom_mem: qseecom_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x1400000>;
+		};
+
+		qseecom_ta_mem: qseecom_ta_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x1000000>;
+		};
+
+		secure_display_memory: secure_display_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0 0x00000000 0 0xffffffff>;
+			reusable;
+			alignment = <0 0x400000>;
+			size = <0 0x5c00000>;
+			status = "disabled";
+		};
+
+		splash_memory: splash_region@5c000000 {
+			reg = <0x0 0x5c000000 0x0 0x00f00000>;
+			label = "cont_splash_region";
+		};
+
+		dfps_data_memory: dfps_data_region@5cf00000 {
+			reg = <0x0 0x5cf00000 0x0 0x0100000>;
+			label = "dfps_data_region";
+		};
+
+		adsp_mem: adsp_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0 0x00000000 0 0xffffffff>;
+			reusable;
+			alignment = <0 0x400000>;
+			size = <0 0x800000>;
+		};
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x2000000>;
+			linux,cma-default;
+		};
+	};
+};
+
+&firmware {
+	scm {
+		compatible = "qcom,scm";
+		qcom,dload-mode = <&tcsr 0x13000>;
+	};
+
+	android {
+		compatible = "android,firmware";
+		vbmeta {
+			compatible="android,vbmeta";
+			parts = "vbmeta,boot,system,vendor,dtbo,recovery";
+		};
+
+		fstab {
+			compatible = "android,fstab";
+			vendor {
+				compatible = "android,vendor";
+				dev =
+		"/dev/block/platform/soc/4744000.sdhci/by-name/vendor";
+				type = "ext4";
+				mnt_flags = "ro,barrier=1,discard";
+				fsmgr_flags = "wait,avb";
+				status = "ok";
+			};
+
+			system {
+				compatible = "android,system";
+				dev =
+		"/dev/block/platform/soc/4744000.sdhci/by-name/system";
+				type = "ext4";
+				mnt_flags = "ro,barrier=1,discard";
+				fsmgr_flags = "wait,avb";
+				status = "ok";
+			};
+		};
+	};
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0 0 0 0xffffffff>;
+	#gpio-cells = <2>;
+	compatible = "simple-bus";
+
+	intc: interrupt-controller@f200000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		#redistributor-regions = <1>;
+		redistributor-stride = <0x0 0x20000>;
+		reg = <0xf200000 0x10000>,     /* GICD */
+		      <0xf300000 0x100000>;    /* GICR * 8 */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <19200000>;
+	};
+
+	memtimer: timer@f120000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		compatible = "arm,armv7-timer-mem";
+		reg = <0x0f120000 0x1000>;
+		clock-frequency = <19200000>;
+
+		frame@f121000 {
+			frame-number = <0>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x0f121000 0x1000>,
+			      <0x0f122000 0x1000>;
+		};
+
+		frame@f123000 {
+			frame-number = <1>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0xf123000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@f124000 {
+			frame-number = <2>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0xf124000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@f125000 {
+			frame-number = <3>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0xf125000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@f126000 {
+			frame-number = <4>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0xf126000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@f127000 {
+			frame-number = <5>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0xf127000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@f128000 {
+			frame-number = <6>;
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0xf128000 0x1000>;
+			status = "disabled";
+		};
+	};
+
+	cpu_pmu: cpu-pmu {
+		compatible = "arm,armv8-pmuv3";
+		qcom,irq-is-percpu;
+		interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	qcom,msm-imem@c125000 {
+		compatible = "qcom,msm-imem";
+		reg = <0xc125000 0x1000>;
+		ranges = <0x0 0xc125000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mem_dump_table@10 {
+			compatible = "qcom,msm-imem-mem_dump_table";
+			reg = <0x10 0x8>;
+		};
+
+		restart_reason@65c {
+			compatible = "qcom,msm-imem-restart_reason";
+			reg = <0x65c 0x4>;
+		};
+
+		dload_type@1c {
+			compatible = "qcom,msm-imem-dload-type";
+			reg = <0x1c 0x4>;
+		};
+
+		boot_stats@6b0 {
+			compatible = "qcom,msm-imem-boot_stats";
+			reg = <0x6b0 0x20>;
+		};
+
+		kaslr_offset@6d0 {
+			compatible = "qcom,msm-imem-kaslr_offset";
+			reg = <0x6d0 0xc>;
+		};
+
+		pil@94c {
+			compatible = "qcom,msm-imem-pil";
+			reg = <0x94c 0xc8>;
+		};
+
+		pil@6dc {
+			compatible = "qcom,msm-imem-pil-disable-timeout";
+			reg = <0x6dc 0x4>;
+		};
+
+		diag_dload@c8 {
+			compatible = "qcom,msm-imem-diag-dload";
+			reg = <0xc8 0xc8>;
+		};
+	};
+
+	dload_mode {
+		compatible = "qcom,dload-mode";
+	};
+
+	qcom,mpm2-slepp-counter@4403000 {
+		compatible = "qcom,mpm2-sleep-counter";
+		reg = <0x4403000 0x1000>;
+		clock-frequency = <32768>;
+	};
+
+	qcom,msm-rtb {
+		compatible = "qcom,msm-rtb";
+		qcom,rtb-size = <0x100000>;
+	};
+
+	qcom,rmtfs_sharedmem@0 {
+		compatible = "qcom,sharedmem-uio";
+		reg = <0x0 0x280000>;
+		reg-names = "rmtfs";
+		qcom,client-id = <0x00000001>;
+		qcom,guard-memory;
+		qcom,vm-nav-path;
+	};
+
+	qcom,chd_silver {
+		compatible = "qcom,core-hang-detect";
+		label = "silver";
+		qcom,threshold-arr = <0x0f1880b0 0x0f1980b0
+				      0x0f1a80b0 0x0f1b80b0>;
+		qcom,config-arr = <0x0f1880b8 0x0f1980b8
+				   0x0f1a80b8 0x0f1b80b8>;
+	};
+
+	qcom_qseecom: qseecom@61800000 {
+		compatible = "qcom,qseecom";
+		reg = <0x61800000 0x2100000>;
+		reg-names = "secapp-region";
+		memory-region = <&qseecom_mem>;
+		qcom,hlos-num-ce-hw-instances = <1>;
+		qcom,hlos-ce-hw-instance = <0>;
+		qcom,qsee-ce-hw-instance = <0>;
+		qcom,disk-encrypt-pipe-pair = <2>;
+		qcom,support-fde;
+		qcom,fde-key-size;
+		qcom,appsbl-qseecom-support;
+		qcom,commonlib64-loaded-by-uefi;
+		interconnect-names = "data_path";
+		interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>;
+		clock-names =
+			"core_clk_src", "core_clk",
+			"iface_clk", "bus_clk";
+		clocks =
+			<&rpmcc RPM_SMD_CE1_CLK>,
+			<&rpmcc RPM_SMD_CE1_CLK>,
+			<&rpmcc RPM_SMD_CE1_CLK>,
+			<&rpmcc RPM_SMD_CE1_CLK>;
+		qcom,ce-opp-freq = <192000000>;
+		qcom,qsee-reentrancy-support = <2>;
+	};
+
+	qtee_shmbridge {
+		compatible = "qcom,tee-shared-memory-bridge";
+	};
+
+	qcom_smcinvoke: smcinvoke@61800000 {
+		compatible = "qcom,smcinvoke";
+	};
+
+	qcom_tzlog: tz-log@c125720 {
+		compatible = "qcom,tz-log";
+		reg = <0xc125720 0x3000>;
+		qcom,hyplog-enabled;
+		hyplog-address-offset = <0x410>;
+		hyplog-size-offset = <0x414>;
+	};
+
+	qcom_rng: qrng@4453000 {
+		compatible = "qcom,msm-rng";
+		reg = <0x4453000 0x1000>;
+		qcom,no-qrng-config;
+		interconnect-names = "data_path";
+		interconnects = <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_HWKM>;
+		clock-names = "km_clk_src";
+		clocks = <&rpmcc RPM_SMD_HWKM_CLK>;
+	};
+
+	qcom_cedev: qcedev@1b20000 {
+		compatible = "qcom,qcedev";
+		reg = <0x1b20000 0x20000>,
+			<0x1b04000 0x24000>;
+		reg-names = "crypto-base","crypto-bam-base";
+		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,bam-pipe-pair = <3>;
+		qcom,ce-hw-instance = <0>;
+		qcom,ce-device = <0>;
+		qcom,ce-hw-shared;
+		qcom,bam-ee = <0>;
+		clock-names =
+			"core_clk_src", "core_clk",
+			"iface_clk", "bus_clk";
+		clocks =
+			<&rpmcc RPM_SMD_CE1_CLK>,
+			<&rpmcc RPM_SMD_CE1_CLK>,
+			<&rpmcc RPM_SMD_CE1_CLK>,
+			<&rpmcc RPM_SMD_CE1_CLK>;
+		qcom,ce-opp-freq = <192000000>;
+		qcom,smmu-s1-enable;
+		interconnect-names = "data_path";
+		interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>;
+		iommus = <&apps_smmu 0x0086 0x0011>,
+			 <&apps_smmu 0x0096 0x0011>;
+		qcom,iommu-dma = "atomic";
+
+		qcom_cedev_ns_cb {
+			compatible = "qcom,qcedev,context-bank";
+			label = "ns_context";
+			iommus = <&apps_smmu 0x92 0>,
+				<&apps_smmu 0x98 0x1>,
+				<&apps_smmu 0x9F 0>;
+			qcom,iommu-dma-addr-pool = <0x70000000 0X10000000>;
+		};
+
+		qcom_cedev_s_cb {
+			compatible = "qcom,qcedev,context-bank";
+			label = "secure_context";
+			iommus = <&apps_smmu 0x93 0>,
+				<&apps_smmu 0x9C 0x1>,
+				<&apps_smmu 0x9E 0>;
+			qcom,iommu-dma-addr-pool = <0x70000000 0X10000000>;
+			qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
+			qcom,secure-context-bank;
+		};
+	};
+
+	qcom_crypto: qcrypto@1b20000 {
+		compatible = "qcom,qcrypto";
+		reg = <0x1b20000 0x20000>,
+			<0x1b04000 0x24000>;
+		reg-names = "crypto-base","crypto-bam-base";
+		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,bam-pipe-pair = <2>;
+		qcom,ce-hw-instance = <0>;
+		qcom,ce-device = <0>;
+		qcom,bam-ee = <0>;
+		qcom,ce-hw-shared;
+		qcom,clk-mgmt-sus-res;
+		clock-names =
+			"core_clk_src", "core_clk",
+			"iface_clk", "bus_clk";
+		clocks =
+			<&rpmcc RPM_SMD_CE1_CLK>,
+			<&rpmcc RPM_SMD_CE1_CLK>,
+			<&rpmcc RPM_SMD_CE1_CLK>,
+			<&rpmcc RPM_SMD_CE1_CLK>;
+		qcom,use-sw-aes-cbc-ecb-ctr-algo;
+		qcom,use-sw-aes-xts-algo;
+		qcom,use-sw-aes-ccm-algo;
+		qcom,use-sw-ahash-algo;
+		qcom,use-sw-aead-algo;
+		qcom,use-sw-hmac-algo;
+		qcom,smmu-s1-enable;
+		interconnect-names = "data_path";
+		interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>;
+		iommus = <&apps_smmu 0x0084 0x0011>,
+			<&apps_smmu 0x0094 0x0011>;
+		qcom,iommu-dma = "atomic";
+	};
+
+	wdog: qcom,wdt@f017000 {
+		compatible = "qcom,msm-watchdog";
+		reg = <0xf017000 0x1000>;
+		reg-names = "wdt-base";
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,bark-time = <11000>;
+		qcom,pet-time = <9360>;
+		qcom,ipi-ping;
+		qcom,wakeup-enable;
+	};
+
+	eud: qcom,msm-eud@1610000 {
+		compatible = "qcom,msm-eud";
+		interrupt-names = "eud_irq";
+		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x1610000 0x2000>,
+		      <0x1612000 0x1000>,
+		      <0x3E5018 0x4>;
+		reg-names = "eud_base", "eud_mode_mgr2",
+				"eud_tcsr_check_reg";
+		qcom,secure-eud-en;
+		qcom,eud-tcsr-check-enable;
+		qcom,eud-clock-vote-req;
+		clocks = <&gcc GCC_AHB2PHY_USB_CLK>;
+		clock-names = "eud_ahb2phy_clk";
+		status = "ok";
+	};
+
+	qcom,sps {
+		compatible = "qcom,msm-sps-4k";
+		qcom,pipe-attr-ee;
+	};
+
+	qfprom: qfprom@1b40000 {
+		compatible = "qcom,qfprom";
+		reg = <0x1b40000 0x7000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		read-only;
+		ranges;
+		adsp_variant: adsp_variant@6011 {
+			reg = <0x6011 0x1>;
+			bits = <3 1>;
+		};
+	};
+
+	mem_dump {
+		compatible = "qcom,mem-dump";
+
+		c0_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x0>;
+		};
+
+		c1_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x1>;
+		};
+
+		c2_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x2>;
+		};
+
+		c3_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x3>;
+		};
+
+		l1_icache0 {
+			qcom,dump-size = <0x9040>;
+			qcom,dump-id = <0x60>;
+		};
+
+		l1_icache1 {
+			qcom,dump-size = <0x9040>;
+			qcom,dump-id = <0x61>;
+		};
+
+		l1_icache2 {
+			qcom,dump-size = <0x9040>;
+			qcom,dump-id = <0x62>;
+		};
+
+		l1_icache3 {
+			qcom,dump-size = <0x9040>;
+			qcom,dump-id = <0x63>;
+		};
+
+		l1_dcache0 {
+			qcom,dump-size = <0x9040>;
+			qcom,dump-id = <0x80>;
+		};
+
+		l1_dcache1 {
+			qcom,dump-size = <0x9040>;
+			qcom,dump-id = <0x81>;
+		};
+
+		l1_dcache2 {
+			qcom,dump-size = <0x9040>;
+			qcom,dump-id = <0x82>;
+		};
+
+		l1_dcache3 {
+			qcom,dump-size = <0x9040>;
+			qcom,dump-id = <0x83>;
+		};
+
+		l2_tlb0 {
+			qcom,dump-size = <0x2000>;
+			qcom,dump-id = <0x120>;
+		};
+
+		l2_tlb1 {
+			qcom,dump-size = <0x2000>;
+			qcom,dump-id = <0x121>;
+		};
+
+		l2_tlb2 {
+			qcom,dump-size = <0x2000>;
+			qcom,dump-id = <0x122>;
+		};
+
+		l2_tlb3 {
+			qcom,dump-size = <0x2000>;
+			qcom,dump-id = <0x123>;
+		};
+
+		pmic {
+			qcom,dump-size = <0x200000>;
+			qcom,dump-id = <0xe4>;
+		};
+
+		tmc_etf {
+			qcom,dump-size = <0x8000>;
+			qcom,dump-id = <0xf0>;
+		};
+
+		etr_reg {
+			qcom,dump-size = <0x1000>;
+			qcom,dump-id = <0x100>;
+		};
+
+		etf_reg {
+			qcom,dump-size = <0x1000>;
+			qcom,dump-id = <0x101>;
+		};
+	};
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			clock-frequency = <38400000>;
+			clock-output-names = "xo_board";
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			clock-output-names = "sleep_clk";
+			#clock-cells = <0>;
+		};
+	};
+
+	rpmcc: qcom,rpmcc {
+		compatible = "qcom,rpmcc-monaco";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	gcc: clock-controller@1410000 {
+		compatible = "qcom,monaco-gcc", "syscon";
+		reg = <0x1400000 0x1e0000>;
+		reg-names = "cc_base";
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		vdd_mx-supply = <&VDD_MXA_LEVEL>;
+		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+			 <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
+			 <&sleep_clk>;
+		clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	dispcc: clock-controller@5f00000 {
+		compatible = "qcom,monaco-dispcc", "syscon";
+		reg = <0x05f00000 0x20000>;
+		reg-names = "cc_base";
+		clock-names = "bi_tcxo", "bi_tcxo_ao", "gpll0_out_main",
+			"sleep_clk";
+		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
+			 <&gcc GPLL0>, <&sleep_clk>;
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	gpucc: clock-controller@5990000 {
+		compatible = "qcom,monaco-gpucc", "syscon";
+		reg = <0x5990000 0x9000>;
+		reg-names = "cc_base";
+		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+			<&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&gcc GPLL0>,
+			 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
+		clock-names = "bi_tcxo", "bi_tcxo_ao", "gpll0_out_main",
+			"gcc_gpu_snoc_dvm_gfx_clk";
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	mccc_debug: syscon@447d200 {
+		compatible = "syscon";
+		reg = <0x0447d200 0x100>;
+	};
+
+	apsscc_debug: syscon@f11101c {
+		compatible = "syscon";
+		reg = <0xf11101c 0x4>;
+	};
+
+	debugcc: clock-controller@0 {
+		compatible = "qcom,monaco-debugcc";
+		qcom,gcc = <&gcc>;
+		qcom,dispcc = <&dispcc>;
+		qcom,gpucc = <&gpucc>;
+		qcom,mccc = <&mccc_debug>;
+		qcom,apsscc = <&apsscc_debug>;
+		clock-names = "xo_clk_src";
+		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+		#clock-cells = <1>;
+	};
+
+	cpufreq_hw: qcom,cpufreq-hw {
+		compatible = "qcom,cpufreq-hw";
+		reg = <0xf521000 0x1400>;
+		reg-names = "freq-domain0";
+		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+		clock-names = "xo", "alternate";
+		qcom,no-accumulative-counter;
+		qcom,max-lut-entries = <12>;
+		#freq-domain-cells = <2>;
+	};
+
+	qcom,cpufreq-hw-debug@f521000 {
+		compatible = "qcom,cpufreq-hw-debug";
+		reg = <0xf521000 0x1400>;
+		reg-names = "domain-top";
+		qcom,freq-hw-domain = <&cpufreq_hw 0>;
+	};
+
+	spmi_bus: qcom,spmi@1c40000 {
+		compatible = "qcom,spmi-pmic-arb";
+		reg = <0x1c40000 0x1100>,
+			<0x1e00000 0x2000000>,
+			<0x3e00000 0x100000>,
+			<0x3f00000 0xa0000>,
+			<0x1c0a000 0x26000>;
+		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+		interrupt-names = "periph_irq";
+		interrupts-extended = <&wakegic 86 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,ee = <0>;
+		qcom,mid = <0>;
+		qcom,channel = <0>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		interrupt-controller;
+		#interrupt-cells = <4>;
+		cell-index = <0>;
+	};
+
+	thermal_zones: thermal-zones {};
+
+	tcsr_mutex_block: syscon@00340000 {
+		compatible = "syscon";
+		reg = <0x340000 0x20000>;
+	};
+
+	tcsr_mutex: hwlock {
+		compatible = "qcom,tcsr-mutex";
+		syscon = <&tcsr_mutex_block 0 0x1000>;
+		#hwlock-cells = <1>;
+	};
+
+	tcsr: syscon@03c0000 {
+		compatible = "syscon";
+		reg = <0x03c0000 0x30000>;
+	};
+
+	smem: qcom,smem {
+		compatible = "qcom,smem";
+		memory-region = <&smem_region>;
+		hwlocks = <&tcsr_mutex 3>;
+	};
+
+	rpm_msg_ram: memory@045f0000 {
+			compatible = "qcom,rpm-msg-ram";
+			reg = <0x45f0000 0x4000>;
+	};
+
+	apcs_glb: mailbox@0f111000 {
+		compatible = "qcom,monaco-apcs-hmss-global";
+		reg = <0xF111000 0x1000>;
+
+		#mbox-cells = <1>;
+	};
+
+	jtag_mm0: jtagmm@9040000 {
+		compatible = "qcom,jtagv8-mm";
+		reg = <0x9040000 0x1000>;
+		reg-names = "etm-base";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "core_clk";
+
+		qcom,coresight-jtagmm-cpu = <&CPU0>;
+	};
+
+	jtag_mm1: jtagmm@9140000 {
+		compatible = "qcom,jtagv8-mm";
+		reg = <0x9140000 0x1000>;
+		reg-names = "etm-base";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "core_clk";
+
+		qcom,coresight-jtagmm-cpu = <&CPU1>;
+	};
+
+	jtag_mm2: jtagmm@9240000 {
+		compatible = "qcom,jtagv8-mm";
+		reg = <0x9240000 0x1000>;
+		reg-names = "etm-base";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "core_clk";
+
+		qcom,coresight-jtagmm-cpu = <&CPU2>;
+	};
+
+	jtag_mm3: jtagmm@9340000 {
+		compatible = "qcom,jtagv8-mm";
+		reg = <0x9340000 0x1000>;
+		reg-names = "etm-base";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "core_clk";
+
+		qcom,coresight-jtagmm-cpu = <&CPU3>;
+	};
+
+	dcc: dcc_v2@16FF000 {
+		compatible = "qcom,dcc-v2";
+		reg = <0x16FF000 0x1000>,
+		      <0x1681000 0x2000>;
+
+		qcom,transaction_timeout = <0>;
+
+		reg-names = "dcc-base", "dcc-ram-base";
+		dcc-ram-offset = <0x1000>;
+
+		per-ll-reg-cnt = <7>;
+		ll-reg-offsets = <0x02C 0x034 0x038 0x03C 0x044 0x048 0x030 0x0AC
+			0x0B4 0x0B8 0x0BC 0x0C4 0x0C8 0x0B0 0x12C 0x134
+			0x138 0x13C 0x144 0x148 0x130 0x1AC 0x1B4 0x1B8
+			0x1BC 0x1C4 0x1C8 0x1B0>;
+
+	};
+
+	clk_virt: interconnect {
+		compatible = "qcom,monaco-clk_virt";
+		#interconnect-cells = <1>;
+		clock-names = "bus", "bus_a";
+		clocks = <&rpmcc RPM_SMD_QUP_CLK>,
+			<&rpmcc RPM_SMD_QUP_A_CLK>;
+	};
+
+	mmnrt_virt: interconnect@0 {
+		compatible = "qcom,monaco-mmnrt_virt";
+		#interconnect-cells = <1>;
+		qcom,util-factor = <142>;
+		qcom,keepalive;
+		clock-names = "bus", "bus_a";
+		clocks = <&rpmcc RPM_SMD_MMNRT_CLK>,
+			<&rpmcc RPM_SMD_MMNRT_A_CLK>;
+	};
+
+	mmrt_virt: interconnect@1 {
+		compatible = "qcom,monaco-mmrt_virt";
+		#interconnect-cells = <1>;
+		qcom,util-factor = <142>;
+		qcom,keepalive;
+		clock-names = "bus", "bus_a";
+		clocks = <&rpmcc RPM_SMD_MMRT_CLK>,
+			<&rpmcc RPM_SMD_MMRT_A_CLK>;
+	};
+
+	system_noc: interconnect@1880000 {
+		reg = <0x01880000 0x5e200>;
+		compatible = "qcom,monaco-system_noc";
+		#interconnect-cells = <1>;
+		qcom,keepalive;
+		clock-names = "bus", "bus_a";
+		clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
+			<&rpmcc RPM_SMD_SNOC_A_CLK>,
+			<&rpmcc RPM_SMD_IPA_CLK>,
+			<&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
+			<&gcc GCC_SYS_NOC_USB2_PRIM_AXI_CLK>;
+	};
+
+	config_noc: interconnect@1900000 {
+		reg = <0x01900000 0x1000>;
+		compatible = "qcom,monaco-config_noc";
+		#interconnect-cells = <1>;
+		qcom,keepalive;
+		clock-names = "bus", "bus_a";
+		clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
+			<&rpmcc RPM_SMD_CNOC_A_CLK>;
+	};
+
+	bimc: interconnect@4480000 {
+		reg = <0x04480000 0x80000>;
+		compatible = "qcom,monaco-bimc";
+		#interconnect-cells = <1>;
+		qcom,util-factor = <151>;
+		qcom,keepalive;
+		clock-names = "bus", "bus_a";
+		clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
+			<&rpmcc RPM_SMD_BIMC_A_CLK>;
+	};
+
+	rpm_bus: qcom,rpm-smd {
+		compatible = "qcom,rpm-smd";
+		rpm-channel-name = "rpm_requests";
+		interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
+		rpm-channel-type = <15>; /* SMD_APPS_RPM */
+	};
+
+	sdhc_1: sdhci@4744000 {
+		compatible = "qcom,sdhci-msm-v5";
+		reg = <0x04744000 0x1000>, <0x04745000 0x1000>,
+		      <0x04748000 0x8000>, <0x04750000 0x9000>;
+		reg-names = "hc_mem", "cqhci_mem", "cqhci_ice",
+			    "cqhci_ice_hwkm";
+
+		iommus = <&apps_smmu 0xC0 0x0>;
+		qcom,iommu-dma = "bypass";
+
+		interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hc_irq", "pwr_irq";
+
+		clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+			<&gcc GCC_SDCC1_AHB_CLK>,
+			<&gcc GCC_SDCC1_ICE_CORE_CLK>;
+		clock-names = "core", "iface", "ice_core";
+
+		qcom,ice-clk-rates = <300000000 100000000>;
+
+		interconnects = <&system_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>,
+			<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_1>;
+		interconnect-names = "sdhc-ddr","cpu-sdhc";
+		qcom,msm-bus,name = "sdhc1";
+		qcom,msm-bus,num-cases = <8>;
+		qcom,msm-bus,num-paths = <2>;
+		qcom,msm-bus,vectors-KBps =
+			/* No vote */
+			<0 0>, <0 0>,
+			/* 400 KB/s*/
+			<523 800>,<800 800>,
+			/* 25 MB/s */
+			<12800 125000>,<25000 66660>,
+			/* 50 MB/s */
+			<25600 125000>,<32500 66660>,
+			/* 100 MB/s */
+			<51200 125000>,<32500 66660>,
+			/* 200 MB/s */
+			<102400 400000>,<100000 150000>,
+			/* 400 MB/s */
+			<102400 400000>,<100000 150000>,
+			/* Max. bandwidth */
+			<669281 2048000>,<669281 2048000>;
+		qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000
+			100750000 200000000 400000000 4294967295>;
+
+		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+		qcom,dll-hsr-list = <0x000F642C 0x0 0x01 0x2c010800 0x80040868>;
+
+		qcom,devfreq,freq-table = <50000000 200000000>;
+		qcom,scaling-lower-bus-speed-mode = "DDR52";
+		qcom,restore-after-cx-collapse;
+
+		mmc-ddr-1_8v;
+		mmc-hs200-1_8v;
+		mmc-hs400-1_8v;
+		mmc-hs400-enhanced-strobe;
+
+		no-sd;
+		no-sdio;
+
+		bus-width = <8>;
+		non-removable;
+		supports-cqe;
+
+		cap-mmc-hw-reset;
+
+		/* Add dt entry for gcc hw reset */
+		resets = <&gcc GCC_SDCC1_BCR>;
+		reset-names = "core_reset";
+
+		status = "disabled";
+
+		qos0 {
+			mask = <0x0f>;
+			vote = <43>;
+		};
+	};
+
+	wakegic: wake-gic {
+		compatible = "qcom,mpm-gic-monaco", "qcom,mpm";
+		interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+		reg = <0x45f01b8 0x1000>,
+			<0xf111008 0x4>;
+		reg-names = "vmpm", "ipc";
+		qcom,num-mpm-irqs = <96>;
+		interrupt-controller;
+		interrupt-parent = <&intc>;
+		#interrupt-cells = <2>;
+	};
+
+	qcom-secure-buffer {
+		compatible = "qcom,secure-buffer";
+	};
+
+	qcom,msm_gsi {
+		compatible = "qcom,msm_gsi";
+	};
+
+	qcom,rmnet-ipa {
+		compatible = "qcom,rmnet-ipa3";
+		qcom,rmnet-ipa-ssr;
+		qcom,ipa-platform-type-msm;
+		qcom,ipa-advertise-sg-support;
+		qcom,ipa-napi-enable;
+	};
+
+	qcom,power-state {
+		compatible = "qcom,power-state";
+	};
+
+	msm_gpu: qcom,kgsl-3d0@5900000 { };
+};
+
+#include "pm5100.dtsi"
+#include "pm5100-rpm-regulator.dtsi"
+#include "pm8010-rpm-regulator.dtsi"
+#include "monaco-regulators.dtsi"
+#include "monaco-pmic.dtsi"
+#include "monaco-pinctrl.dtsi"
+#include "monaco-coresight.dtsi"
+#include "msm-arm-smmu-monaco.dtsi"
+#include "monaco-dma-heaps.dtsi"
+#include "monaco-gdsc.dtsi"
+#include "monaco-usb.dtsi"
+#include "monaco-thermal.dtsi"
+
+&gcc_camss_top_gdsc {
+	parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&gcc_usb20_prim_gdsc {
+	parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&gcc_vcodec0_gdsc {
+	qcom,support-hw-trigger;
+	parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&gcc_venus_gdsc {
+	parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc {
+	parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc {
+	parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&mdss_core_gdsc {
+	parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&gpu_cx_gdsc {
+	parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&gpu_gx_gdsc {
+	parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&usb0 {
+	extcon = <&pm5100_charger>, <&eud>;
+
+	#io-channel-cells = <1>;
+	io-channels= <&pm5100_charger PSY_IIO_USB_REAL_TYPE>;
+	io-channel-names = "chg_type";
+};
diff --git a/qcom/monacop.dts b/qcom/monacop.dts
new file mode 100644
index 00000000..1f328106
--- /dev/null
+++ b/qcom/monacop.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "monacop.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. MonacoP SoC";
+	compatible = "qcom,monacop";
+	qcom,board-id = <0 0>;
+};
diff --git a/qcom/monacop.dtsi b/qcom/monacop.dtsi
new file mode 100644
index 00000000..c48c296f
--- /dev/null
+++ b/qcom/monacop.dtsi
@@ -0,0 +1,13 @@
+#include "monaco.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. MonacoP";
+	compatible = "qcom,monacop";
+	qcom,msm-id = <517 0x10000>;
+};
+
+&soc {
+	qcom,rmnet-ipa {
+		status = "disabled";
+	};
+};
diff --git a/qcom/msm-arm-smmu-monaco.dtsi b/qcom/msm-arm-smmu-monaco.dtsi
new file mode 100644
index 00000000..62381dae
--- /dev/null
+++ b/qcom/msm-arm-smmu-monaco.dtsi
@@ -0,0 +1,216 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interconnect/qcom,monaco.h>
+
+&soc {
+	kgsl_smmu: kgsl-smmu@0x59a0000 {
+		status = "okay";
+		compatible = "qcom,qsmmu-v500";
+		reg = <0x59a0000 0x10000>,
+			<0x59da000 0x20>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,skip-init;
+		qcom,no-dynamic-asid;
+		qcom,use-3-lvl-tables;
+		#global-interrupts = <1>;
+		qcom,regulator-names = "vdd";
+		vdd-supply = <&gpu_cx_gdsc>;
+		clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+			<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+			<&gpucc GPU_CC_AHB_CLK>,
+			<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+			clock-names = "gcc_gpu_memnoc_gfx",
+				"gcc_gpu_snoc_dvm_gfx",
+				"gpu_cc_ahb",
+				"gpu_cc_hlos1_vote_gpu_smmu_clk";
+		#size-cells = <1>;
+		ranges;
+		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+			qcom,actlr =
+				/* ALL CBs of GFX: +15 deep PF */
+				<0x0 0x3ff 0x32B>;
+
+		gfx_0_tbu: gfx_0_tbu@0x59dd000 {
+				compatible = "qcom,qsmmuv500-tbu";
+				reg = <0x59dd000 0x1000>,
+					<0x59da200 0x8>;
+				reg-names = "base", "status-reg";
+				qcom,stream-id-range = <0x0 0x400>;
+				interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+
+	apps_smmu: apps-smmu@0xc600000 {
+				status = "okay";
+				compatible = "qcom,qsmmu-v500";
+				reg = <0xc600000 0x80000>,
+					<0xc7f2000 0x20>;
+				reg-names = "base", "tcu-base";
+				#iommu-cells = <2>;
+				qcom,skip-init;
+				qcom,use-3-lvl-tables;
+				#global-interrupts = <1>;
+				#size-cells = <1>;
+				#address-cells = <1>;
+				ranges;
+				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+				qcom,msm-bus,name = "apps_smmu";
+				qcom,msm-bus,num-cases = <2>;
+				qcom,msm-bus,active-only;
+				qcom,msm-bus,num-paths = <1>;
+				qcom,msm-bus,vectors-KBps =
+					<MASTER_AMPSS_M0 SLAVE_TCU 0 0>,
+					<MASTER_AMPSS_M0 SLAVE_TCU 0 1000>;
+
+				qcom,actlr =
+					/* For rt TBU +3 deep PF */
+					<0x400 0x3ff 0x103>,
+					/* For nrt TBU +3 deep PF */
+					<0x800 0x3ff 0x103>;
+
+				anoc_1_tbu: anoc_1_tbu@0xc7f5000 {
+					compatible = "qcom,qsmmuv500-tbu";
+					reg = <0xc7f5000 0x1000>,
+						<0xc7f2200 0x8>;
+					reg-names = "base", "status-reg";
+					qcom,stream-id-range = <0x0 0x400>;
+					interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+					qcom,msm-bus,name = "apps_smmu";
+					qcom,msm-bus,num-cases = <2>;
+					qcom,msm-bus,active-only;
+					qcom,msm-bus,num-paths = <2>;
+					qcom,msm-bus,vectors-KBps =
+						<MASTER_AMPSS_M0 SLAVE_TCU 0 0>,
+						<MASTER_AMPSS_M0 SLAVE_IMEM_CFG 0 0>,
+						<MASTER_AMPSS_M0 SLAVE_TCU 0 1000>,
+						<MASTER_AMPSS_M0 SLAVE_IMEM_CFG 0 1000>;
+				};
+
+				mm_rt_tbu: mm_rt_tbu@0xc7f9000 {
+					compatible = "qcom,qsmmuv500-tbu";
+					reg = <0xc7f9000 0x1000>,
+						<0xc7f2208 0x8>;
+					reg-names = "base", "status-reg";
+					qcom,stream-id-range = <0x400 0x400>;
+					interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+					qcom,msm-bus,name = "apps_smmu";
+					qcom,msm-bus,num-cases = <2>;
+					qcom,msm-bus,active-only;
+					qcom,msm-bus,num-paths = <2>;
+					qcom,msm-bus,vectors-KBps =
+						<MASTER_AMPSS_M0 SLAVE_TCU 0 0>,
+						<MASTER_MDP_PORT0 SLAVE_SNOC_BIMC_RT 0 0>,
+						<MASTER_AMPSS_M0 SLAVE_TCU 0 1000>,
+						<MASTER_MDP_PORT0 SLAVE_SNOC_BIMC_RT 0 1000>;
+				};
+
+				mm_nrt_tbu: mm_nrt_tbu@0xc7fd000 {
+					compatible = "qcom,qsmmuv500-tbu";
+					reg = <0xc7fd000 0x1000>,
+						<0xc7f2210 0x8>;
+					reg-names = "base", "status-reg";
+					qcom,stream-id-range = <0x800 0x400>;
+					interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+					qcom,msm-bus,name = "apps_smmu";
+					qcom,msm-bus,num-cases = <2>;
+					qcom,msm-bus,active-only;
+					qcom,msm-bus,num-paths = <2>;
+					qcom,msm-bus,vectors-KBps =
+						<MASTER_AMPSS_M0 SLAVE_TCU 0 0>,
+						<MASTER_CAMNOC_SF SLAVE_SNOC_BIMC_NRT 0 0>,
+						<MASTER_AMPSS_M0 SLAVE_TCU 0 1000>,
+						<MASTER_CAMNOC_SF SLAVE_SNOC_BIMC_NRT 0 1000>;
+				};
+
+	};
+
+	kgsl_iommu_test_device {
+			compatible = "iommu-debug-test";
+			iommus = <&kgsl_smmu 0x7 0x0>;
+	};
+
+	apps_iommu_test_device {
+			compatible = "iommu-debug-test";
+			iommus = <&apps_smmu 0x1E0 0x0>;
+	};
+
+	apps_iommu_coherent_test_device {
+			compatible = "iommu-debug-test";
+			qcom,iommu-dma = "disabled";
+			iommus = <&apps_smmu 0x1E1 0x0>;
+			dma-coherent;
+	};
+};
diff --git a/qcom/msm-rdbg-monaco.dtsi b/qcom/msm-rdbg-monaco.dtsi
new file mode 100644
index 00000000..758dda2c
--- /dev/null
+++ b/qcom/msm-rdbg-monaco.dtsi
@@ -0,0 +1,15 @@
+&soc {
+  /* smp2p information */
+	qcom,smp2p_interrupt_rdbg_2_out {
+		compatible = "qcom,smp2p-interrupt-rdbg-2-out";
+		qcom,smem-states = <&smp2p_rdbg2_out 0>;
+		qcom,smem-state-names = "rdbg-smp2p-out";
+	};
+
+	qcom,smp2p_interrupt_rdbg_2_in {
+		compatible = "qcom,smp2p-interrupt-rdbg-2-in";
+		interrupts-extended = <&smp2p_rdbg2_in 0 0>;
+		interrupt-names = "rdbg-smp2p-in";
+	};
+
+};
diff --git a/qcom/pm5100-rpm-regulator.dtsi b/qcom/pm5100-rpm-regulator.dtsi
new file mode 100644
index 00000000..e7349c3f
--- /dev/null
+++ b/qcom/pm5100-rpm-regulator.dtsi
@@ -0,0 +1,614 @@
+&rpm_bus {
+	rpm-regulator-smpa1 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "smpa";
+		qcom,resource-id = <1>;
+		qcom,regulator-type = <1>;
+		qcom,hpm-min-load = <100000>;
+		status = "disabled";
+
+		regulator-s1 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_s1";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-smpa2 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "smpa";
+		qcom,resource-id = <2>;
+		qcom,regulator-type = <1>;
+		qcom,hpm-min-load = <100000>;
+		status = "disabled";
+
+		regulator-s2 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_s2";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-smpa3 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "smpa";
+		qcom,resource-id = <3>;
+		qcom,regulator-type = <1>;
+		qcom,hpm-min-load = <100000>;
+		status = "disabled";
+
+		regulator-s3 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_s3";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-smpa4 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "smpa";
+		qcom,resource-id = <4>;
+		qcom,regulator-type = <1>;
+		qcom,hpm-min-load = <100000>;
+		status = "disabled";
+
+		regulator-s4 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_s4";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-smpa5 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "smpa";
+		qcom,resource-id = <5>;
+		qcom,regulator-type = <1>;
+		qcom,hpm-min-load = <100000>;
+		status = "disabled";
+
+		regulator-s5 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_s5";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa1 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <1>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l1 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l1";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa2 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <2>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l2 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l2";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa3 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <3>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l3 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l3";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa4 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <4>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l4 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l4";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa5 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <5>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l5 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l5";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa6 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <6>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l6 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l6";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa7 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <7>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l7 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l7";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa8 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <8>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l8 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l8";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa9 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <9>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l9 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l9";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa10 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <10>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l10 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l10";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa11 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <11>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l11 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l11";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa12 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <12>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l12 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l12";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa13 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <13>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <30000>;
+		status = "disabled";
+
+		regulator-l13 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l13";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa14 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <14>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l14 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l14";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa15 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <15>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l15 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l15";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa16 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <16>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l16 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l16";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa17 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <17>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l17 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l17";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa18 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <18>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l18 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l18";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa19 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <19>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l19 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l19";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa20 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <20>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l20 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l20";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa21 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <21>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l21 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l21";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa22 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <22>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l22 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l22";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa23 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <23>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l23 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l23";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa24 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <24>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l24 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l24";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa25 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <25>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l25 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l25";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa26 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <26>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l26 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l26";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa27 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <27>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l27 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l27";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa28 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <28>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l28 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l28";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldoa29 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldoa";
+		qcom,resource-id = <29>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l29 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_l29";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-boba {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "boba";
+		qcom,resource-id = <1>;
+		qcom,regulator-type = <4>;
+		qcom,regulator-hw-type = "pmic5-bob";
+		qcom,send-defaults;
+		status = "disabled";
+
+		regulator-pm5100a-bob {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100a_bob";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+
+		regulator-pm5100a-bob-ao {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100a_bob_ao";
+			qcom,set = <1>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-chg-boost {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "bsta";
+		qcom,resource-id = <1>;
+		qcom,regulator-type = <1>;
+		qcom,hpm-min-load = <100000>;
+		status = "disabled";
+
+		regulator-chg-boost {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm5100_chg_boost";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi
new file mode 100644
index 00000000..0f6d3f2f
--- /dev/null
+++ b/qcom/pm5100.dtsi
@@ -0,0 +1,659 @@
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/qcom,qpnp-power-on.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm5100.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/input/qcom,hv-haptics.h>
+
+&spmi_bus {
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pm5100@0 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pon_hlos@1300 {
+			compatible = "qcom,qpnp-power-on";
+			reg = <0x1300>;
+			interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>,
+				     <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "kpdpwr", "resin";
+
+			qcom,pon_1 {
+				qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
+				linux,code = <KEY_POWER>;
+			};
+
+			qcom,pon_2 {
+				qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
+				linux,code = <KEY_VOLUMEDOWN>;
+			};
+		};
+
+	pm5100_charger: qcom,qpnp-smblite {
+			compatible = "qcom,qpnp-pm5100-smblite";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#cooling-cells = <2>;
+
+			qcom,thermal-mitigation = <1500000 1400000
+				1300000 1200000 1100000 1000000 900000
+				800000 700000 600000 500000 400000
+				300000 200000 100000>;
+
+			qcom,chgr@2600 {
+				reg = <0x1000>;
+				interrupts =
+					<0x0 0x26 0x1 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x26 0x0 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x26 0x4 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x26 0x7 IRQ_TYPE_EDGE_RISING>;
+
+				interrupt-names = "chgr-error",
+						  "chg-state-change",
+						  "buck-oc",
+						  "vph-ov";
+			};
+
+			qcom,dcdc@2700 {
+				reg = <0x2700>;
+				interrupts =
+					<0x0 0x27 0x0 IRQ_TYPE_EDGE_BOTH>,
+					<0x0 0x27 0x4 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x27 0x6 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x27 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+				interrupt-names = "boost-mode-sw-en",
+						  "skip-mode",
+						  "input-current-limiting",
+						  "switcher-power-ok";
+			};
+
+			qcom,batif@2800 {
+				reg = <0x2800>;
+				interrupts =
+					<0x0 0x28 0x0 IRQ_TYPE_EDGE_BOTH>,
+					<0x0 0x28 0x2 IRQ_TYPE_EDGE_BOTH>,
+					<0x0 0x28 0x3 IRQ_TYPE_EDGE_BOTH>,
+					<0x0 0x28 0x4 IRQ_TYPE_EDGE_RISING>;
+
+				interrupt-names = "bat-temp",
+						  "bat-low",
+						  "bat-ov",
+						  "bsm-active";
+			};
+
+			qcom,usb@2900 {
+				reg = <0x2900>;
+				interrupts =
+					<0x0 0x29 0x0 IRQ_TYPE_EDGE_BOTH>,
+					<0x0 0x29 0x1 IRQ_TYPE_EDGE_BOTH>,
+					<0x0 0x29 0x2 IRQ_TYPE_EDGE_BOTH>,
+					<0x0 0x29 0x3 IRQ_TYPE_EDGE_BOTH>,
+					<0x0 0x29 0x4 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x29 0x6 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x29 0x7 IRQ_TYPE_EDGE_RISING>;
+
+				interrupt-names = "usbin-plugin",
+						  "usbin-collapse",
+						  "usbin-uv",
+						  "usbin-ov",
+						  "usbin-gtvt",
+						  "usbin-icl-change",
+						  "usbin-src-change";
+			};
+
+			qcom,misc@2c00 {
+				reg = <0x2c00>;
+				interrupts =
+					<0x0 0x2c 0x0 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x2c 0x1 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x2c 0x2 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x2c 0x3 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x2c 0x4 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x2c 0x5 IRQ_TYPE_EDGE_RISING>,
+					<0x0 0x2c 0x6 IRQ_TYPE_EDGE_BOTH>;
+
+				interrupt-names = "wdog-snarl",
+						  "wdog-bark",
+						  "aicl-fail",
+						  "aicl-done",
+						  "imp-trigger",
+						  "all-chnl-cond-done",
+						  "temp-change";
+			};
+		};
+
+		pm5100_tz: qcom,temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			io-channels = <&pm5100_adc PM5100_ADC5_GEN3_DIE_TEMP>;
+			io-channel-names = "thermal";
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm5100_adc: vadc@8000 {
+			compatible = "qcom,spmi-adc5-gen3";
+			reg = <0x8000>, <0x8300>;
+			reg-names = "adc5-gen3-base", "adc5-gen3-debug-base";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "adc";
+			#io-channel-cells = <1>;
+			status = "disabled";
+
+			pm5100_ref_gnd {
+				reg = <PM5100_ADC5_GEN3_OFFSET_REF>;
+				label = "pm5100_ref_gnd";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm5100_vref_1p25 {
+				reg = <PM5100_ADC5_GEN3_1P25VREF>;
+				label = "pm5100_vref_1p25";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm5100_die_temp {
+				reg = <PM5100_ADC5_GEN3_DIE_TEMP>;
+				label = "pm5100_die_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm5100_xo_therm {
+				reg = <PM5100_ADC5_GEN3_AMUX1_THM_100K_PU>;
+				label = "pm5100_xo_therm";
+				qcom,ratiometric;
+				qcom,hw-settle-time = <700>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm5100_usb_in_i_uv {
+				reg = <PM5100_ADC5_GEN3_USB_IN_I>;
+				label = "pm5100_usb_in_i_uv";
+				qcom,pre-scaling = <1 1>;
+				qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_GEN3_USB_IN_I>;
+			};
+
+			pm5100_chg_temp {
+				reg = <PM5100_ADC5_GEN3_CHG_TEMP>;
+				label = "pm5100_chg_temp";
+				qcom,pre-scaling = <1 1>;
+				qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_CHG_TEMP>;
+			};
+
+			pm5100_usb_in_v {
+				reg = <PM5100_ADC5_GEN3_USB_SNS_V_16>;
+				label = "pm5100_usb_in_v";
+				qcom,pre-scaling = <1 16>;
+			};
+
+			pm5100_boost_out_v {
+				reg = <PM5100_ADC5_GEN3_VIN_DIV16_MUX>;
+				label = "pm5100_boost_out_v";
+				qcom,pre-scaling = <1 6>;
+			};
+
+			pm5100_bat_therm {
+				reg = <PM5100_ADC5_GEN3_BATT_THM_100K_PU>;
+				label = "pm5100_bat_therm";
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+				qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_GEN3_BATT_THERM_100K>;
+			};
+
+			pm5100_bat_id {
+				reg = <PM5100_ADC5_GEN3_BAT_ID_100K_PU>;
+				label = "pm5100_bat_id";
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+				qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_GEN3_BATT_ID_100K>;
+			};
+
+			pm5100_vph_pwr {
+				reg = <PM5100_ADC5_GEN3_VPH_PWR>;
+				label = "pm5100_vph_pwr";
+				qcom,pre-scaling = <1 3>;
+			};
+
+			pm5100_vbat_sns {
+				reg = <PM5100_ADC5_GEN3_VBAT_SNS_QBG>;
+				label = "pm5100_vbat_sns";
+				qcom,pre-scaling = <1 3>;
+			};
+		};
+
+		pm5100_gpios: pinctrl@8800 {
+			compatible = "qcom,pm5100-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pm5100_rtc: rtc@6400 {
+			compatible = "qcom,pm5100-rtc";
+			reg = <0x6400>, <0x6500>;
+			reg-names = "rtc", "alarm";
+			interrupts = <0x0 0x65 0x1 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		pm5100_bcl: bcl@4700 {
+			compatible = "qcom,bcl-v5";
+			reg = <0x4700 0x100>;
+			interrupts = <0x0 0x47 0x0 IRQ_TYPE_NONE>,
+					<0x0 0x47 0x1 IRQ_TYPE_NONE>,
+					<0x0 0x47 0x2 IRQ_TYPE_NONE>;
+			interrupt-names = "bcl-lvl0",
+						"bcl-lvl1",
+						"bcl-lvl2";
+			qcom,pmic7-threshold;
+			qcom,ibat-ccm-hw-support;
+			#thermal-sensor-cells = <1>;
+		};
+
+		bcl_soc:bcl-soc {
+			compatible = "qcom,msm-bcl-soc";
+			#thermal-sensor-cells = <0>;
+		};
+
+		bcl_off: bcl-off@4700 {
+			compatible = "qcom,bcl-off";
+			reg =  <0x4700 0x100>;
+			#cooling-cells = <2>;
+		};
+
+		pm5100_sdam_2: sdam@7100 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7100>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			restart_reason: restart@48 {
+				reg = <0x48 0x1>;
+				bits = <1 7>;
+			};
+
+			charger_debug_mask: debug@94 {
+				reg = <0x94 0x1>;
+			};
+
+			qbg_debug_mask_low: debug@96 {
+				reg = <0x96 0x1>;
+			};
+
+			qbg_debug_mask_high: debug@97 {
+				reg = <0x97 0x1>;
+			};
+
+		};
+
+		pm5100_sdam_7: sdam@7600 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7600>;
+		};
+
+		pm5100_sdam_22: sdam@8500 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x8500>;
+
+			/* GPS demod state */
+			skip_esr_state: demod@46 {
+				reg = <0x46 0x1>;
+			};
+		};
+
+		pm5100_sdam_23: sdam@8600 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x8600>;
+		};
+
+		pm5100_qbg: qpnp,qbg@4f00 {
+			status = "disabled";
+			compatible = "qcom,qbg";
+			#address-cells = <1>;
+			reg = <0x4f00>;
+			interrupt-names = "qbg-sdam";
+			interrupts = <0x0 0x76 0x1 IRQ_TYPE_EDGE_RISING>;
+			qcom,num-data-sdams = <5>;
+			qcom,sdam-base = <0x7600>;
+			qcom,adc-cmn-wb-base = <0x3000>;
+			qcom,adc-cmn-base = <0x3900>;
+		};
+
+		pm5100_haptics: qcom,hv-haptics@f000 {
+			compatible = "qcom,pm5100-haptics";
+			reg = <0xf000>, <0xf100>;
+			interrupts = <0x0 0xf0 0x1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "fifo-empty";
+			qcom,vmax-mv = <2500>;
+			qcom,brake-mode = <BRAKE_CLOSE_LOOP>;
+			qcom,brake-pattern = /bits/ 8 <0xff 0x3f 0x1f>;
+			qcom,lra-period-us = <4167>;
+			qcom,drv-sig-shape = <WF_SINE>;
+			qcom,brake-sig-shape = <WF_SINE>;
+			status = "disabled";
+
+			effect_0 {
+				/* CLICK */
+				qcom,effect-id = <0>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x01f  S_PERIOD_T_LRA  0>,
+							<0x03f  S_PERIOD_T_LRA  0>,
+							<0x05f  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>,
+							<0x17f  S_PERIOD_T_LRA  0>,
+							<0x15f  S_PERIOD_T_LRA  0>,
+							<0x13f  S_PERIOD_T_LRA  0>,
+							<0x11f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-pattern-preload;
+				qcom,wf-auto-res-disable;
+			};
+
+			effect_1 {
+				/* DOUBLE_CLICK */
+				qcom,effect-id = <1>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x01f  S_PERIOD_T_LRA  0>,
+							<0x03f  S_PERIOD_T_LRA  0>,
+							<0x05f  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>,
+							<0x17f  S_PERIOD_T_LRA  0>,
+							<0x15f  S_PERIOD_T_LRA  0>,
+							<0x13f  S_PERIOD_T_LRA  0>,
+							<0x11f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			effect_2 {
+				/* TICK */
+				qcom,effect-id = <2>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x01f  S_PERIOD_T_LRA  0>,
+							<0x03f  S_PERIOD_T_LRA  0>,
+							<0x05f  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>,
+							<0x17f  S_PERIOD_T_LRA  0>,
+							<0x15f  S_PERIOD_T_LRA  0>,
+							<0x13f  S_PERIOD_T_LRA  0>,
+							<0x11f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			effect_3 {
+				/* THUD */
+				qcom,effect-id = <3>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x01f  S_PERIOD_T_LRA  0>,
+							<0x03f  S_PERIOD_T_LRA  0>,
+							<0x05f  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>,
+							<0x17f  S_PERIOD_T_LRA  0>,
+							<0x15f  S_PERIOD_T_LRA  0>,
+							<0x13f  S_PERIOD_T_LRA  0>,
+							<0x11f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			effect_4 {
+				/* POP */
+				qcom,effect-id = <4>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x01f  S_PERIOD_T_LRA  0>,
+							<0x03f  S_PERIOD_T_LRA  0>,
+							<0x05f  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>,
+							<0x17f  S_PERIOD_T_LRA  0>,
+							<0x15f  S_PERIOD_T_LRA  0>,
+							<0x13f  S_PERIOD_T_LRA  0>,
+							<0x11f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			effect_5 {
+				/* HEAVY CLICK */
+				qcom,effect-id = <5>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x01f  S_PERIOD_T_LRA  0>,
+							<0x03f  S_PERIOD_T_LRA  0>,
+							<0x05f  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>,
+							<0x17f  S_PERIOD_T_LRA  0>,
+							<0x15f  S_PERIOD_T_LRA  0>,
+							<0x13f  S_PERIOD_T_LRA  0>,
+							<0x11f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_0 {
+				/* NOOP */
+				qcom,primitive-id = <0>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0  S_PERIOD_T_LRA  0>,
+							<0  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_1 {
+				/* CLICK */
+				qcom,primitive-id = <1>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_2 {
+				/* THUD */
+				qcom,primitive-id = <2>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_3 {
+				/* SPIN */
+				qcom,primitive-id = <3>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_4 {
+				/* QUICK_RISE */
+				qcom,primitive-id = <4>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_5 {
+				/* SLOW_RISE */
+				qcom,primitive-id = <5>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_6 {
+				/* QUICK_FALL */
+				qcom,primitive-id = <6>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+
+			primitive_7 {
+				/* LIGHT_TICK */
+				qcom,primitive-id = <7>;
+				qcom,wf-vmax-mv = <4800>;
+				qcom,wf-pattern-data =  <0x0ff  S_PERIOD_T_LRA  0>,
+							<0x07f  S_PERIOD_T_LRA  0>;
+				qcom,wf-pattern-period-us = <4167>;
+				qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
+				qcom,wf-auto-res-disable;
+			};
+		};
+	};
+};
+
+&thermal_zones {
+	pm5100-tz {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm5100_tz>;
+
+		trips {
+			pm5100_trip0: trip0 {
+				temperature = <95000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			pm5100_trip1: trip1 {
+				temperature = <115000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+
+			pm5100_trip2: trip2 {
+				temperature = <145000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+		};
+	};
+
+	pm5100-ibat-lvl0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm5100_bcl 0>;
+
+		trips {
+			ibat_lvl0:ibat-lvl0 {
+				temperature = <1500>;
+				hysteresis = <200>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm5100-ibat-lvl1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm5100_bcl 1>;
+
+		trips {
+			ibat_lvl1:ibat-lvl1 {
+				temperature = <1900>;
+				hysteresis = <200>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm5100-bcl-lvl0 {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm5100_bcl 5>;
+
+		trips {
+			bcl_lvl0: bcl-lvl0 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm5100-bcl-lvl1 {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm5100_bcl 6>;
+
+		trips {
+			bcl_lvl1: bcl-lvl1 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm5100-bcl-lvl2 {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm5100_bcl 7>;
+
+		trips {
+			bcl_lvl2: bcl-lvl2 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+	};
+
+	socd {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&bcl_soc>;
+
+		trips {
+			socd_trip:socd-trip {
+				temperature = <90>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+		};
+	};
+};
diff --git a/qcom/pm8010-rpm-regulator.dtsi b/qcom/pm8010-rpm-regulator.dtsi
new file mode 100644
index 00000000..bb498fe7
--- /dev/null
+++ b/qcom/pm8010-rpm-regulator.dtsi
@@ -0,0 +1,120 @@
+&rpm_bus {
+	rpm-regulator-ldom1 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldom";
+		qcom,resource-id = <1>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l1 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm8010_l1";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldom2 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldom";
+		qcom,resource-id = <2>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <10000>;
+		status = "disabled";
+
+		regulator-l2 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm8010_l2";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldom3 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldom";
+		qcom,resource-id = <3>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <0>;
+		status = "disabled";
+
+		regulator-l3 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm8010_l3";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldom4 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldom";
+		qcom,resource-id = <4>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <0>;
+		status = "disabled";
+
+		regulator-l4 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm8010_l4";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldom5 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldom";
+		qcom,resource-id = <5>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <0>;
+		status = "disabled";
+
+		regulator-l5 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm8010_l5";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldom6 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldom";
+		qcom,resource-id = <6>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <0>;
+		status = "disabled";
+
+		regulator-l6 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm8010_l6";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+
+	rpm-regulator-ldom7 {
+		compatible = "qcom,rpm-smd-regulator-resource";
+		qcom,resource-name = "ldom";
+		qcom,resource-id = <7>;
+		qcom,regulator-type = <0>;
+		qcom,regulator-hw-type = "pmic5-ldo";
+		qcom,hpm-min-load = <0>;
+		status = "disabled";
+
+		regulator-l7 {
+			compatible = "qcom,rpm-smd-regulator";
+			regulator-name = "pm8010_l7";
+			qcom,set = <3>;
+			status = "disabled";
+		};
+	};
+};