From 69959416bd0e448e33b4a27ab40e4f4c6396710d Mon Sep 17 00:00:00 2001
From: Viken Dadhaniya <vdadhani@qti.qualcomm.com>
Date: Tue, 28 Jun 2022 11:16:33 +0530
Subject: [PATCH] ARM: dts: msm: Add CS1 pinctrl support for Lassen

Add pin control changes for multiple cs support(cs0 and cs1)
for SPI on Lassen target. For SE14 we have usecase for two slave
devices over SPI. CS0 for SI5518 and CS1 for LMK01020.

Change-Id: I735421da3a8ab31d9197c2e5d0340931963c87c3
---
 qcom/cinder-pinctrl.dtsi | 23 ++++++++++++++++++-----
 qcom/cinder-qupv3.dtsi   |  4 +++-
 2 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/qcom/cinder-pinctrl.dtsi b/qcom/cinder-pinctrl.dtsi
index dde7a039..d1c6e3a0 100644
--- a/qcom/cinder-pinctrl.dtsi
+++ b/qcom/cinder-pinctrl.dtsi
@@ -1635,7 +1635,7 @@
 			};
 		};
 
-		qupv3_se14_spi_cs_active: qupv3_se14_spi_cs_active {
+		qupv3_se14_spi_cs_0_active: qupv3_se14_spi_cs_0_active {
 			mux {
 				pins = "gpio37";
 				function = "qup1_se6_l3";
@@ -1648,16 +1648,29 @@
 			};
 		};
 
+		qupv3_se14_spi_cs_1_active: qupv3_se14_spi_cs_1_active {
+			mux {
+				pins = "gpio38";
+				function = "qup1_se6_l4";
+			};
+
+			config {
+				pins = "gpio38";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
 		qupv3_se14_spi_sleep: qupv3_se14_spi_sleep {
 			mux {
-				pins = "gpio34", "gpio35",
-					"gpio36", "gpio37";
+				pins = "gpio34", "gpio35", "gpio36",
+					"gpio37", "gpio38";
 				function = "gpio";
 			};
 
 			config {
-				pins = "gpio34", "gpio35",
-					"gpio36", "gpio37";
+				pins = "gpio34", "gpio35", "gpio36",
+					"gpio37", "gpio38";
 				drive-strength = <2>;
 				bias-disable;
 			};
diff --git a/qcom/cinder-qupv3.dtsi b/qcom/cinder-qupv3.dtsi
index 7b193c7d..6184906d 100644
--- a/qcom/cinder-qupv3.dtsi
+++ b/qcom/cinder-qupv3.dtsi
@@ -725,8 +725,10 @@
 			<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_1>,
 			<&system_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
 			pinctrl-names = "default", "sleep";
+			/* CS0 for SI5518 and CS1 for LMK01020 */
 			pinctrl-0 = <&qupv3_se14_spi_mosi_active>, <&qupv3_se14_spi_miso_active>,
-				<&qupv3_se14_spi_clk_active>, <&qupv3_se14_spi_cs_active>;
+				<&qupv3_se14_spi_clk_active>, <&qupv3_se14_spi_cs_0_active>,
+				<&qupv3_se14_spi_cs_1_active>;
 			pinctrl-1 = <&qupv3_se14_spi_sleep>;
 			dmas = <&gpi_dma1 0 6 1 64 0>,
 				<&gpi_dma1 1 6 1 64 0>;