From 9071baf3c6dd49615cbc2f648f3c5b6fd1b1950d Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Wed, 7 Jul 2021 13:55:58 -0700 Subject: [PATCH 1/3] dt-bindings: usb: Add bindings for MSM SSUSB controller Add bindings documenting the MSM SuperSpeed USB controller with compatible "qcom,dwc-usb3-msm". Change-Id: I2e1a611c70af09521cc23b19eba101505bf9b37e --- bindings/usb/msm-ssusb.txt | 148 +++++++++++++++++++++++++++++++++++++ 1 file changed, 148 insertions(+) create mode 100644 bindings/usb/msm-ssusb.txt diff --git a/bindings/usb/msm-ssusb.txt b/bindings/usb/msm-ssusb.txt new file mode 100644 index 00000000..e4f788e6 --- /dev/null +++ b/bindings/usb/msm-ssusb.txt @@ -0,0 +1,148 @@ +MSM SuperSpeed USB3.0 SoC controller + +Required properties : +- compatible : should be "qcom,dwc-usb3-msm" + - reg: Address and length of the register set for the device + Required regs are: + "core_base" : usb controller register set +- interrupts: IRQ lines used by this controller +- interrupt-names : Interrupt resource entries are : + "pwr_event_irq" : Interrupt to controller for asynchronous events in LPM. + Used for SS-USB power events. + - clocks: a list of phandles to the controller clocks. Use as per + Documentation/devicetree/bindings/clock/clock-bindings.txt + - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" + property. Required clocks are "xo", "iface_clk", "core_clk", "sleep_clk" + and "utmi_clk". +- resets: reset specifier pair consists of phandle for the reset provider + and reset lines used by this controller. +- reset-names: reset signal name strings sorted in the same order as the resets + property. + +Optional properties : +- reg: Additional registers + "ahb2phy_base" : top-level register to configure read/write wait cycle with + both QMP and QUSB PHY registers. + +- interconnects: Pairs of phandles and interconnect provider specifiers. See + interconnect.txt for more details. +- interconnect-names: List of interconnect path names strings corresponding to + each interconnect specifier pair in the interconnects property. Currently + the following paths are supported: + "usb-ddr", "usb-ipa", "ddr-usb" + +- qcom,default-bus-vote: To use default bus voting other than NOMINAL. Default is NOMINAL. +- interrupt-names : Optional interrupt resource entries are: + "ss_phy_irq" : Interrupt from super speed phy for wake up notification. + "hs_phy_irq" : Interrupt from HS PHY for asynchronous events in LPM. + "dp_hs_phy_irq" : Interrupt from HS PHY for asynchronous events in LPM + going through PDC. (use qcom,use-pdc-interrupts property) + "dm_hs_phy_irq" : Interrupt from HS PHY for asynchronous events in LPM + going through PDC. (use qcom,use-pdc-interrupts property) + + - clocks: a list of phandles to the controller clocks. Use as per + Documentation/devicetree/bindings/clock/clock-bindings.txt + - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" + property. Optional clocks are "bus_aggr_clk", "noc_aggr_clk" and "cfg_ahb_clk". +- qcom,charging-disabled: If present then battery charging using USB + is disabled. +- vbus_dwc3-supply: phandle to the 5V VBUS supply regulator used for host mode. +- USB3_GDSC-supply : phandle to the globally distributed switch controller + regulator node to the USB controller. +- dpdm-supply: phandle to dpdm supply which will be used to drive dp/dm lines + in high-z state. +- qcom,dwc-usb3-msm-tx-fifo-size: If present, represents RAM size available for + TX fifo allocation in bytes +- qcom,lpm-to-suspend-delay-ms: Indicates timeout (in milliseconds) to release wakeup source + after USB is kept into LPM. +- qcom,disable-dev-mode-pm: If present, it disables PM runtime functionality for device mode. +- qcom,core-clk-rate: If present, indicates clock frequency to be set for USB master clock. +- qcom,core-clk-rate-hs: If present, indicates min core clock frequency required to support + hs speed. +- qcom,use-pdc-interrupts: It present, it configures provided PDC IRQ with required + configuration for wakeup functionality. +- extcon: phandles to external connector devices. First phandle should point to + external connector, which provide type-C based "USB" cable events, the + second should point to external connector device, which provide type-C + "USB-HOST" cable events. A single phandle may be specified if a single + connector device provides both "USB" and "USB-HOST" events. An optional + third phandle may be specified for EUD based attach/detach events. A + mandatory fourth phandle has to be specified to provide microUSB based + "USB" cable events. An optional fifth phandle may be specified to provide + microUSB based "USB-HOST" cable events. Only the fourth phandle may be + specified if a single connector device provides both "USB" and "USB-HOST" + events. +- qcom,num-gsi-evt-buffs: If present, specifies number of GSI based hardware accelerated + event buffers. 1 event buffer is needed per h/w accelerated endpoint. +- qcom,gsi-reg-offset: USB GSI wrapper registers offset. It is must to provide this + if qcom,num-gsi-evt-buffs property is specified. Check dwc3-msm driver for order + and name of register offset need to provide. +- qcom,gsi-disable-io-coherency: IO-coherency is enabled by default in usb gsi driver. + This property disables io-coherency in usb gsi driver. +- qcom,pm-qos-latency: This represents max tolerable CPU latency in microsecs, + which is used as a vote by driver to get max performance in perf mode. +- qcom,smmu-s1-bypass: If present, configure SMMU to bypass stage 1 translation. +- qcom,dbm-version: If present, specifies DBM version. Currently "1.4" or "1.5" + are supported. If omitted, assume HW supports "1.5". +- qcom,host-poweroff-in-pm-suspend: If present, allow PM suspend to happen + irrespective of runtimePM state of host and power collapse the core. + This also leads to reset-resume of connected devices on PM resume. +- qcom,default-mode-none: If present, do not start any mode on probe for an OTG + capable DWC3 which does not have extcon handle. +- qcom,default-mode-host: If present, start host mode on probe for an OTG + capable DWC3 which does not have extcon handle. +- qcom,usb-charger: If present, phandle to device node associated with charger + device that handles battery charging on this USB port. + +Sub nodes: +- Sub node for "DWC3- USB3 controller". + This sub node is required property for device node. The properties of this subnode + are specified in dwc3.txt. + +Example MSM USB3.0 controller device node : + usb@f9200000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xf9200000 0xfc000>, + <0xf9b3e000 0x3ff>; + reg-names = "core_base", + "ahb2phy_base", + interrupts = <0 133 0>; + interrupt-names = "hs_phy_irq"; + vbus_dwc3-supply = <&pm8941_mvs1>; + USB3_GDSC-supply = <&gdsc_usb30>; + qcom,dwc-usb3-msm-dbm-eps = <4> + qcom,dwc_usb3-adc_tm = <&pm8941_adc_tm>; + qcom,dwc-usb3-msm-tx-fifo-size = <29696>; + qcom,usb-dbm = <&dbm_1p4>; + qcom,lpm-to-suspend-delay-ms = <2>; + qcom,num-gsi-evt-buffs = <0x2>; + qcom,pm-qos-latency = <2>; + + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; + + clocks = <&clock_gcc clk_gcc_usb30_master_clk>, + <&clock_gcc clk_gcc_cfg_noc_usb3_axi_clk>, + <&clock_gcc clk_gcc_aggre1_usb3_axi_clk>, + <&clock_rpmcc RPM_AGGR2_NOC_CLK>, + <&clock_gcc clk_gcc_usb30_mock_utmi_clk>, + <&clock_gcc clk_gcc_usb30_sleep_clk>, + <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, + <&clock_gcc clk_cxo_dwc3_clk>; + + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "noc_aggr_clk", + "utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo"; + + resets = <&clock_gcc GCC_USB_30_BCR>; + reset-names = "core_reset"; + + dwc3@f9200000 { + compatible = "synopsys,dwc3"; + reg = <0xf9200000 0xfc000>; + interrupts = <0 131 0>, <0 179 0>; + interrupt-names = "irq", "otg_irq"; + tx-fifo-resize; + }; + }; From 1840461354e36952ba2fa1c89c4f8b7761407f3e Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Fri, 25 Jun 2021 09:04:42 -0700 Subject: [PATCH 2/3] ARM: dts: msm: Add USB controller related configuration for Kalama Add USB controller related configuration for Kalama. Change-Id: I3a96a884f1653da7f628f6e79e060fab3f4bfa6e --- qcom/kalama-usb.dtsi | 47 ++++++++++++++++++++++++++++++++++++++++++++ qcom/kalama.dtsi | 1 + 2 files changed, 48 insertions(+) create mode 100644 qcom/kalama-usb.dtsi diff --git a/qcom/kalama-usb.dtsi b/qcom/kalama-usb.dtsi new file mode 100644 index 00000000..f54a58bc --- /dev/null +++ b/qcom/kalama-usb.dtsi @@ -0,0 +1,47 @@ +#include + +&soc { + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event_irq"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xd93c>; + + interrupts = ; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,ssp-u3-u0-quirk; + maximum-speed = "super-speed-plus"; + usb-role-switch; + }; + }; +}; diff --git a/qcom/kalama.dtsi b/qcom/kalama.dtsi index b2f94b2b..034b0eea 100644 --- a/qcom/kalama.dtsi +++ b/qcom/kalama.dtsi @@ -715,6 +715,7 @@ #include "kalama-pinctrl.dtsi" #include "kalama-qupv3.dtsi" +#include "kalama-usb.dtsi" &qupv3_se7_2uart { status = "ok"; From fe31e3059a59a30bd26be2d3c521880d8a01b7b3 Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Wed, 7 Jul 2021 16:15:48 -0700 Subject: [PATCH 3/3] ARM: dts: msm: Add USB controller and PHY configuration for Kalama RUMI Add USB controller and PHY configuration for Kalama RUMI. Change-Id: I0473ed6efb8d154c3b93bc3e84b1a6765716c89c --- qcom/kalama-rumi.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/qcom/kalama-rumi.dtsi b/qcom/kalama-rumi.dtsi index d2952a9f..ccfd7e6c 100644 --- a/qcom/kalama-rumi.dtsi +++ b/qcom/kalama-rumi.dtsi @@ -8,3 +8,33 @@ &memtimer { clock-frequency = <192000>; }; + +&soc { + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + usb_emu_phy: phy@a784000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x0a784000 0x9500>; + + qcom,emu-init-seq = <0xfffff 0x4 + 0xffff3 0x4 + 0xffff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x000101F0 0x20 + 0x00100000 0x3c + 0x0 0x3c + 0x0010060 0x3c + 0x0 0x4>; + }; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb_emu_phy>, <&usb_nop_phy>; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + }; +};