From 1b8c60074c48f000074b8f20a5ca5adb1a1546f9 Mon Sep 17 00:00:00 2001
From: Vijayanand Jitta <vjitta@qti.qualcomm.com>
Date: Tue, 21 Jun 2022 11:40:42 +0530
Subject: [PATCH 1/2] ARM: dts: msm: Add initial smmu configuration for sdxpinn

Describe the interrupts, register map used by the iommu
device on sdxpinn.

Change-Id: I951a717edf833837e30fe17637c772eb50c1c0d7
---
 qcom/msm-arm-smmu-sdxpinn.dtsi | 107 +++++++++++++++++++++++++++++++++
 qcom/sdxpinn.dtsi              |   2 +
 2 files changed, 109 insertions(+)
 create mode 100644 qcom/msm-arm-smmu-sdxpinn.dtsi

diff --git a/qcom/msm-arm-smmu-sdxpinn.dtsi b/qcom/msm-arm-smmu-sdxpinn.dtsi
new file mode 100644
index 00000000..c894d791
--- /dev/null
+++ b/qcom/msm-arm-smmu-sdxpinn.dtsi
@@ -0,0 +1,107 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+		apps_smmu: apps-smmu@15000000 {
+		compatible = "qcom,qsmmu-v500";
+		reg = <0x15000000 0x40000>;
+		#iommu-cells = <2>;
+		qcom,use-3-lvl-tables;
+		#global-interrupts = <1>;
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		dma-coherent;
+
+		interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+
+		anoc_1_qtb: anoc_1_qtb@1680000 {
+			compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
+			reg = <0x1680000 0x1000>;
+			qcom,stream-id-range = <0x0 0x400>;
+			qcom,iova-width = <36>;
+			qcom,num-qtb-ports = <1>;
+		};
+
+		ipa_qtb: ipa_qtb@1688000 {
+			compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
+			reg = <0x1688000 0x1000>;
+			qcom,stream-id-range = <0x400 0x400>;
+			qcom,iova-width = <41>;
+			qcom,num-qtb-ports = <1>;
+		};
+
+		pcie_qtb: pcie_qtb@16d0000 {
+			compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
+			reg = <0x16d0000 0x1000>;
+			qcom,stream-id-range = <0x800 0x400>;
+			qcom,iova-width = <36>;
+			qcom,num-qtb-ports = <1>;
+			qcom,opt-out-tbu-halting;
+		};
+	};
+
+	dma_dev {
+		compatible = "qcom,iommu-dma";
+		memory-region = <&system_cma>;
+	};
+
+	iommu_test_device {
+		compatible = "qcom,iommu-debug-test";
+
+		usecase0_apps {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x3e0 0x0>;
+		};
+
+		usecase1_apps_fastmap {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x3e0 0x0>;
+			qcom,iommu-dma = "fastmap";
+		};
+
+		usecase2_apps_atomic {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x3e0 0x0>;
+			qcom,iommu-dma = "atomic";
+		};
+
+		usecase3_apps_dma {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x3e0 0x0>;
+			dma-coherent;
+		};
+
+	};
+};
diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi
index 5aaa8d34..78c7813a 100644
--- a/qcom/sdxpinn.dtsi
+++ b/qcom/sdxpinn.dtsi
@@ -112,6 +112,7 @@
 };
 
 #include "sdxpinn-reserved-memory.dtsi"
+
 &reserved_memory {
 	#address-cells = <2>;
 	#size-cells = <2>;
@@ -379,6 +380,7 @@
 #include "sdxpinn-regulators.dtsi"
 #include "sdxpinn-pinctrl.dtsi"
 #include "sdxpinn-qupv3.dtsi"
+#include "msm-arm-smmu-sdxpinn.dtsi"
 
 &qupv3_se1_2uart {
 	status = "ok";

From 809acb76947379a4e119d2bbe07914f97f66a8c2 Mon Sep 17 00:00:00 2001
From: Vijayanand Jitta <vjitta@qti.qualcomm.com>
Date: Fri, 24 Jun 2022 09:47:45 +0530
Subject: [PATCH 2/2] ARM: dts: msm: Add initial dmabuf heaps for sdxpinn

System, secure system heaps are by default enabled.

Change-Id: Id1dfe8d4a32aa64f0420c1e8ddeeca24e9681025
---
 qcom/sdxpinn-dma-heaps.dtsi | 7 +++++++
 qcom/sdxpinn.dtsi           | 1 +
 2 files changed, 8 insertions(+)
 create mode 100644 qcom/sdxpinn-dma-heaps.dtsi

diff --git a/qcom/sdxpinn-dma-heaps.dtsi b/qcom/sdxpinn-dma-heaps.dtsi
new file mode 100644
index 00000000..224331fe
--- /dev/null
+++ b/qcom/sdxpinn-dma-heaps.dtsi
@@ -0,0 +1,7 @@
+#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h>
+
+&soc {
+	qcom,dma-heaps {
+		compatible = "qcom,dma-heaps";
+	};
+};
diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi
index 78c7813a..62a941df 100644
--- a/qcom/sdxpinn.dtsi
+++ b/qcom/sdxpinn.dtsi
@@ -381,6 +381,7 @@
 #include "sdxpinn-pinctrl.dtsi"
 #include "sdxpinn-qupv3.dtsi"
 #include "msm-arm-smmu-sdxpinn.dtsi"
+#include "sdxpinn-dma-heaps.dtsi"
 
 &qupv3_se1_2uart {
 	status = "ok";