diff --git a/bindings/msm-cam-cpas.txt b/bindings/msm-cam-cpas.txt
index 1295a562..52a2ebf6 100644
--- a/bindings/msm-cam-cpas.txt
+++ b/bindings/msm-cam-cpas.txt
@@ -156,6 +156,16 @@ First Level Node - CAM CPAS device
   Definition: Percentage value to be added to camnoc bw while calculating
               camnoc axi clock frequency.
 
+- rpmh-bcm-info
+  Usage: optional
+  Value type: <u32:idx> <u32:bcm_fe> <u32:bcm_be> <u32:ddr_idx> <u32:mmnoc_idx>
+  Definition: Rpmh bcm register map
+  idx: Total number of BCMs
+  bcm_fe: First BCM FE (front-end) register offset.
+  bcm_be: First BCM BE (back-end) register offset.
+  ddr_idx: DDR BCM index
+  mmnoc_idx: MMNOC BCM index
+
 - qcom,msm-bus,name
 - qcom,msm-bus,num-cases
 - qcom,msm-bus,num-paths
diff --git a/shima-camera.dtsi b/shima-camera.dtsi
index 86038b5a..3b923c78 100644
--- a/shima-camera.dtsi
+++ b/shima-camera.dtsi
@@ -1313,10 +1313,11 @@
 		label = "cpas";
 		arch-compat = "cpas_top";
 		status = "ok";
-		reg-names = "cam_cpas_top", "cam_camnoc";
+		reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh";
 		reg = <0xac40000 0x1000>,
-			<0xac42000 0x8000>;
-		reg-cam-base = <0x40000 0x42000>;
+			<0xac42000 0x8000>,
+			<0xbbf0000 0x1F00>;
+		reg-cam-base = <0x40000 0x42000 0x0BBF0000>;
 		cam_hw_fuse = <CAM_CPAS_MF_HDR_ENABLE 0x007801E0 0x400000 CAM_CPAS_FEATURE_TYPE_ENABLE 0xFF>,
 			<CAM_CPAS_MP_LIMIT_FUSE 0x7801EC 0x18000000 CAM_CPAS_FEATURE_TYPE_VALUE 0xFF>;
 		interrupt-names = "cpas_camnoc";
@@ -1367,6 +1368,7 @@
 		interconnect-names = "cam_ahb";
 		interconnects =<&gem_noc MASTER_APPSS_PROC
 			&config_noc SLAVE_CAMERA_CFG>;
+		rpmh-bcm-info = <12 0x4 0x800 0 4>;
 		cam-ahb-num-cases = <8>;
 		cam-ahb-bw-KBps =
 			<0 0>, <0 76800>, <0 76800>, <0 150000>, <0 150000>,