From 36bf2a69d3b1b2c20b5be95abd8d5a4e4b7ac605 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Thu, 13 Oct 2022 15:25:30 +0530 Subject: [PATCH 01/41] ARM: dts: msm: Add cluster ID to core hang DT node Add cluster ID support to core hang DT node for Khaje. Change-Id: Ia0c34debb13735ae1d1928e26a1161aff26ad3aa --- qcom/khaje.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index 6c46439c..46c6f5d5 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -2128,6 +2128,7 @@ qcom,chd_silver { compatible = "qcom,core-hang-detect"; label = "silver"; + cluster-id = <0>; qcom,threshold-arr = <0x0f1880b0 0x0f1980b0 0x0f1a80b0 0x0f1b80b0>; qcom,config-arr = <0x0f1880b8 0x0f1980b8 @@ -2137,6 +2138,7 @@ qcom,chd_gold { compatible = "qcom,core-hang-detect"; label = "gold"; + cluster-id = <1>; qcom,threshold-arr = <0x0f0880b0 0x0f0980b0 0x0f0a80b0 0x0f0b80b0>; qcom,config-arr = <0x0f0880b8 0x0f0980b8 From 84aa386a5e485788c69c07d3a5e3bd8e00d7ec34 Mon Sep 17 00:00:00 2001 From: Chris Goldsworthy Date: Mon, 19 Sep 2022 18:30:55 -0700 Subject: [PATCH 02/41] ARM: dts: qcom: Provide a 16 MB CMA region to be used by glink Provide a contiguous region for use by glink. Unless explicitly instructed, this region should not be used by external customers. Change-Id: Icc6a228d4827eda38b3917b443110c2bbe9219c1 --- qcom/kalama.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/kalama.dtsi b/qcom/kalama.dtsi index 6955570f..c155a137 100644 --- a/qcom/kalama.dtsi +++ b/qcom/kalama.dtsi @@ -645,6 +645,14 @@ size = <0x0 0x1000000>; }; + glink_contig_mem: glink_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + ramoops_mem: ramoops_region { compatible = "ramoops"; alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>; From fed04e5127e04eb2411d392721782a6dfeb2fe49 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Wed, 19 Oct 2022 20:32:11 +0530 Subject: [PATCH 03/41] ARM: dts: msm: Add USB clock handle for ICB CINDER Add usb clock handler to enable qos programming of usb master Change-Id: I1861eff39e7da6ef2ffddf296de7cbcd98130ed3 --- qcom/cinder.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi index 0bc99812..2dc5dd74 100644 --- a/qcom/cinder.dtsi +++ b/qcom/cinder.dtsi @@ -1521,7 +1521,8 @@ qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; clocks = <&ecpricc ECPRI_CC_ECPRI_DMA_NOC_CLK>, - <&ecpricc ECPRI_CC_ECPRI_FAST_DIV2_NOC_CLK>; + <&ecpricc ECPRI_CC_ECPRI_FAST_DIV2_NOC_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>; }; gem_noc: interconnect@19100000 { From 7ef33d36a70d7b8caa09d993e30402b88e870852 Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Fri, 21 Oct 2022 07:09:48 -0700 Subject: [PATCH 04/41] ARM: dts: msm: add multi EE flag QUPV3 SE2 is i2c shared usecase, so added shared flag in dt entry to support mult EE usecase. Change-Id: I1eff8c2f59a3c0efccc3c3442ae01d29ad108314 --- qcom/sdxpinn-qupv3.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxpinn-qupv3.dtsi b/qcom/sdxpinn-qupv3.dtsi index 6b5d3a59..2492462f 100644 --- a/qcom/sdxpinn-qupv3.dtsi +++ b/qcom/sdxpinn-qupv3.dtsi @@ -168,6 +168,7 @@ dmas = <&gpi_dma0 0 2 3 64 0>, <&gpi_dma0 1 2 3 64 0>; dma-names = "tx", "rx"; + qcom,shared; status = "disabled"; }; From e501109283b29107da6018f8bfecaf19b16ba439 Mon Sep 17 00:00:00 2001 From: Huang Yiwei Date: Mon, 26 Sep 2022 10:48:19 +0800 Subject: [PATCH 05/41] ARM: dts: msm: Add debug-kinfo for Kalama Add device node and reserved memory to enable debug-kinfo for Kalama, so necessary kernel information can be stored in mem and used by other drivers. Change-Id: I4f30c69eb87c0012f110d6cbc29350f959002248 --- qcom/kalama.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/kalama.dtsi b/qcom/kalama.dtsi index 016076af..96710bee 100644 --- a/qcom/kalama.dtsi +++ b/qcom/kalama.dtsi @@ -662,6 +662,12 @@ size = <0x0 0x2000000>; linux,cma-default; }; + + kinfo_mem: debug_kinfo_region { + alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>; + size = <0x0 0x1000>; + no-map; + }; }; &soc { @@ -3859,6 +3865,11 @@ }; msm_gpu: qcom,kgsl-3d0@3d00000 { }; + + google,debug-kinfo { + compatible = "google,debug-kinfo"; + memory-region = <&kinfo_mem>; + }; }; &firmware { From f2e2bd6fb87c27f1d876a69794d3283197d0b4c0 Mon Sep 17 00:00:00 2001 From: Fei Yang Date: Thu, 27 Oct 2022 10:15:30 +0800 Subject: [PATCH 06/41] ARM: dts: qcom: Add virtio_regulator node for direwolf vm Add virtio_regulator for automotive vm on direwolf. Change-Id: I4bcc49324d0988fd33a6e7bc9750ca46ef48686c --- qcom/direwolf-vm.dtsi | 112 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 285fb72f..82a270b1 100644 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -5,3 +5,115 @@ qcom,msm-name = "SA_DIREWOLF_IVI"; qcom,msm-id = <460 0x10000>; }; + +®ulator { + virt_regulator { + compatible = "virtio,device31"; + + gcc_usb30_prim_gdsc: gcc_usb30_prim_gdsc { + regulator-name = "gcc_usb30_prim_gdsc"; + }; + + gcc_usb30_sec_gdsc: gcc_usb30_sec_gdsc { + regulator-name = "gcc_usb30_sec_gdsc"; + }; + + gcc_usb30_mp_gdsc: gcc_usb30_mp_gdsc { + regulator-name = "gcc_usb30_mp_gdsc"; + }; + + gcc_pcie_2a_gdsc: gcc_pcie_2a_gdsc { + regulator-name = "gcc_pcie_2a_gdsc"; + }; + + gcc_pcie_2b_gdsc: gcc_pcie_2b_gdsc { + regulator-name = "gcc_pcie_2b_gdsc"; + }; + + gcc_pcie_3a_gdsc: gcc_pcie_3a_gdsc { + regulator-name = "gcc_pcie_3a_gdsc"; + }; + + gcc_pcie_3b_gdsc: gcc_pcie_3b_gdsc { + regulator-name = "gcc_pcie_3b_gdsc"; + }; + + gcc_pcie_4_gdsc: gcc_pcie_4_gdsc { + regulator-name = "gcc_pcie_4_gdsc"; + }; + + L3A0: pm8540_a0_l3: regulator-pm8540_a0-l3 { + regulator-name = "ldoa3"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + }; + + S4E0: pm8540_e0_s4: regulator-pm8540_e0-s4 { + regulator-name = "smpe4"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <2040000>; + }; + + L5A0: pm8540_a0_l5: regulator-pm8540_a0-l5 { + regulator-name = "ldoa5"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + }; + + L6G0: pm8540_g0_l6: regulator-pm8540_g0-l6 { + regulator-name = "ldog6"; + }; + + L7A0: pm8540_a0_l7: regulator-pm8540_a0-l7 { + regulator-name = "ldoa7"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L11A0: pm8540_a0_l11: regulator-pm8540_a0-l11 { + regulator-name = "ldoa11"; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + }; + + L13A0: pm8540_a0_l13: regulator-pm8540_a0-l13 { + regulator-name = "ldoa13"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3544000>; + }; + + L1C0: pm8540_c0_l1: regulator-pm8540_c0-l1 { + regulator-name = "ldoc1"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + }; + + L7C0: pm8540_c0_l7: regulator-pm8540_c0-l7 { + regulator-name = "ldoc7"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L2C0: pm8540_c0_l2: regulator-pm8540_c0-l2 { + regulator-name = "ldoc2"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3544000>; + }; + + L15A0: pm8540_a0_l15: regulator-pm8540_a0-l15 { + regulator-name = "ldoa15"; + }; + + L7G0: pm8540_g0_l7: regulator-pm8540_g0-l7 { + regulator-name = "ldog7"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L4C0: pm8540_c0_l4: regulator-pm8540_c0-l4 { + regulator-name = "ldoc4"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + }; + }; +}; From 8f3535b6b32f13043602370ee5734ce3171adb85 Mon Sep 17 00:00:00 2001 From: Krishnaiah Tadakamalla Date: Tue, 25 Oct 2022 06:16:47 -0700 Subject: [PATCH 07/41] ARM: dts: msm: Increase IOVA size for CB Increased IOVA size for aDSP and cDSP SMMU context banks. Change-Id: I9752862a541bba536b789075d503bd4438c1dade --- qcom/kalama.dtsi | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/qcom/kalama.dtsi b/qcom/kalama.dtsi index 016076af..d54506c5 100644 --- a/qcom/kalama.dtsi +++ b/qcom/kalama.dtsi @@ -2713,7 +2713,7 @@ iommus = <&apps_smmu 0x1961 0x0000>, <&apps_smmu 0x0C01 0x0020>, <&apps_smmu 0x19C1 0x0010>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; }; @@ -2724,7 +2724,7 @@ iommus = <&apps_smmu 0x1962 0x0000>, <&apps_smmu 0x0C02 0x0020>, <&apps_smmu 0x19C2 0x0010>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; }; @@ -2735,7 +2735,7 @@ iommus = <&apps_smmu 0x1963 0x0000>, <&apps_smmu 0x0C03 0x0020>, <&apps_smmu 0x19C3 0x0010>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; }; @@ -2746,7 +2746,7 @@ iommus = <&apps_smmu 0x1964 0x0000>, <&apps_smmu 0x0C04 0x0020>, <&apps_smmu 0x19C4 0x0010>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; }; @@ -2757,7 +2757,7 @@ iommus = <&apps_smmu 0x1965 0x0000>, <&apps_smmu 0x0C05 0x0020>, <&apps_smmu 0x19C5 0x0010>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; }; @@ -2768,7 +2768,7 @@ iommus = <&apps_smmu 0x1966 0x0000>, <&apps_smmu 0x0C06 0x0020>, <&apps_smmu 0x19C6 0x0010>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; }; @@ -2779,7 +2779,7 @@ iommus = <&apps_smmu 0x1967 0x0000>, <&apps_smmu 0x0C07 0x0020>, <&apps_smmu 0x19C7 0x0010>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; }; @@ -2790,7 +2790,7 @@ iommus = <&apps_smmu 0x1968 0x0000>, <&apps_smmu 0x0C08 0x0020>, <&apps_smmu 0x19C8 0x0010>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; }; @@ -2802,7 +2802,7 @@ iommus = <&apps_smmu 0x1969 0x0000>, <&apps_smmu 0x0C09 0x0020>, <&apps_smmu 0x19C9 0x0010>; - qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>; + qcom,iommu-dma-addr-pool = <0x40000000 0x98000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ dma-coherent; @@ -2813,7 +2813,7 @@ label = "adsprpc-smd"; iommus = <&apps_smmu 0x1003 0x0080>, <&apps_smmu 0x1063 0x0000>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; }; @@ -2823,7 +2823,7 @@ label = "adsprpc-smd"; iommus = <&apps_smmu 0x1004 0x0080>, <&apps_smmu 0x1064 0x0000>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; }; @@ -2833,7 +2833,7 @@ label = "adsprpc-smd"; iommus = <&apps_smmu 0x1005 0x0080>, <&apps_smmu 0x1065 0x0000>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; shared-cb = <8>; dma-coherent; @@ -2844,7 +2844,7 @@ label = "adsprpc-smd"; iommus = <&apps_smmu 0x1006 0x0080>, <&apps_smmu 0x1066 0x0000>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; }; @@ -2854,7 +2854,7 @@ label = "adsprpc-smd"; iommus = <&apps_smmu 0x1007 0x0080>, <&apps_smmu 0x1067 0x0000>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; }; @@ -2865,7 +2865,7 @@ iommus = <&apps_smmu 0x196C 0x0000>, <&apps_smmu 0x0C0C 0x0020>, <&apps_smmu 0x19CC 0x0010>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; }; @@ -2876,7 +2876,7 @@ iommus = <&apps_smmu 0x196D 0x0000>, <&apps_smmu 0x0C0D 0x0020>, <&apps_smmu 0x19CD 0x0010>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; }; @@ -2887,7 +2887,7 @@ iommus = <&apps_smmu 0x196E 0x0000>, <&apps_smmu 0x0C0E 0x0020>, <&apps_smmu 0x19CE 0x0010>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; }; @@ -2898,7 +2898,7 @@ iommus = <&apps_smmu 0x196F 0x0000>, <&apps_smmu 0x0C0F 0x0020>, <&apps_smmu 0x19CF 0x0010>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; }; From ddb820f3544376d5320a1b80256f3478dae60a8f Mon Sep 17 00:00:00 2001 From: Naga Rashmi Ayiluri Date: Mon, 10 Oct 2022 12:16:47 +0530 Subject: [PATCH 08/41] ARM: dts: msm: Add PCIe devicetree node for sa410m Add initial devicetree node to support PCIe controller on sa410m platform. Change-Id: Iffe666c96eddda12878c53e5cbb3cd29c61a3d9a --- qcom/sa410m-pcie.dtsi | 258 +++++++++++++++++++++++++++++++++++++++ qcom/sa410m-pinctrl.dtsi | 38 ++++++ qcom/sa410m.dtsi | 4 +- 3 files changed, 299 insertions(+), 1 deletion(-) create mode 100644 qcom/sa410m-pcie.dtsi diff --git a/qcom/sa410m-pcie.dtsi b/qcom/sa410m-pcie.dtsi new file mode 100644 index 00000000..b5268ced --- /dev/null +++ b/qcom/sa410m-pcie.dtsi @@ -0,0 +1,258 @@ +#include + +&soc { + pcie0: qcom,pcie@05020000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x05020000 0x3000>, + <0x05026000 0x1000>, + <0x18000000 0xf20>, + <0x18000f20 0xa8>, + <0x18001000 0x1000>, + <0x18100000 0x100000>, + <0x05023000 0x1000>; + + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", + "conf", "mhi"; + #adddress-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x18200000 0x18200000 0x0 0x100000>, + <0x02000000 0x0 0x18300000 0x18300000 0x0 0x27d00000>; + + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; + + qcom,phy-sequence = <0x0800 0x01 0x0 + 0x0804 0x03 0x0 + 0x0034 0x18 0x0 + 0x0038 0x10 0x0 + 0x0070 0x0f 0x0 + 0x00c8 0x01 0x0 + 0x0128 0x00 0x0 + 0x0144 0xff 0x0 + 0x0148 0x1f 0x0 + 0x0194 0x06 0x0 + 0x0048 0x0f 0x0 + 0x0178 0x00 0x0 + 0x019c 0x01 0x0 + 0x018c 0x20 0x0 + 0x0184 0x0a 0x0 + 0x00b4 0x20 0x0 + 0x000c 0x09 0x0 + 0x00ac 0x04 0x0 + 0x00d0 0x82 0x0 + 0x00e4 0x03 0x0 + 0x00e0 0x55 0x0 + 0x00dc 0x55 0x0 + 0x0054 0x00 0x0 + 0x0050 0x0d 0x0 + 0x004c 0x04 0x0 + 0x0174 0x35 0x0 + 0x003c 0x02 0x0 + 0x0040 0x1f 0x0 + 0x0078 0x04 0x0 + 0x0084 0x16 0x0 + 0x0090 0x30 0x0 + 0x010c 0x00 0x0 + 0x0108 0x80 0x0 + 0x00a8 0x01 0x0 + 0x000c 0x0a 0x0 + 0x0010 0x01 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0014 0x02 0x0 + 0x0018 0x00 0x0 + 0x0024 0x2f 0x0 + 0x0028 0x19 0x0 + 0x0268 0x45 0x0 + 0x0194 0x06 0x0 + 0x024c 0x02 0x0 + 0x02ac 0x12 0x0 + 0x0510 0x1c 0x0 + 0x051c 0x14 0x0 + 0x04d8 0x01 0x0 + 0x04dc 0x00 0x0 + 0x04e0 0xdb 0x0 + 0x0448 0x4b 0x0 + 0x041c 0x04 0x0 + 0x0410 0x04 0x0 + 0x0074 0x19 0x0 + 0x0854 0x04 0x0 + 0x09ac 0x00 0x0 + 0x08a0 0x40 0x0 + 0x09e0 0x00 0x0 + 0x09dc 0x40 0x0 + 0x09a8 0x00 0x0 + 0x08a4 0x40 0x0 + 0x08a8 0x73 0x0 + 0x09b0 0x07 0x0 + 0x09d8 0x99 0x0 + 0x0824 0x15 0x0 + 0x0828 0x0e 0x0 + 0x0800 0x00 0x0 + 0x0808 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 25 0>; + wake-gpio = <&tlmm 26 0>; + + gdsc-core-vdd-supply = <&gcc_pcie_0_gdsc>; + vreg-1p2-supply = <&L16A>; + vreg-0p9-supply = <&L12A>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MX_LEVEL>; + + qcom,vreg-1p2-voltage-level = <1800000 1800000 24000>; + qcom,vreg-0p9-voltage-level = <925000 925000 24000>; + qcom,vreg-cx-voltage-level = ; + qcom,vreg-mx-voltage-level = ; + + dma-coherent; + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + interconnects = <&sys_noc MASTER_PCIE &bimc_noc SLAVE_EBI_CH0>; + + msi-parent = <&pcie0_msi>; + + qcom,no-l0s-supported; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + + qcom,max-link-speed = <0x2>; + qcom,target-link-speed = <0x2>; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x4000000>; + + qcom,phy-status-offset = <0x974>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x804>; + qcom,core-preset = <0x77777777>; + + qcom,boot-option = <0x0>; + + linux,pci-domain = <0>; + + qcom,pcie-phy-ver = <2609>; + qcom,aux-clk-freq = <20>; + + qcom,smmu-sid-base = <0x0400>; + + iommu-map = <0x0 &apps_smmu 0x0400 0x1>, + <0x100 &apps_smmu 0x0401 0x1>, + <0x200 &apps_smmu 0x0402 0x1>, + <0x300 &apps_smmu 0x0403 0x1>, + <0x400 &apps_smmu 0x0404 0x1>, + <0x500 &apps_smmu 0x0405 0x1>, + <0x600 &apps_smmu 0x0406 0x1>, + <0x700 &apps_smmu 0x0407 0x1>, + <0x800 &apps_smmu 0x0408 0x1>, + <0x900 &apps_smmu 0x0409 0x1>, + <0xa00 &apps_smmu 0x040a 0x1>, + <0xb00 &apps_smmu 0x040b 0x1>, + <0xc00 &apps_smmu 0x040c 0x1>, + <0xd00 &apps_smmu 0x040d 0x1>, + <0xe00 &apps_smmu 0x040e 0x1>, + <0xf00 &apps_smmu 0x040f 0x1>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&pcie_0_pipe_clk>; + + clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_slv_q2a_axi_clk", + "pcie_pipe_clk_ext_src"; + + clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>; + + clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + pcie0_rp: pcie0_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie0_msi: qcom,pcie0_msi@0xf200040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0xf200040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; + diff --git a/qcom/sa410m-pinctrl.dtsi b/qcom/sa410m-pinctrl.dtsi index e80bf951..609b06df 100644 --- a/qcom/sa410m-pinctrl.dtsi +++ b/qcom/sa410m-pinctrl.dtsi @@ -739,6 +739,44 @@ rclk { pins = "sdc1_rclk"; bias-pull-down; + pcie0 { + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio24"; + function = "PCIE0_CLK_REQ"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + drive-strength = <2>; + bias-pull-up; + }; }; }; }; diff --git a/qcom/sa410m.dtsi b/qcom/sa410m.dtsi index 58bd314b..e5a4a65b 100644 --- a/qcom/sa410m.dtsi +++ b/qcom/sa410m.dtsi @@ -29,6 +29,7 @@ serial0 = &qupv3_se4_2uart; qpic_nand1 = &qnand_1; mmc0 = &sdhc_1; /*SDC1 eMMC slot*/ + pci-domain0 = &pcie0; }; firmware: firmware {}; @@ -203,7 +204,7 @@ }; chosen { - bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 pcie_ports=compat"; }; soc: soc { }; @@ -936,6 +937,7 @@ #include "monaco-gdsc.dtsi" #include "sa410m-qupv3.dtsi" #include "sa410m-dma-heap.dtsi" +#include "sa410m-pcie.dtsi" &gcc_emac0_gdsc { status = "ok"; From 67d1637dab53fae775427444f78b7c93802832d9 Mon Sep 17 00:00:00 2001 From: Singa Reddy Dasari Date: Fri, 14 Oct 2022 10:47:51 +0530 Subject: [PATCH 09/41] ARM: dts: qcom: Add usb node for auto sa8155 vm Add usb node for automotive VM platform. Change-Id: Ib7f49ba22fdd3e4798cc30e24a83f74a2aa6e32f --- qcom/sa8155-vm-la.dtsi | 20 +++ qcom/sa8155-vm-usb.dtsi | 309 ++++++++++++++++++++++++++++++++++++++++ qcom/sa8155-vm.dtsi | 1 + 3 files changed, 330 insertions(+) create mode 100644 qcom/sa8155-vm-usb.dtsi diff --git a/qcom/sa8155-vm-la.dtsi b/qcom/sa8155-vm-la.dtsi index 6f10825d..828cf0ab 100644 --- a/qcom/sa8155-vm-la.dtsi +++ b/qcom/sa8155-vm-la.dtsi @@ -19,3 +19,23 @@ &soc { }; + +&usb0 { + status = "ok"; +}; + +&usb2_phy0 { + status = "ok"; +}; + +&usb1 { + status = "ok"; +}; + +&usb2_phy1 { + status = "ok"; +}; + +&usb_qmp_phy { + status = "ok"; +}; diff --git a/qcom/sa8155-vm-usb.dtsi b/qcom/sa8155-vm-usb.dtsi new file mode 100644 index 00000000..63e5cef5 --- /dev/null +++ b/qcom/sa8155-vm-usb.dtsi @@ -0,0 +1,309 @@ +#include + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 9 IRQ_TYPE_EDGE_RISING>, + <&pdc 8 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "pwr_event_irq","dp_hs_phy_irq", + "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,ignore-wakeup-src-in-hostmode; + + status = "disabled"; + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xcd00>; + iommus = <&apps_smmu 0x140 0x0>; + qcom,iommu-dma = "bypass"; + + interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,usb2-gadget-lpm-disable; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + usb-role-switch; + }; + }; + + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@88e2000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e2000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&L5A>; + vdda18-supply = <&L12A>; + vdda33-supply = <&L2A>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "ref_clk_src", "ref_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; + qcom,rcal-mask = <0x1e00000>; + status = "disabled"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* Secondary USB port related controller */ + usb1: ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a800000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 11 IRQ_TYPE_EDGE_RISING>, + <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "pwr_event_irq","dp_hs_phy_irq", + "ss_phy_irq","dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + qcom,default-mode-host; + qcom,ignore-wakeup-src-in-hostmode; + + USB3_GDSC-supply = <&usb30_sec_gdsc>; + clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>; + + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk"; + + resets = <&gcc GCC_USB30_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + + status = "disabled"; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0x0a800000 0xd941>; + iommus = <&apps_smmu 0x160 0x0>; + qcom,iommu-dma = "bypass"; + + interrupts = ; + usb-phy = <&usb2_phy1>, <&usb_qmp_phy>; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,ssp-u3-u0-quirk; + snps,is-utmi-l1-suspend; + snps,usb2-gadget-lpm-disable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,force-gen1; + tx-fifo-resize; + maximum-speed = "super-speed"; + dr_mode = "otg"; + usb-role-switch; + }; + }; + + /* Secondary USB port related High Speed PHY */ + usb2_phy1: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&L5A>; + vdda18-supply = <&L12A>; + vdda33-supply = <&L2A>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "ref_clk_src", "ref_clk"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70 + 0x01 0xb0>; + qcom,rcal-mask = <0x1e00000>; + status = "disabled"; + }; + + /* Secondary USB port related QMP PHY */ + usb_qmp_phy: ssphy@88eb000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88eb000 0x1000>, + <0x088eb88c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&L5A>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L8C>; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, + <&dummycc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB3PHY_PHY_SEC_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + status = "disabled"; + }; +}; diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 24e1a3e9..9c37af5e 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -296,6 +296,7 @@ #include "sm8150-pinctrl.dtsi" #include "sa8155-vm-pcie.dtsi" #include "sa8155-vm-qupv3.dtsi" +#include "sa8155-vm-usb.dtsi" &tlmm { /delete-property/ wakeup-parent; From 4880b837d6da4c82c3d278b64256646c31a647ec Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Thu, 27 Oct 2022 11:18:33 +0530 Subject: [PATCH 10/41] ARM: dts: msm: update PCIe0 ultrashort chan settings for QRD Update PCie ultrashort channel settings for QRD platform Set PCIe RC0 deemphasis settings to 3.5DB, Fixed gain settings for Gen-2, update regiters to lock PLL at 38.4 MHZ refclk, Enables driving of the endpoint refclk before the PLL is locked on the exit of l1.1 and l1.2. Change-Id: Idd8e7461f4d5e9e9d96831930731eaccfd1e96d9 --- qcom/kalama-qrd.dtsi | 125 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 125 insertions(+) diff --git a/qcom/kalama-qrd.dtsi b/qcom/kalama-qrd.dtsi index 2a7d776c..400e9d0f 100644 --- a/qcom/kalama-qrd.dtsi +++ b/qcom/kalama-qrd.dtsi @@ -342,3 +342,128 @@ periph-d45-supply = <&L6N>; periph-d46-supply = <&L7N>; }; + +&pcie0 { + qcom,pcie-phy-ver = <101>; + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x00c0 0x01 0x0 + 0x00cc 0x62 0x0 + 0x00d0 0x02 0x0 + 0x0060 0xf8 0x0 + 0x0064 0x01 0x0 + 0x0000 0x93 0x0 + 0x0004 0x01 0x0 + 0x00e0 0x90 0x0 + 0x00e4 0x82 0x0 + 0x00f4 0x07 0x0 + 0x0070 0x02 0x0 + 0x0010 0x02 0x0 + 0x0074 0x16 0x0 + 0x0014 0x16 0x0 + 0x0078 0x36 0x0 + 0x0018 0x36 0x0 + 0x0110 0x08 0x0 + 0x00bc 0x0a 0x0 + 0x0120 0x42 0x0 + 0x0080 0x04 0x0 + 0x0084 0x0d 0x0 + 0x0020 0x0a 0x0 + 0x0024 0x1a 0x0 + 0x0088 0x41 0x0 + 0x0028 0x34 0x0 + 0x0090 0xab 0x0 + 0x0094 0xaa 0x0 + 0x0098 0x01 0x0 + 0x0030 0x55 0x0 + 0x0034 0x55 0x0 + 0x0038 0x01 0x0 + 0x0140 0x14 0x0 + 0x0164 0x34 0x0 + 0x003c 0x01 0x0 + 0x001c 0x04 0x0 + 0x0174 0x16 0x0 + 0x01bc 0x0f 0x0 + 0x0170 0xa0 0x0 + 0x11a4 0x38 0x0 + 0x10dc 0x11 0x0 + 0x1160 0xbf 0x0 + 0x1164 0xbf 0x0 + 0x1168 0xb7 0x0 + 0x116c 0xea 0x0 + 0x115c 0x3f 0x0 + 0x1174 0x5c 0x0 + 0x1178 0x9c 0x0 + 0x117c 0x1a 0x0 + 0x1180 0x89 0x0 + 0x1170 0xdc 0x0 + 0x1188 0x94 0x0 + 0x118c 0x5b 0x0 + 0x1190 0x1a 0x0 + 0x1194 0x89 0x0 + 0x10cc 0x00 0x0 + 0x1008 0x09 0x0 + 0x1014 0x05 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x10d8 0x0f 0x0 + 0x1118 0x1c 0x0 + 0x10f8 0x07 0x0 + 0x11f8 0x08 0x0 + 0x0e84 0x15 0x0 + 0x0e90 0x3f 0x0 + 0x0ee4 0x02 0x0 + 0x0e40 0x06 0x0 + 0x0e3c 0x18 0x0 + 0x19a4 0x38 0x0 + 0x18dc 0x11 0x0 + 0x1960 0xbf 0x0 + 0x1964 0xbf 0x0 + 0x1968 0xb7 0x0 + 0x196c 0xea 0x0 + 0x195c 0x3f 0x0 + 0x1974 0x5c 0x0 + 0x1978 0x9c 0x0 + 0x197c 0x1a 0x0 + 0x1980 0x89 0x0 + 0x1970 0xdc 0x0 + 0x1988 0x94 0x0 + 0x198c 0x5b 0x0 + 0x1990 0x1a 0x0 + 0x1994 0x89 0x0 + 0x18cc 0x00 0x0 + 0x1808 0x09 0x0 + 0x1814 0x05 0x0 + 0x184c 0x08 0x0 + 0x1850 0x08 0x0 + 0x18d8 0x0f 0x0 + 0x1918 0x1c 0x0 + 0x18f8 0x07 0x0 + 0x19f8 0x08 0x0 + 0x1684 0x15 0x0 + 0x1690 0x3f 0x0 + 0x16e4 0x02 0x0 + 0x1640 0x06 0x0 + 0x163c 0x18 0x0 + 0x02dc 0x05 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x06a4 0x1e 0x0 + 0x03e0 0x0f 0x0 + 0x060c 0x1d 0x0 + 0x0614 0x07 0x0 + 0x0620 0xc1 0x0 + 0x0368 0x0F 0x0 + 0x1180 0x8C 0x0 + 0x1980 0x8C 0x0 + 0x0120 0x40 0x0 + 0x0080 0x0A 0x0 + 0x0084 0x1A 0x0 + 0x0020 0x14 0x0 + 0x0024 0x34 0x0 + 0x0624 0x05 0x0 + 0x0694 0x00 0x0 + 0x03d0 0x8c 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + +}; From dd21e196faa3cb8f881a1135e1e83633595d9730 Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Sun, 30 Oct 2022 22:40:11 -0700 Subject: [PATCH 11/41] ARM: dts: msm: Correct gpii-mask for sdxpinn This change will correct gpii mask property for sdxpinn Change-Id: Iba2ba0a73924cf6eca46e1c78404c9ea1c259898 --- qcom/sdxpinn-qupv3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxpinn-qupv3.dtsi b/qcom/sdxpinn-qupv3.dtsi index 6b5d3a59..42f01f18 100644 --- a/qcom/sdxpinn-qupv3.dtsi +++ b/qcom/sdxpinn-qupv3.dtsi @@ -31,7 +31,7 @@ , , ; - qcom,gpii-mask = <0xfff>; + qcom,gpii-mask = <0x7f>; qcom,ev-factor = <2>; qcom,iommu-dma-addr-pool = <0x100000 0x100000>; qcom,gpi-ee-offset = <0x10000>; From b2fd6db23b7fe072d8ab8c9e8289e374bfb59a52 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Mon, 31 Oct 2022 11:46:20 +0530 Subject: [PATCH 12/41] ARM: dts: msm: skip qos for lemans skip qos configuration for lemans. Change-Id: I0a2412f6fd8fdb6fd5da8f211c86b34df9c800a1 --- qcom/lemans.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index 8953fc9c..3957ec67 100644 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -908,6 +908,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; }; mc_virt: interconnect@1 { @@ -915,6 +916,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; }; config_noc: interconnect@014C0000 { @@ -923,6 +925,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; }; system_noc: interconnect@01680000 { @@ -931,6 +934,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; }; aggre1_noc:interconnect@016C0000 { @@ -939,6 +943,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, @@ -952,6 +957,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, <&rpmhcc RPMH_IPA_CLK>; }; @@ -962,6 +968,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; }; gpdsp_anoc: interconnect@01780000 { @@ -970,6 +977,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; }; mmss_noc: interconnect@017A0000 { @@ -978,6 +986,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; }; lpass_ag_noc: interconnect@03C40000 { @@ -986,6 +995,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; }; dc_noc: interconnect@090E0000 { @@ -994,6 +1004,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; }; gem_noc: interconnect@09100000 { @@ -1003,6 +1014,7 @@ qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>; + qcom,skip-qos; }; nspa_noc: interconnect@260C0000 { @@ -1011,6 +1023,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; }; nspb_noc: interconnect@2A0C0000 { @@ -1019,6 +1032,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; }; vendor_hooks: qcom,cpu-vendor-hooks { From 7f900741d30be7e9e7d72a71c3664939a3c0274d Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Wed, 26 Oct 2022 18:45:15 +0530 Subject: [PATCH 13/41] ARM: dts: msm: Add support for CPUFREQ and DEBUGCC nodes for sdxbaagha Add support for CPUFREQ and DEBUGCC nodes for sdxbaagha platform. Change-Id: I2095387299ab9917c1578f536d652277ace6b545 --- qcom/sdxbaagha-rumi.dtsi | 8 ++++++++ qcom/sdxbaagha.dtsi | 41 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/qcom/sdxbaagha-rumi.dtsi b/qcom/sdxbaagha-rumi.dtsi index e2f47e70..48ff6d67 100644 --- a/qcom/sdxbaagha-rumi.dtsi +++ b/qcom/sdxbaagha-rumi.dtsi @@ -55,3 +55,11 @@ dr_mode = "peripheral"; }; }; + +&debugcc { + clocks = <&bi_tcxo>, <&gcc 0>; +}; + +&cpufreq_hw { + clocks = <&bi_tcxo>, <&gcc GPLL0>; +}; diff --git a/qcom/sdxbaagha.dtsi b/qcom/sdxbaagha.dtsi index 06c8b5ee..071966bd 100644 --- a/qcom/sdxbaagha.dtsi +++ b/qcom/sdxbaagha.dtsi @@ -20,7 +20,7 @@ }; chosen { - bootargs = "pcie_ports=compat"; + bootargs = "pcie_ports=compat cpufreq.default_governor=performance"; }; memory { device_type = "memory"; reg = <0 0>; }; @@ -141,6 +141,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x0>; + qcom,freq-domain = <&cpufreq_hw 0>; }; }; @@ -441,6 +442,44 @@ #reset-cells = <1>; }; + apsscc: syscon@17011000 { + compatible = "syscon"; + reg = <0x17011000 0x20>; + }; + + mccc: syscon@190ba000 { + compatible = "syscon"; + reg = <0x190ba000 0x54>; + }; + + debugcc: clock-controller@0 { + compatible = "qcom,sdxbaagha-debugcc"; + qcom,gcc = <&gcc>; + qcom,mccc = <&mccc>; + qcom,apsscc = <&apsscc>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc 0>; + clock-names = "xo_clk_src", + "gcc"; + #clock-cells = <1>; + }; + + cpufreq_hw: qcom,cpufreq-hw { + compatible = "qcom,cpufreq-epss"; + reg = <0x17191000 0x1000>; + reg-names = "freq-domain0"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + interrupts = ; + interrupt-names = "dcvsh0_int"; + #freq-domain-cells = <1>; + }; + + qcom,cpufreq-hw-debug { + compatible = "qcom,cpufreq-hw-epss-debug"; + qcom,freq-hw-domain = <&cpufreq_hw 0>; + }; + /* GCC GDSCs */ gcc_emac0_gdsc: qcom,gdsc@f1004 { compatible = "qcom,gdsc"; From cb5ec52e63b0e1431af61f4c388b800d843cf894 Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Mon, 31 Oct 2022 11:43:16 +0530 Subject: [PATCH 14/41] ARM: dts: msm: Add VDD_MODEM_LEVEL for sdxbaagha stub regulator Add VDD_MODEM_LEVEL for stub regulator for sdxbaagha. Change-Id: Ie3da3d9f89c206884650eb4665cf161a86eb7401 --- qcom/sdxbaagha-stub-regulator.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdxbaagha-stub-regulator.dtsi b/qcom/sdxbaagha-stub-regulator.dtsi index f2414dc5..0aea7fc7 100644 --- a/qcom/sdxbaagha-stub-regulator.dtsi +++ b/qcom/sdxbaagha-stub-regulator.dtsi @@ -1,6 +1,7 @@ #include / { + VDD_MODEM_LEVEL: VDD_CX_LEVEL: S1A_LEVEL: pmx35_s1_level: regulator-pmx35-s1-level { From b0f9ae6644cfc9b85301377cd638e89e545b532c Mon Sep 17 00:00:00 2001 From: Vishal Kulkarni Date: Tue, 1 Nov 2022 10:33:27 +0530 Subject: [PATCH 15/41] ARM: dts: msm: add hgsl to sa8155 vm for GPU doorbell hgsl device is for GPU doorbell feature which allows GVM to submit commands to GPU directly. Change-Id: Ib05082e80b411e02d62beb07ee83f7c684db06b4 --- bindings/soc/qcom/hgsl-tcsr.txt | 31 +++++++++++++++++ bindings/soc/qcom/hgsl.txt | 32 +++++++++++++++++ qcom/sa8155-vm.dtsi | 61 +++++++++++++++++++++++++++++++++ 3 files changed, 124 insertions(+) create mode 100644 bindings/soc/qcom/hgsl-tcsr.txt create mode 100644 bindings/soc/qcom/hgsl.txt diff --git a/bindings/soc/qcom/hgsl-tcsr.txt b/bindings/soc/qcom/hgsl-tcsr.txt new file mode 100644 index 00000000..80e237de --- /dev/null +++ b/bindings/soc/qcom/hgsl-tcsr.txt @@ -0,0 +1,31 @@ +Top Control and Status Register(TCSR) for HGSL + +TCSR hardware contains compute signal sub-block, which allows drivers in hypervisor +Linux to communicate with GPU hardware directly. This HGSL TCSR driver is to enable +the TCSR compute signal hardware. There are multiple instances of compute signal. +Each instance is either a signal sender or signal receiver. + +The HGSL TCSR driver is built on top of generic TCSR driver, refer to +Documentation/devicetree/bindings/mfd/qcom,tcsr.txt for the generic TCSR driver. + +Required properties: +- compatible : Must be "qcom,hgsl-tcsr-sender" or "qcom,hgsl-tcsr-receiver" +- syscon : Point to the generic TCSR compute signal node +- syscon-glb : Point to the generice TCSR node for compute signal global control. + This is only needed by signal sender. +- interrupts : Specify IRQ information used by the compute signal. + This is only needed by signal receiver. + +Examples: + hgsl_tcsr_sender0: hgsl_tcsr_sender0 { + compatible = "qcom,hgsl-tcsr-sender"; + syscon = <&tcsr_compute_signal_sender0>; + syscon-glb = <&tcsr_compute_signal_glb>; + }; + + hgsl_tcsr_receiver0: hgsl_tcsr_receiver0 { + compatible = "qcom,hgsl-tcsr-receiver"; + syscon = <&tcsr_compute_signal_receiver0>; + interrupts = <0 238 0>; + }; + diff --git a/bindings/soc/qcom/hgsl.txt b/bindings/soc/qcom/hgsl.txt new file mode 100644 index 00000000..cbbed4be --- /dev/null +++ b/bindings/soc/qcom/hgsl.txt @@ -0,0 +1,32 @@ +* HGSL + +HGSL(Hypervisor Graphics system layer) is graphics driver under the hypervisor system. + +Required properties: +- compatible : Must be "qcom,hgsl" + +- reg : physical base address and length of the register set(s). + +- reg-names : names corresponding to each reg property value. + reg_hwver: HW version registers + reg_doorbell_idx: address of GMUAO_DOORBELL_IDX + +Optional properties: +- db-off: Disable Doorbell feature but keep hgsl for ifence service +- qcom,glb-db-senders : Point to possible nodes of HGSL TCSR sender. The user will select + which sender to use. The driver will use TCSR compute signal to + send signal to GPU. +- qcom,glb-db-receivers : Point to possible nodes of HGSL TCSR receiver. The user will + select which receiver to use. The driver will use TCSR compute + signal to receive signal from GPU. + +Example: + msm_gpu_hyp { + compatible = "qcom,hgsl"; + reg = <0x2c00000 0x8>, <0x2c8f000 0x4>; + reg-names = "hgsl_reg_hwinf", "hgsl_reg_gmucx"; + + db-off = <0>; + qcom,glb-db-senders = <&hgsl_tcsr_sender0 &hgsl_tcsr_sender1>; + qcom,glb-db-receivers = <&hgsl_tcsr_receiver0 &hgsl_tcsr_receiver1>; + }; diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 9c37af5e..b3c4047a 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -412,3 +412,64 @@ &qupv3_se12_2uart { status = "disabled"; }; +&soc { + tcsr_compute_signal_glb: syscon@0x1fd8000 { + compatible = "syscon"; + reg = <0x1fd8000 0x1000>; + }; + + tcsr_compute_signal_sender0: syscon@0x1fd9000 { + compatible = "syscon"; + reg = <0x1fd9000 0x1000>; + }; + + tcsr_compute_signal_sender1: syscon@0x1fdd000 { + compatible = "syscon"; + reg = <0x1fdd000 0x1000>; + }; + + tcsr_compute_signal_receiver0: syscon@0x1fdb000 { + compatible = "syscon"; + reg = <0x1fdb000 0x1000>; + }; + + tcsr_compute_signal_receiver1: syscon@0x1fdf000 { + compatible = "syscon"; + reg = <0x1fdf000 0x1000>; + }; + + hgsl_tcsr_sender0: hgsl_tcsr_sender0 { + compatible = "qcom,hgsl-tcsr-sender"; + syscon = <&tcsr_compute_signal_sender0>; + syscon-glb = <&tcsr_compute_signal_glb>; + }; + + hgsl_tcsr_sender1: hgsl_tcsr_sender1 { + compatible = "qcom,hgsl-tcsr-sender"; + syscon = <&tcsr_compute_signal_sender1>; + syscon-glb = <&tcsr_compute_signal_glb>; + }; + + hgsl_tcsr_receiver0: hgsl_tcsr_receiver0 { + compatible = "qcom,hgsl-tcsr-receiver"; + syscon = <&tcsr_compute_signal_receiver0>; + interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>; + }; + + hgsl_tcsr_receiver1: hgsl_tcsr_receiver1 { + compatible = "qcom,hgsl-tcsr-receiver"; + syscon = <&tcsr_compute_signal_receiver1>; + interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>; + }; + + msm_gpu_hyp: qcom,hgsl@0x2c00000 { + compatible = "qcom,hgsl"; + reg = <0x2c00000 0x8>, <0x2c8f000 0x4>; + reg-names = "hgsl_reg_hwinf", "hgsl_reg_gmucx"; + + qcom,glb-db-senders = <&hgsl_tcsr_sender0 + &hgsl_tcsr_sender1>; + qcom,glb-db-receivers = <&hgsl_tcsr_receiver0 + &hgsl_tcsr_receiver1>; + }; +}; From 06c9b07586d79462a84ed06c85cd572d662845ff Mon Sep 17 00:00:00 2001 From: Sai Srujana Oruganti Date: Tue, 18 Oct 2022 15:15:11 +0530 Subject: [PATCH 16/41] ARM: dts: msm: add display heap region for monaco This change adds display heap region for monaco target Change-Id: I4fbb304781c8cb8b7d086c14e1c137c88f49524a --- qcom/monaco-dma-heaps.dtsi | 7 +++++++ qcom/monaco.dtsi | 8 ++++++++ 2 files changed, 15 insertions(+) diff --git a/qcom/monaco-dma-heaps.dtsi b/qcom/monaco-dma-heaps.dtsi index 8c12959c..9349d675 100644 --- a/qcom/monaco-dma-heaps.dtsi +++ b/qcom/monaco-dma-heaps.dtsi @@ -21,5 +21,12 @@ qcom,dma-heap-type = ; memory-region = <&user_contig_mem>; }; + + qcom,display { + qcom,dma-heap-name = "qcom,display"; + qcom,dma-heap-type = ; + qcom,max-align = <9>; + memory-region = <&non_secure_display_memory>; + }; }; }; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 9e1c2765..31a9bd9b 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -273,6 +273,14 @@ status = "disabled"; }; + non_secure_display_memory: non_secure_display_region { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + size = <0x0 0xa400000>; + alignment = <0x0 0x400000>; + }; + splash_memory: splash_region@5c000000 { reg = <0x0 0x5c000000 0x0 0x00f00000>; label = "cont_splash_region"; From e31e16e47eed89cea9d6719384bc1426e64ff7e7 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Wed, 2 Nov 2022 10:01:27 +0530 Subject: [PATCH 17/41] ARM: dts: msm: Update gpio function name in pinctrl Update all SEs gpio function names to match the pinctrl driver. Previously, the function's name matched IPCAT. pinctrl driver is using older name as per 5.4 kernel. Change-Id: I6950ffa3a08ef6d8f794e1e7a6d77797528a87e6 --- qcom/monaco-pinctrl.dtsi | 98 ++++++++++++++++++++-------------------- qcom/monaco-qupv3.dtsi | 2 +- 2 files changed, 50 insertions(+), 50 deletions(-) diff --git a/qcom/monaco-pinctrl.dtsi b/qcom/monaco-pinctrl.dtsi index 58b6ad67..dcc209d5 100644 --- a/qcom/monaco-pinctrl.dtsi +++ b/qcom/monaco-pinctrl.dtsi @@ -13,7 +13,7 @@ qupv3_se6_2uart_tx_active: qupv3_se6_2uart_tx_active { mux { pins = "gpio30"; - function = "qup0_l2"; + function = "qup06"; }; config { @@ -23,10 +23,10 @@ }; }; - qupv3_se3_2uart_rx_active: qupv3_se3_2uart_rx_active { + qupv3_se6_2uart_rx_active: qupv3_se6_2uart_rx_active { mux { pins = "gpio31"; - function = "qup0_l3"; + function = "qup06"; }; config { @@ -54,7 +54,7 @@ qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active { mux { pins = "gpio4"; - function = "qup0_l0"; + function = "qup00"; }; config { @@ -67,7 +67,7 @@ qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active { mux { pins = "gpio5"; - function = "qup0_l1"; + function = "qup00"; }; config { @@ -157,7 +157,7 @@ qupv3_se0_spi_miso_active: qupv3_se0_spi_miso_active { mux { pins = "gpio4"; - function = "qup0_l0"; + function = "qup00"; }; config { @@ -170,7 +170,7 @@ qupv3_se0_spi_mosi_active: qupv3_se0_spi_mosi_active { mux { pins = "gpio5"; - function = "qup0_l1"; + function = "qup00"; }; config { @@ -183,7 +183,7 @@ qupv3_se0_spi_clk_active: qupv3_se0_spi_clk_active { mux { pins = "gpio6"; - function = "qup0_l2"; + function = "qup00"; }; config { @@ -196,7 +196,7 @@ qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active { mux { pins = "gpio7"; - function = "qup0_l3"; + function = "qup00"; }; config { @@ -226,7 +226,7 @@ qupv3_se1_i2c_sda_active: qupv3_se1_i2c_sda_active { mux { pins = "gpio10"; - function = "qup0_l0"; + function = "qup01"; }; config { @@ -239,7 +239,7 @@ qupv3_se1_i2c_scl_active: qupv3_se1_i2c_scl_active { mux { pins = "gpio11"; - function = "qup0_l1"; + function = "qup01"; }; config { @@ -267,7 +267,7 @@ qupv3_se1_spi_miso_active: qupv3_se1_spi_miso_active { mux { pins = "gpio10"; - function = "qup0_l0"; + function = "qup01"; }; config { @@ -280,7 +280,7 @@ qupv3_se1_spi_mosi_active: qupv3_se1_spi_mosi_active { mux { pins = "gpio11"; - function = "qup0_l1"; + function = "qup01"; }; config { @@ -293,7 +293,7 @@ qupv3_se1_spi_clk_active: qupv3_se1_spi_clk_active { mux { pins = "gpio12"; - function = "qup0_l2"; + function = "qup01"; }; config { @@ -306,7 +306,7 @@ qupv3_se1_spi_cs_active: qupv3_se1_spi_cs_active { mux { pins = "gpio13"; - function = "qup0_l3"; + function = "qup01"; }; config { @@ -336,7 +336,7 @@ qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active { mux { pins = "gpio0"; - function = "qup0_l0"; + function = "qup02"; }; config { @@ -349,7 +349,7 @@ qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active { mux { pins = "gpio1"; - function = "qup0_l1"; + function = "qup02"; }; config { @@ -377,7 +377,7 @@ qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active { mux { pins = "gpio0"; - function = "qup0_l0"; + function = "qup02"; }; config { @@ -390,7 +390,7 @@ qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active { mux { pins = "gpio1"; - function = "qup0_l1"; + function = "qup02"; }; config { @@ -403,7 +403,7 @@ qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active { mux { pins = "gpio2"; - function = "qup0_l2"; + function = "qup02"; }; config { @@ -416,7 +416,7 @@ qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active { mux { pins = "gpio3"; - function = "qup0_l3"; + function = "qup02"; }; config { @@ -446,7 +446,7 @@ qupv3_se3_i2c_sda_active: qupv3_se3_i2c_sda_active { mux { pins = "gpio14"; - function = "qup0_l0"; + function = "qup03"; }; config { @@ -459,7 +459,7 @@ qupv3_se3_i2c_scl_active: qupv3_se3_i2c_scl_active { mux { pins = "gpio15"; - function = "qup0_l1"; + function = "qup03"; }; config { @@ -487,7 +487,7 @@ qupv3_se3_spi_miso_active: qupv3_se3_spi_miso_active { mux { pins = "gpio14"; - function = "qup0_l0"; + function = "qup03"; }; config { @@ -500,7 +500,7 @@ qupv3_se3_spi_mosi_active: qupv3_se3_spi_mosi_active { mux { pins = "gpio15"; - function = "qup0_l1"; + function = "qup03"; }; config { @@ -513,7 +513,7 @@ qupv3_se3_spi_clk_active: qupv3_se3_spi_clk_active { mux { pins = "gpio16"; - function = "qup0_l2"; + function = "qup03"; }; config { @@ -526,7 +526,7 @@ qupv3_se3_spi_cs_active: qupv3_se3_spi_cs_active { mux { pins = "gpio17"; - function = "qup0_l3"; + function = "qup03"; }; config { @@ -556,7 +556,7 @@ qupv3_se4_i2c_sda_active: qupv3_se4_i2c_sda_active { mux { pins = "gpio20"; - function = "qup0_l0"; + function = "qup04"; }; config { @@ -569,7 +569,7 @@ qupv3_se4_i2c_scl_active: qupv3_se4_i2c_scl_active { mux { pins = "gpio21"; - function = "qup0_l1"; + function = "qup04"; }; config { @@ -597,7 +597,7 @@ qupv3_se4_spi_miso_active: qupv3_se4_spi_miso_active { mux { pins = "gpio20"; - function = "qup0_l0"; + function = "qup04"; }; config { @@ -610,7 +610,7 @@ qupv3_se4_spi_mosi_active: qupv3_se4_spi_mosi_active { mux { pins = "gpio21"; - function = "qup0_l1"; + function = "qup04"; }; config { @@ -623,7 +623,7 @@ qupv3_se4_spi_clk_active: qupv3_se4_spi_clk_active { mux { pins = "gpio22"; - function = "qup0_l2"; + function = "qup04"; }; config { @@ -636,7 +636,7 @@ qupv3_se4_spi_cs_active: qupv3_se4_spi_cs_active { mux { pins = "gpio23"; - function = "qup0_l3"; + function = "qup04"; }; config { @@ -666,7 +666,7 @@ qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active { mux { pins = "gpio26"; - function = "qup0_l0"; + function = "qup05"; }; config { @@ -679,7 +679,7 @@ qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active { mux { pins = "gpio27"; - function = "qup0_l1"; + function = "qup05"; }; config { @@ -707,7 +707,7 @@ qupv3_se5_spi_miso_active: qupv3_se5_spi_miso_active { mux { pins = "gpio26"; - function = "qup0_l0"; + function = "qup05"; }; config { @@ -720,7 +720,7 @@ qupv3_se5_spi_mosi_active: qupv3_se5_spi_mosi_active { mux { pins = "gpio27"; - function = "qup0_l1"; + function = "qup05"; }; config { @@ -733,7 +733,7 @@ qupv3_se5_spi_clk_active: qupv3_se5_spi_clk_active { mux { pins = "gpio28"; - function = "qup0_l2"; + function = "qup05"; }; config { @@ -746,7 +746,7 @@ qupv3_se5_spi_cs_active: qupv3_se5_spi_cs_active { mux { pins = "gpio29"; - function = "qup0_l3"; + function = "qup05"; }; config { @@ -776,7 +776,7 @@ qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active { mux { pins = "gpio24"; - function = "qup0_10"; + function = "qup06"; }; config { @@ -789,7 +789,7 @@ qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active { mux { pins = "gpio25"; - function = "qup0_11"; + function = "qup06"; }; config { @@ -817,7 +817,7 @@ qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active { mux { pins = "gpio24"; - function = "qup0_l0"; + function = "qup06"; }; config { @@ -830,7 +830,7 @@ qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active { mux { pins = "gpio25"; - function = "qup0_l1"; + function = "qup06"; }; config { @@ -843,7 +843,7 @@ qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active { mux { pins = "gpio30"; - function = "qup0_l2"; + function = "qup06"; }; config { @@ -856,7 +856,7 @@ qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active { mux { pins = "gpio31"; - function = "qup0_l3"; + function = "qup06"; }; config { @@ -1158,7 +1158,7 @@ qupv3_se5_cts: qupv3_se5_cts { mux { pins = "gpio26"; - function = "qup0_l0"; + function = "qup05"; }; config { @@ -1171,7 +1171,7 @@ qupv3_se5_rts: qupv3_se5_rts { mux { pins = "gpio27"; - function = "qup0_l1"; + function = "qup05"; }; config { @@ -1184,7 +1184,7 @@ qupv3_se5_tx: qupv3_se5_tx { mux { pins = "gpio28"; - function = "qup0_l2"; + function = "qup05"; }; config { @@ -1197,7 +1197,7 @@ qupv3_se5_rx: qupv3_se5_rx { mux { pins = "gpio29"; - function = "qup0_l3"; + function = "qup05"; }; config { diff --git a/qcom/monaco-qupv3.dtsi b/qcom/monaco-qupv3.dtsi index 4abcfea1..3d51f4ba 100644 --- a/qcom/monaco-qupv3.dtsi +++ b/qcom/monaco-qupv3.dtsi @@ -69,7 +69,7 @@ <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se6_2uart_tx_active>, <&qupv3_se3_2uart_rx_active>; + pinctrl-0 = <&qupv3_se6_2uart_tx_active>, <&qupv3_se6_2uart_rx_active>; pinctrl-1 = <&qupv3_se6_2uart_sleep>; status = "disabled"; }; From b49260b7bcf3eaa275e3c86a993bceb509214814 Mon Sep 17 00:00:00 2001 From: Yadu MG Date: Wed, 2 Nov 2022 04:14:07 +0530 Subject: [PATCH 18/41] dt-bindings: Add documentation for ADSP remoteproc Add Documentation for ADSP remote processor for Lemans target. Change-Id: I02fc46a4c72835501b0f9dbe8c30b69c0ad86302 --- bindings/remoteproc/qcom,adsp.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/remoteproc/qcom,adsp.txt b/bindings/remoteproc/qcom,adsp.txt index 3200fdb2..eabcba09 100644 --- a/bindings/remoteproc/qcom,adsp.txt +++ b/bindings/remoteproc/qcom,adsp.txt @@ -47,6 +47,7 @@ on the Qualcomm Technologies inc ADSP Hexagon core. "qcom,monaco-adsp-pas" "qcom,monaco-modem-pas" "qcom,sdxpinn-modem-pas" + "qcom,lemans-adsp-pas" - interrupts-extended: Usage: required From 600df4d11418a66d563a1132b641efe10051b8f4 Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Wed, 2 Nov 2022 15:23:02 +0800 Subject: [PATCH 19/41] ARM: dts: msm: update to correct regulator which kalama + baagha target used Update to correct regulator which kalama + baagha target used. Change-Id: I20a58be9aec6922ffcaf3cec547827adee0d0544 --- qcom/sdxbaagha-external-soc.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxbaagha-external-soc.dtsi b/qcom/sdxbaagha-external-soc.dtsi index 731d27c6..00fbebde 100644 --- a/qcom/sdxbaagha-external-soc.dtsi +++ b/qcom/sdxbaagha-external-soc.dtsi @@ -31,8 +31,8 @@ qcom,ap2mdm-soft-reset-gpio = <&pm8550_gpios 1 0>; reg-names = "l10b"; - l10c-supply = <&L10B>; - l10c-uV-uA = <1200000 100000>; + l10b-supply = <&L10B>; + l10b-uV-uA = <1200000 100000>; qcom,esoc-skip-restart-for-mdm-crash; status = "ok"; From 69d3d5c795c2526d0f4f858cbf58d7f697fe5257 Mon Sep 17 00:00:00 2001 From: Akhil Vinod Date: Tue, 1 Nov 2022 16:53:05 +0530 Subject: [PATCH 20/41] ARM: dts: msm: Update PCIe PHY settings for cinder Updated phy settings as per HSR v1.01. Change-Id: I30e27a9015d19d18a9d6a0a6d4272313b380eac4 --- qcom/cinder.dtsi | 100 ++++++++++++++++++++++++++++------------------- 1 file changed, 59 insertions(+), 41 deletions(-) diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi index d45ac646..4b1999e4 100644 --- a/qcom/cinder.dtsi +++ b/qcom/cinder.dtsi @@ -1323,14 +1323,16 @@ qcom,sriov-mask = <0x1E0>; qcom,phy-init = <0x9040 0x01 0x0 + 0x8030 0x0a 0x0 + 0x80b4 0x88 0x0 0x80c4 0x00 0x0 0x80c8 0x1f 0x0 - 0x80d4 0x12 0x0 - 0x80d8 0x1a 0x0 - 0x80dc 0xba 0x0 - 0x80e0 0x8a 0x0 + 0x80d4 0x93 0x0 + 0x80d8 0xda 0x0 + 0x80dc 0xf1 0x0 + 0x80e0 0xca 0x0 0x80e4 0x8b 0x0 - 0x80e8 0x82 0x0 + 0x80e8 0x81 0x0 0x80ec 0x65 0x0 0x80f0 0x1f 0x0 0x80f4 0x1f 0x0 @@ -1344,13 +1346,14 @@ 0x880c 0x02 0x0 0x8844 0x1c 0x0 0x884c 0x07 0x0 - 0x8858 0x0f 0x0 - 0x8874 0x28 0x0 - 0x8878 0x28 0x0 - 0x887c 0x0d 0x0 - 0x8880 0x0d 0x0 + 0x8858 0x1f 0x0 + 0x8860 0x10 0x0 + 0x8874 0x27 0x0 + 0x8878 0x0a 0x0 + 0x887c 0x17 0x0 + 0x8880 0x19 0x0 0x8884 0x00 0x0 - 0x8888 0x00 0x0 + 0x8888 0x03 0x0 0x8894 0x00 0x0 0x88a4 0x46 0x0 0x88a8 0x04 0x0 @@ -1358,64 +1361,79 @@ 0x88b0 0x04 0x0 0x88b4 0xff 0x0 0x88b8 0x04 0x0 - 0x88bc 0x32 0x0 + 0x88bc 0x19 0x0 0x88c4 0x28 0x0 0x88ec 0xfb 0x0 0x88f0 0x03 0x0 0x88f4 0xfb 0x0 - 0x88f8 0x03 0x0 + 0x88f8 0x01 0x0 0x890c 0x02 0x0 - 0x8958 0x13 0x0 + 0x8958 0x12 0x0 0x895c 0x00 0x0 0x8968 0x0a 0x0 0x896c 0x08 0x0 0x8974 0x20 0x0 - 0x897c 0x16 0x0 + 0x897c 0x06 0x0 0x899c 0x88 0x0 0x89a0 0x14 0x0 0x89a8 0x0f 0x0 0x917c 0x2e 0x0 - 0x9194 0x66 0x0 + 0x9194 0x00 0x0 0x91bc 0x11 0x0 - 0x91f8 0x16 0x0 + 0x91f8 0x00 0x0 0x91fc 0x22 0x0 0x9858 0x02 0x0 0x988c 0x08 0x0 0x98a8 0x16 0x0 + 0x98ac 0x6b 0x0 0x9910 0x02 0x0 0x9964 0x2e 0x0 0x9984 0x03 0x0 0x998c 0x28 0x0 - 0x999c 0x03 0x0 - 0xe030 0x00 0x0 - 0xe034 0x00 0x0 + 0x999c 0x1f 0x0 + 0x90c8 0xff 0x0 + 0x90cc 0x8f 0x0 + 0x91c4 0x00 0x0 + 0x91c8 0x80 0x0 + 0xe030 0x1d 0x0 + 0xe034 0x0a 0x0 0xe078 0x01 0x0 - 0xe07c 0x80 0x0 - 0xe080 0x50 0x0 - 0xe208 0x0a 0x0 - 0xe20c 0x0a 0x0 + 0xe07c 0x00 0x0 + 0xe080 0x70 0x0 + 0xe208 0x0c 0x0 + 0xe20c 0x08 0x0 + 0xe218 0x04 0x0 + 0xe21c 0x05 0x0 0xe220 0x16 0x0 0xe234 0x00 0x0 - 0xe2b4 0x05 0x0 - 0xe2e8 0x0a 0x0 - 0xe30c 0x0d 0x0 + 0xe2a0 0x00 0x0 + 0xe2b0 0x00 0x0 + 0xe2b4 0x45 0x0 + 0xe2e0 0x00 0x0 + 0xe2e8 0x03 0x0 + 0xe2f4 0x30 0x0 + 0xe30c 0x09 0x0 0xe320 0x0b 0x0 - 0xe348 0x1c 0x0 + 0xe33c 0x7c 0x0 + 0xe348 0xdc 0x0 + 0xe34c 0x03 0x0 + 0xe354 0x14 0x0 0xe388 0x20 0x0 0xe394 0x38 0x0 - 0xe3f4 0x12 0x0 - 0xe3f8 0x1a 0x0 - 0xe3fc 0xba 0x0 - 0xe400 0xca 0x0 - 0xe404 0x8b 0x0 - 0xe408 0x82 0x0 - 0xe40c 0xef 0x0 - 0xe410 0x2c 0x0 - 0xe414 0x5b 0x0 - 0xe418 0x7c 0x0 - 0xe41c 0xeb 0x0 - 0xe420 0x4b 0x0 - 0xe424 0x86 0x0 + 0xe3dc 0x07 0x0 + 0xe3f4 0x9c 0x0 + 0xe3f8 0x1b 0x0 + 0xe3fc 0x3a 0x0 + 0xe400 0xe3 0x0 + 0xe404 0xbf 0x0 + 0xe408 0x03 0x0 + 0xe40c 0x8d 0x0 + 0xe410 0x9b 0x0 + 0xe414 0x1b 0x0 + 0xe418 0x2d 0x0 + 0xe41c 0xc7 0x0 + 0xe420 0x5f 0x0 + 0xe424 0x6e 0x0 0xe428 0xff 0x0 0x9000 0x00 0x0 0x9044 0x03 0x0>; From 8c9e75a5b2b2acd50488610cb42c0e30864e00bb Mon Sep 17 00:00:00 2001 From: Yadu MG Date: Wed, 2 Nov 2022 12:55:19 +0530 Subject: [PATCH 21/41] dt-bindings: Add documentation for CDSP remoteproc's Add Documentation for CDSP remote processors for Lemans target. Change-Id: I9392aa3cb556a7ab2afc0e01328926f967772a53 --- bindings/remoteproc/qcom,adsp.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/remoteproc/qcom,adsp.txt b/bindings/remoteproc/qcom,adsp.txt index eabcba09..51291b02 100644 --- a/bindings/remoteproc/qcom,adsp.txt +++ b/bindings/remoteproc/qcom,adsp.txt @@ -48,6 +48,8 @@ on the Qualcomm Technologies inc ADSP Hexagon core. "qcom,monaco-modem-pas" "qcom,sdxpinn-modem-pas" "qcom,lemans-adsp-pas" + "qcom,lemans-cdsp-pas" + "qcom,lemans-cdsp1-pas" - interrupts-extended: Usage: required From 05b77656ab968b229bff01a6faa5fb400bcc33df Mon Sep 17 00:00:00 2001 From: Yadu MG Date: Wed, 2 Nov 2022 12:56:55 +0530 Subject: [PATCH 22/41] dt-bindings: Add documentation for GPDSP remoteproc's Add Documentation for GPDSP remote processors for Lemans target. Change-Id: I7cfff191fe2209d7205cad9a9e9b9fdd6bbdcb91 --- bindings/remoteproc/qcom,adsp.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/remoteproc/qcom,adsp.txt b/bindings/remoteproc/qcom,adsp.txt index 51291b02..8d488c9c 100644 --- a/bindings/remoteproc/qcom,adsp.txt +++ b/bindings/remoteproc/qcom,adsp.txt @@ -50,6 +50,8 @@ on the Qualcomm Technologies inc ADSP Hexagon core. "qcom,lemans-adsp-pas" "qcom,lemans-cdsp-pas" "qcom,lemans-cdsp1-pas" + "qcom,lemans-gpdsp0-pas" + "qcom,lemans-gpdsp1-pas" - interrupts-extended: Usage: required From 72f1a82c38ecffa94ba58f8eee6e3ba1348dd587 Mon Sep 17 00:00:00 2001 From: Anjana Hari Date: Wed, 2 Nov 2022 15:08:38 +0530 Subject: [PATCH 23/41] ARM: dts: msm: Disable Write Booster support on SA8155 Disable Write Booster support on SA8155. Change-Id: I3fba1a97dbd74dabd9ef181922c3216fd552fa0d --- qcom/sa8155-adp-common.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi index e5923968..1f9c6a67 100644 --- a/qcom/sa8155-adp-common.dtsi +++ b/qcom/sa8155-adp-common.dtsi @@ -78,6 +78,9 @@ qcom,vddp-ref-clk-supply = <&pm8150_2_l5>; qcom,vddp-ref-clk-max-microamp = <100>; + /* Disable Write Booster Feature */ + qcom,disable-wb-support; + status = "ok"; }; From 8a4156934d966be39d58022c9fd71b061dcdcd00 Mon Sep 17 00:00:00 2001 From: Anjana Hari Date: Wed, 2 Nov 2022 15:19:21 +0530 Subject: [PATCH 24/41] ARM: dts: msm: Disable Write Booster support on SA8195p Disable Write Booster support on SA8195p. Change-Id: I996db750d6837855a56a34b3d93a76ac067af02e --- qcom/sa8195p.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index b40320fd..8ff30377 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -57,5 +57,8 @@ qcom,vccq-parent-supply = <&pm8195_1_s2>; qcom,vccq-parent-max-microamp = <210000>; + /* Disable Write Booster Feature */ + qcom,disable-wb-support; + status= "ok"; }; From 77df51256ca6dbd4f20e57814de9151b12631b67 Mon Sep 17 00:00:00 2001 From: Minghao Zhang Date: Wed, 2 Nov 2022 18:46:23 +0800 Subject: [PATCH 25/41] ARM: dts: qcom: Update cpu, gpu and usb-therm mitigation rules on Kalama HHG Update cpu, gpu and usb-therm mitigation rules based on the latest recommendation. Change-Id: I981fa2bb0dedc671b3ed90bf31b8ff7a2fa44b2d --- qcom/kalama-sg-hhg.dtsi | 104 +++++++++++++++++++++++++++++++++------- 1 file changed, 88 insertions(+), 16 deletions(-) diff --git a/qcom/kalama-sg-hhg.dtsi b/qcom/kalama-sg-hhg.dtsi index 42c9480c..6af80349 100644 --- a/qcom/kalama-sg-hhg.dtsi +++ b/qcom/kalama-sg-hhg.dtsi @@ -157,7 +157,7 @@ }; }; - cpu-1-6 { + cpu-1-9 { trips { thermal-engine-config { temperature = <125000>; @@ -171,22 +171,33 @@ type = "passive"; }; - fan_cpu16_config0: fan-cpu16-config0 { - temperature = <95000>; - hysteresis = <5000>; + fan_cpu19_config0: fan-cpu19-config0 { + temperature = <85000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_cpu19_config1: fan-cpu19-config1 { + temperature = <90000>; + hysteresis = <0>; type = "passive"; }; }; cooling-maps { fan_cdev_0 { - trip = <&fan_cpu16_config0>; - cooling-device = <&fancontroller 1 1>; + trip = <&fan_cpu19_config0>; + cooling-device = <&fancontroller 2 2>; + }; + + fan_cdev_1 { + trip = <&fan_cpu19_config1>; + cooling-device = <&fancontroller 3 3>; }; }; }; - cpu-1-7 { + cpu-1-10 { trips { thermal-engine-config { temperature = <125000>; @@ -200,17 +211,28 @@ type = "passive"; }; - fan_cpu17_config0: fan-cpu17-config0 { - temperature = <95000>; - hysteresis = <5000>; + fan_cpu1a_config0: fan-cpu1a-config0 { + temperature = <85000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_cpu1a_config1: fan-cpu1a-config1 { + temperature = <90000>; + hysteresis = <0>; type = "passive"; }; }; cooling-maps { fan_cdev_0 { - trip = <&fan_cpu17_config0>; - cooling-device = <&fancontroller 1 1>; + trip = <&fan_cpu1a_config0>; + cooling-device = <&fancontroller 2 2>; + }; + + fan_cdev_1 { + trip = <&fan_cpu1a_config1>; + cooling-device = <&fancontroller 3 3>; }; }; }; @@ -230,7 +252,13 @@ }; fan_gpuss0_config0: fan-gpuss0-config0 { - temperature = <95000>; + temperature = <70000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_gpuss0_config1: fan-gpuss0-config1 { + temperature = <90000>; hysteresis = <0>; type = "passive"; }; @@ -239,7 +267,12 @@ cooling-maps { fan_cdev_0 { trip = <&fan_gpuss0_config0>; - cooling-device = <&fancontroller 1 1>; + cooling-device = <&fancontroller 3 3>; + }; + + fan_cdev_1 { + trip = <&fan_gpuss0_config1>; + cooling-device = <&fancontroller 4 4>; }; }; }; @@ -259,7 +292,13 @@ }; fan_gpuss1_config0: fan-gpuss1-config0 { - temperature = <95000>; + temperature = <70000>; + hysteresis = <0>; + type = "passive"; + }; + + fan_gpuss1_config1: fan-gpuss1-config1 { + temperature = <90000>; hysteresis = <0>; type = "passive"; }; @@ -268,7 +307,40 @@ cooling-maps { fan_cdev_0 { trip = <&fan_gpuss1_config0>; - cooling-device = <&fancontroller 1 1>; + cooling-device = <&fancontroller 3 3>; + }; + + fan_cdev_1 { + trip = <&fan_gpuss1_config1>; + cooling-device = <&fancontroller 4 4>; + }; + }; + }; + + usb-therm { + trips { + fan_thmbat0_config0: fan-thmbat0-config0 { + temperature = <43000>; + hysteresis = <2000>; + type = "passive"; + }; + + fan_thmbat1_config1: fan-thmbat1-config1 { + temperature = <45000>; + hysteresis = <3000>; + type = "passive"; + }; + }; + + cooling-maps { + fan_cdev_0 { + trip = <&fan_thmbat0_config0>; + cooling-device = <&fancontroller 3 3>; + }; + + fan_cdev_1 { + trip = <&fan_thmbat1_config1>; + cooling-device = <&fancontroller 4 4>; }; }; }; From 638bf07124e2ba24e998598aa03e89f382386e41 Mon Sep 17 00:00:00 2001 From: Meenu Raja Sundaram Date: Fri, 22 Jul 2022 18:14:06 +0530 Subject: [PATCH 26/41] ARM: dts: msm: Add Mproc driver support for Lemans target Add below mproc modules support for Lemans target. 1. Glink 2. QRTR 3. QMP 4. SMEM 5. SMP2P 6. HW spinlock. Change-Id: If31802e5650f931ef78c948dfde76b6104168635 --- qcom/lemans.dtsi | 142 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 142 insertions(+) diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index 3957ec67..d69a1497 100644 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. Lemans"; @@ -1204,6 +1205,147 @@ vote = <44>; }; }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + aoss_qmp: power-controller@c300000 { + + compatible = "qcom,sm8150-aoss-qmp"; + reg = <0xc300000 0x400>; + mboxes = <&ipcc_mproc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "aop_qmp"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + #clock-cells = <0>; + #power-domain-cells = <1>; + }; + + qmp_aop: qcom,qmp-aop@c300000 { + compatible = "qcom,qmp-mbox"; + qcom,qmp = <&aoss_qmp>; + label = "aop"; + #mbox-cells = <1>; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-cdsp@1799000c { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-gpdsp0 { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_GPDSP0 + IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <17>; + + gpdsp0_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + gpdsp0_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-gpdsp1 { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_GPDSP1 + IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <18>; + + gpdsp1_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + gpdsp1_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; #include "lemans-4pmic-regulators.dtsi" From e55803940b2877f55d091ee54355569e847acbd7 Mon Sep 17 00:00:00 2001 From: Mao Jinlong Date: Wed, 2 Nov 2022 22:54:51 +0800 Subject: [PATCH 27/41] ARM: dts: msm: Correct names of swao tpdms for cinder Correct names of swao tpdms to match with other targets. Change-Id: Ifa2ce1e698587de51cf0772ccfc4c06fcdc7e0af --- qcom/cinder-coresight.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/cinder-coresight.dtsi b/qcom/cinder-coresight.dtsi index b3a41f4c..884bb3f2 100644 --- a/qcom/cinder-coresight.dtsi +++ b/qcom/cinder-coresight.dtsi @@ -28,7 +28,7 @@ reg-names = "tpdm-base"; atid = <71>; - coresight-name = "coresight-tpdm-swao_prio1"; + coresight-name = "coresight-tpdm-swao-prio-1"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -49,7 +49,7 @@ reg = <0x10b0b000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-tpdm-swao_prio2"; + coresight-name = "coresight-tpdm-swao-prio-2"; atid = <71>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -70,7 +70,7 @@ reg = <0x10b0c000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-tpdm-swao_prio3"; + coresight-name = "coresight-tpdm-swao-prio-3"; atid = <71>; clocks = <&aoss_qmp>; From d22501835b68a38b63be47cf8d68b96a8f6e93d7 Mon Sep 17 00:00:00 2001 From: Shilpa Suresh Date: Thu, 27 Oct 2022 16:49:25 +0530 Subject: [PATCH 28/41] ARM: dts: msm: Update ports, lpass path, cti, usb for Khaje -Update the compatible string and periphid details for all the cti nodes to comply with the 5.15 design. -Update all the port numbers to match with the registers -Update the audio etm and lpass tpdm paths to go via the static lpass funnel to funnel_qatb. -Add usb_bam_support to enable usb out_mode. Change-Id: Ic4afb2c0f2d305d3825154dbf81fc1ee30f9056e --- qcom/bengal-coresight.dtsi | 255 +++++++++++++++++++++---------------- 1 file changed, 144 insertions(+), 111 deletions(-) diff --git a/qcom/bengal-coresight.dtsi b/qcom/bengal-coresight.dtsi index 61bab206..2d0a921b 100644 --- a/qcom/bengal-coresight.dtsi +++ b/qcom/bengal-coresight.dtsi @@ -142,14 +142,16 @@ out-ports { port { - audio_etm0_out_funnel_qatb: endpoint { + audio_etm0_out_funnel_lpass_lpi: endpoint { remote-endpoint = - <&funnel_qatb_in_audio_etm0>; + <&funnel_lpass_lpi_in_audio_etm0>; }; }; }; }; + + snoc: snoc { compatible = "qcom,coresight-dummy"; @@ -174,9 +176,9 @@ out-ports { port { - tpdm_lpass_out_funnel_qatb: endpoint { + tpdm_lpass_out_funnel_lpass_lpi: endpoint { remote-endpoint = - <&funnel_qatb_in_tpdm_lpass>; + <&funnel_lpass_lpi_in_tpdm_lpass>; }; }; }; @@ -636,7 +638,7 @@ #address-cells = <1>; #size-cells = <0>; - port@1 { + port@0 { reg = <0>; funnel_apss0_in_etm0: endpoint { remote-endpoint = @@ -644,7 +646,7 @@ }; }; - port@2 { + port@1 { reg = <1>; funnel_apss0_in_etm1: endpoint { remote-endpoint = @@ -652,7 +654,7 @@ }; }; - port@3 { + port@2 { reg = <2>; funnel_apss0_in_etm2: endpoint { remote-endpoint = @@ -660,7 +662,7 @@ }; }; - port@4 { + port@3 { reg = <3>; funnel_apss0_in_etm3: endpoint { remote-endpoint = @@ -668,7 +670,7 @@ }; }; - port@5 { + port@4 { reg = <4>; funnel_apss0_in_etm4: endpoint { remote-endpoint = @@ -676,7 +678,7 @@ }; }; - port@6 { + port@5 { reg = <5>; funnel_apss0_in_etm5: endpoint { remote-endpoint = @@ -684,7 +686,7 @@ }; }; - port@7 { + port@6 { reg = <6>; funnel_apss0_in_etm6: endpoint { remote-endpoint = @@ -692,7 +694,7 @@ }; }; - port@8 { + port@7 { reg = <7>; funnel_apss0_in_etm7: endpoint { remote-endpoint = @@ -730,7 +732,7 @@ #address-cells = <1>; #size-cells = <0>; - port@1 { + port@0 { reg = <0>; tpda_actpm_in_tpdm_actpm: endpoint { remote-endpoint = @@ -769,7 +771,7 @@ #address-cells = <1>; #size-cells = <0>; - port@1 { + port@0 { reg = <0>; tpda_apss_in_tpdm_apss: endpoint { remote-endpoint = @@ -807,7 +809,7 @@ #address-cells = <1>; #size-cells = <0>; - port@1 { + port@0 { reg = <0>; tpda_llm_silver_in_tpdm_llm_silver: endpoint { remote-endpoint = @@ -843,7 +845,7 @@ #address-cells = <1>; #size-cells = <0>; - port@1 { + port@0 { reg = <0>; funnel_apss1_in_funnel_apss0: endpoint { remote-endpoint = @@ -907,7 +909,7 @@ #address-cells = <1>; #size-cells = <0>; - port@1 { + port@0 { reg = <0>; tpda_mapss_in_tpdm_mapss: endpoint { remote-endpoint = @@ -942,7 +944,7 @@ #address-cells = <1>; #size-cells = <0>; - port@1 { + port@0 { reg = <0>; funnel_gpu_in_tpdm_gpu: endpoint { remote-endpoint = @@ -987,7 +989,7 @@ #address-cells = <1>; #size-cells = <0>; - port@2 { + port@0 { reg = <0>; funnel_turing_in_tpdm_turing: endpoint { remote-endpoint = @@ -995,7 +997,7 @@ }; }; - port@3 { + port@1 { reg = <1>; funnel_turing_in_turing_etm0: endpoint { remote-endpoint = @@ -1043,7 +1045,7 @@ #address-cells = <1>; #size-cells = <0>; - port@1 { + port@0 { reg = <0>; tpda0_in_tpdm_dl_ct: endpoint { remote-endpoint = @@ -1051,7 +1053,7 @@ }; }; - port@2 { + port@1 { reg = <1>; tpda1_in_funnel_gpu: endpoint { remote-endpoint = @@ -1059,7 +1061,7 @@ }; }; - port@3 { + port@5 { reg = <5>; tpda5_in_funnel_turing: endpoint { remote-endpoint = @@ -1067,7 +1069,7 @@ }; }; - port@4 { + port@7 { reg = <7>; tpda7_in_tpdm_vsense: endpoint { remote-endpoint = @@ -1075,7 +1077,7 @@ }; }; - port@5 { + port@8 { reg = <8>; tpda8_in_tpdm_dcc: endpoint { remote-endpoint = @@ -1083,7 +1085,7 @@ }; }; - port@6 { + port@10 { reg = <10>; tpda10_in_tpdm_prng: endpoint { remote-endpoint = @@ -1091,7 +1093,7 @@ }; }; - port@7 { + port@12 { reg = <12>; tpda12_in_tpdm_qm: endpoint { remote-endpoint = @@ -1099,7 +1101,7 @@ }; }; - port@8 { + port@13 { reg = <13>; tpda13_in_tpdm_west: endpoint { remote-endpoint = @@ -1107,7 +1109,7 @@ }; }; - port@9 { + port@15 { reg = <15>; tpda15_in_tpdm_pimem: endpoint { remote-endpoint = @@ -1118,6 +1120,43 @@ }; }; + funnel_lpass_lpi: funnel@8a24000 { + compatible = "arm,coresight-static-funnel"; + coresight-name = "coresight-funnel-lpass-lpi"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_lpass_lpi_in_audio_etm0: endpoint { + remote-endpoint = + <&audio_etm0_out_funnel_lpass_lpi>; + }; + }; + + port@5 { + reg = <5>; + funnel_lpass_lpi_in_tpdm_lpass: endpoint { + remote-endpoint = + <&tpdm_lpass_out_funnel_lpass_lpi>; + }; + }; + + }; + + out-ports { + port { + lpass_lpi_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_lpass_lpi>; + }; + }; + }; + + }; + funnel_qatb: funnel@8005000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x000bb908>; @@ -1143,7 +1182,7 @@ #address-cells = <1>; #size-cells = <0>; - port@1 { + port@0 { reg = <0>; funnel_qatb_in_tpda: endpoint { remote-endpoint = @@ -1151,7 +1190,7 @@ }; }; - port@2 { + port@6 { reg = <6>; funnel_qatb_in_funnel_turing: endpoint { remote-endpoint = @@ -1159,21 +1198,14 @@ }; }; - port@3 { + port@5 { reg = <5>; - funnel_qatb_in_tpdm_lpass: endpoint { + funnel_qatb_in_lpass_lpi: endpoint { remote-endpoint = - <&tpdm_lpass_out_funnel_qatb>; + <&lpass_lpi_out_funnel_qatb>; }; }; - port@4 { - reg = <5>; - funnel_qatb_in_audio_etm0: endpoint { - remote-endpoint = - <&audio_etm0_out_funnel_qatb>; - }; - }; }; }; @@ -1202,7 +1234,7 @@ #address-cells = <1>; #size-cells = <0>; - port@1 { + port@5 { reg = <5>; funnel_in0_in_snoc: endpoint { remote-endpoint = @@ -1210,7 +1242,7 @@ }; }; - port@2 { + port@6 { reg = <6>; funnel_in0_in_funnel_qatb: endpoint { remote-endpoint = @@ -1218,7 +1250,7 @@ }; }; - port@3 { + port@7 { reg = <7>; funnel_in0_in_stm: endpoint { remote-endpoint = @@ -1285,7 +1317,7 @@ }; }; - port@5 { + port@6 { reg = <6>; funnel_in1_in_funnel_apss1: endpoint { remote-endpoint = @@ -1321,7 +1353,7 @@ #address-cells = <1>; #size-cells = <0>; - port@1 { + port@0 { reg = <0>; funnel_merg_in_funnel_in0: endpoint { remote-endpoint = @@ -1329,7 +1361,7 @@ }; }; - port@2 { + port@1 { reg = <1>; funnel_merg_in_funnel_in1: endpoint { remote-endpoint = @@ -1366,7 +1398,7 @@ #address-cells = <1>; #size-cells = <0>; - port@1 { + port@0 { reg = <0>; tmc_etf_in_funnel_merg: endpoint { remote-endpoint = @@ -1402,7 +1434,7 @@ #address-cells = <1>; #size-cells = <0>; - port@1 { + port@0 { reg = <0>; replicator_qdss_in_tmc_etf: endpoint { remote-endpoint = @@ -1432,6 +1464,7 @@ ranges; qcom,mem_support; + usb_bam_support; dma-coherent; arm,buffer-size = <0x400000>; arm,scatter-gather; @@ -1463,8 +1496,8 @@ }; cti_cortex_M3: cti@8B30000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8B30000 0x1000>; reg-names = "cti-base"; @@ -1475,8 +1508,8 @@ }; cti_apss_cti0: cti@98E0000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x98E0000 0x1000>; reg-names = "cti-base"; @@ -1487,8 +1520,8 @@ }; cti_apss_cti1: cti@98F0000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x98F0000 0x1000>; reg-names = "cti-base"; @@ -1499,8 +1532,8 @@ }; cti_wcss_cti0: cti@89A4000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x89A4000 0x1000>; reg-names = "cti-base"; status = "disabled"; @@ -1511,8 +1544,8 @@ }; cti_wcss_cti1: cti@89A5000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x89A5000 0x1000>; reg-names = "cti-base"; status = "disabled"; @@ -1523,8 +1556,8 @@ }; cti_wcss_cti2: cti@89A6000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x89A6000 0x1000>; reg-names = "cti-base"; status = "disabled"; @@ -1535,8 +1568,8 @@ }; cti_lpass_q6: cti@8A21000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8A21000 0x1000>; reg-names = "cti-base"; @@ -1548,8 +1581,8 @@ }; cti_turing_q6: cti@8867000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8867000 0x1000>; reg-names = "cti-base"; @@ -1560,8 +1593,8 @@ }; cti_mss_q6: cti@8833000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8833000 0x1000>; reg-names = "cti-base"; @@ -1572,8 +1605,8 @@ }; cti_isdb_gpu: cti@8941000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8941000 0x1000>; reg-names = "cti-base"; status = "disabled"; @@ -1584,8 +1617,8 @@ }; cti_mapss: cti@8A02000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8A02000 0x1000>; reg-names = "cti-base"; @@ -1596,8 +1629,8 @@ }; cti_dlct_cti0: cti@8B59000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8B59000 0x1000>; reg-names = "cti-base"; @@ -1608,8 +1641,8 @@ }; cti_dlct_cti1: cti@8B5A000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8B5A000 0x1000>; reg-names = "cti-base"; @@ -1620,8 +1653,8 @@ }; cti_dlct_cti2: cti@8B5B000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8B5B000 0x1000>; reg-names = "cti-base"; @@ -1632,8 +1665,8 @@ }; cti_dlct_cti3: cti@8B5C000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8B5C000 0x1000>; reg-names = "cti-base"; @@ -1644,8 +1677,8 @@ }; cti0: cti@8010000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8010000 0x1000>; reg-names = "cti-base"; @@ -1656,8 +1689,8 @@ }; cti1: cti@8011000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8011000 0x1000>; reg-names = "cti-base"; @@ -1668,8 +1701,8 @@ }; cti10: cti@801a000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x801a000 0x1000>; reg-names = "cti-base"; @@ -1680,8 +1713,8 @@ }; cti11: cti@801b000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x801b000 0x1000>; reg-names = "cti-base"; @@ -1692,8 +1725,8 @@ }; cti12: cti@801c000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x801c000 0x1000>; reg-names = "cti-base"; @@ -1704,8 +1737,8 @@ }; cti13: cti@801d000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x801d000 0x1000>; reg-names = "cti-base"; @@ -1716,8 +1749,8 @@ }; cti14: cti@801e000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x801e000 0x1000>; reg-names = "cti-base"; @@ -1728,8 +1761,8 @@ }; cti15: cti@801f000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x801f000 0x1000>; reg-names = "cti-base"; @@ -1740,8 +1773,8 @@ }; cti2: cti@8012000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8012000 0x1000>; reg-names = "cti-base"; @@ -1752,8 +1785,8 @@ }; cti3: cti@8013000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8013000 0x1000>; reg-names = "cti-base"; @@ -1764,8 +1797,8 @@ }; cti4: cti@8014000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8014000 0x1000>; reg-names = "cti-base"; @@ -1776,8 +1809,8 @@ }; cti5: cti@8015000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8015000 0x1000>; reg-names = "cti-base"; @@ -1788,8 +1821,8 @@ }; cti6: cti@8016000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8016000 0x1000>; reg-names = "cti-base"; @@ -1800,8 +1833,8 @@ }; cti7: cti@8017000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8017000 0x1000>; reg-names = "cti-base"; @@ -1812,8 +1845,8 @@ }; cti8: cti@8018000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8018000 0x1000>; reg-names = "cti-base"; @@ -1824,8 +1857,8 @@ }; cti9: cti@8019000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb966>; + compatible = "arm,coresight-cti", "arm,primecell"; + arm,primecell-periphid = <0x000bb922>; reg = <0x8019000 0x1000>; reg-names = "cti-base"; From cdfed5d819f441c4b5beea6d2f0f59333240f4de Mon Sep 17 00:00:00 2001 From: Yao Zhao Date: Wed, 28 Sep 2022 07:12:33 +0530 Subject: [PATCH 29/41] ARM: dts: msm: Add initial device tree for kona iot target Add initial devicetree support for kona iot target. Change-Id: I455bf739ec049e1e1ef01f55707a746fd54653d4 --- bindings/arm/msm/msm.txt | 1 + bindings/pinctrl/qcom,kona-pinctrl.txt | 197 + qcom/Makefile | 10 + qcom/kona-iot-v2.1-vc-overlay.dts | 10 + qcom/kona-iot-v2.1-vc.dtsi | 1 + qcom/kona-iot-v2.1.dts | 9 + qcom/kona-iot-v2.1.dtsi | 7 + qcom/kona-iot-v2.dts | 9 + qcom/kona-iot-v2.dtsi | 8 + qcom/kona-iot-vc.dtsi | 12 + qcom/kona-iot.dts | 9 + qcom/kona-iot.dtsi | 7 + qcom/kona-pinctrl.dtsi | 4542 ++++++++++++++++++++++++ qcom/kona-v2.1.dtsi | 8 + qcom/kona-v2.dtsi | 23 + qcom/kona.dtsi | 1108 ++++++ 16 files changed, 5961 insertions(+) create mode 100644 bindings/pinctrl/qcom,kona-pinctrl.txt create mode 100644 qcom/kona-iot-v2.1-vc-overlay.dts create mode 100644 qcom/kona-iot-v2.1-vc.dtsi create mode 100644 qcom/kona-iot-v2.1.dts create mode 100644 qcom/kona-iot-v2.1.dtsi create mode 100644 qcom/kona-iot-v2.dts create mode 100644 qcom/kona-iot-v2.dtsi create mode 100644 qcom/kona-iot-vc.dtsi create mode 100644 qcom/kona-iot.dts create mode 100644 qcom/kona-iot.dtsi create mode 100644 qcom/kona-pinctrl.dtsi create mode 100644 qcom/kona-v2.1.dtsi create mode 100644 qcom/kona-v2.dtsi create mode 100644 qcom/kona.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 6b7f1c2c..c8f05b54 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -247,6 +247,7 @@ compatible = "qcom,kona-rumi" compatible = "qcom,kona-mtp" compatible = "qcom,kona-cdp" compatible = "qcom,kona-qrd" +compatible = "qcom,kona-iot" compatible = "qcom,lahaina-rumi" compatible = "qcom,lahaina-atp" compatible = "qcom,lahaina-mtp" diff --git a/bindings/pinctrl/qcom,kona-pinctrl.txt b/bindings/pinctrl/qcom,kona-pinctrl.txt new file mode 100644 index 00000000..92520b8c --- /dev/null +++ b/bindings/pinctrl/qcom,kona-pinctrl.txt @@ -0,0 +1,197 @@ +Qualcomm Technologies, Inc. KONA TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +KONA platform. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,kona-pinctrl" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- wakeup-parent: + Usage: optional + Value type: + Definition: A phandle to the wakeup interrupt controller for the SoC. + +- qcom,gpios-reserved: + Usage: optional + Value type: + Definition: A list of reserved gpios that should not be used by the kernel drivers. + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins are: + gpio0-gpio149 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + +- function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + + blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio + +- bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configured as no pull. + +- bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull down. + +- bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull up. + +- output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + high. + Not valid for sdc pins. + +- output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + low. + Not valid for sdc pins. + +- drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@03000000 { + compatible = "qcom,kona-pinctrl"; + reg = <0x03000000 0xdc2000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + }; diff --git a/qcom/Makefile b/qcom/Makefile index e8d09d92..5e38c8a2 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -122,6 +122,16 @@ bengal-dtb-$(CONFIG_ARCH_KHAJE) += \ bengal-overlays-dtb-$(CONFIG_ARCH_KHAJE) += $(KHAJE_BOARDS) $(KHAJE_BASE_DTB) dtb-y += $(bengal-dtb-y) +KONA_BASE_DTB += kona-iot.dtb kona-iot-v2.dtb kona-iot-v2.1.dtb + +KONA_BOARDS += \ + kona-iot-v2.1-vc-overlay.dtbo + +kona-dtb-$(CONFIG_ARCH_KONA) += \ + $(call add-overlays, $(KONA_BOARDS) ,$(KONA_BASE_DTB)) +kona-overlays-dtb-$(CONFIG_ARCH_KONA) += $(KONA_BOARDS) $(KONA_BASE_DTB) +dtb-y += $(kona-dtb-y) + MONACO_BASE_DTB += monaco.dtb monacop.dtb MONACO_BOARDS += \ diff --git a/qcom/kona-iot-v2.1-vc-overlay.dts b/qcom/kona-iot-v2.1-vc-overlay.dts new file mode 100644 index 00000000..8e41be32 --- /dev/null +++ b/qcom/kona-iot-v2.1-vc-overlay.dts @@ -0,0 +1,10 @@ +/dts-v1/; +/plugin/; + +#include "kona-iot-v2.1-vc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. kona-iot VC"; + compatible = "qcom,kona-iot"; + qcom,board-id = <0x010020 0x07>; +}; diff --git a/qcom/kona-iot-v2.1-vc.dtsi b/qcom/kona-iot-v2.1-vc.dtsi new file mode 100644 index 00000000..5c17996d --- /dev/null +++ b/qcom/kona-iot-v2.1-vc.dtsi @@ -0,0 +1 @@ +#include "kona-iot-vc.dtsi" diff --git a/qcom/kona-iot-v2.1.dts b/qcom/kona-iot-v2.1.dts new file mode 100644 index 00000000..435cd698 --- /dev/null +++ b/qcom/kona-iot-v2.1.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "kona-iot-v2.1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. kona-iot v2.1 SoC"; + compatible = "qcom,kona-iot"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/kona-iot-v2.1.dtsi b/qcom/kona-iot-v2.1.dtsi new file mode 100644 index 00000000..4ce3f21c --- /dev/null +++ b/qcom/kona-iot-v2.1.dtsi @@ -0,0 +1,7 @@ + #include "kona-v2.1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. kona-iot v2.1"; + compatible = "qcom,kona-iot"; + qcom,msm-id = <481 0x20001>; +}; diff --git a/qcom/kona-iot-v2.dts b/qcom/kona-iot-v2.dts new file mode 100644 index 00000000..c7606918 --- /dev/null +++ b/qcom/kona-iot-v2.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "kona-iot-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. kona-iot v2 SoC"; + compatible = "qcom,kona-iot"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/kona-iot-v2.dtsi b/qcom/kona-iot-v2.dtsi new file mode 100644 index 00000000..db10880e --- /dev/null +++ b/qcom/kona-iot-v2.dtsi @@ -0,0 +1,8 @@ + #include "kona-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. kona-iot v2"; + compatible = "qcom,kona-iot"; + qcom,msm-id = <481 0x20000>; +}; + diff --git a/qcom/kona-iot-vc.dtsi b/qcom/kona-iot-vc.dtsi new file mode 100644 index 00000000..fa9050d0 --- /dev/null +++ b/qcom/kona-iot-vc.dtsi @@ -0,0 +1,12 @@ +#include + +&tlmm { + key_factory_reset { + key_factory_reset_default: key_factory_reset_default { + pins = "gpio22"; + function = "normal"; + input-enable; + bias-pull-up; + }; + }; +}; diff --git a/qcom/kona-iot.dts b/qcom/kona-iot.dts new file mode 100644 index 00000000..1fb20243 --- /dev/null +++ b/qcom/kona-iot.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "kona-iot.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. kona-iot"; + compatible = "qcom,kona-iot"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/kona-iot.dtsi b/qcom/kona-iot.dtsi new file mode 100644 index 00000000..62a4c346 --- /dev/null +++ b/qcom/kona-iot.dtsi @@ -0,0 +1,7 @@ +#include "kona.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kona-iot"; + compatible = "qcom,kona-iot"; + qcom,msm-id = <481 0x0>; +}; diff --git a/qcom/kona-pinctrl.dtsi b/qcom/kona-pinctrl.dtsi new file mode 100644 index 00000000..d9a4e596 --- /dev/null +++ b/qcom/kona-pinctrl.dtsi @@ -0,0 +1,4542 @@ +&soc { + tlmm: pinctrl@f000000 { + compatible = "qcom,kona-pinctrl"; + reg = <0x0F000000 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + qcom,gpios-reserved = <28 29 30 31 40 41 42 43>; + irqdomain-map = <0 0 &pdc 79 0>, + <1 0 &pdc 84 0>, + <2 0 &pdc 80 0>, + <3 0 &pdc 82 0>, + <4 0 &pdc 107 0>, + <7 0 &pdc 43 0>, + <11 0 &pdc 42 0>, + <14 0 &pdc 44 0>, + <15 0 &pdc 52 0>, + <19 0 &pdc 67 0>, + <23 0 &pdc 68 0>, + <24 0 &pdc 105 0>, + <27 0 &pdc 92 0>, + <28 0 &pdc 106 0>, + <31 0 &pdc 69 0>, + <35 0 &pdc 70 0>, + <39 0 &pdc 73 0>, + <40 0 &pdc 108 0>, + <43 0 &pdc 71 0>, + <45 0 &pdc 72 0>, + <47 0 &pdc 83 0>, + <51 0 &pdc 74 0>, + <55 0 &pdc 77 0>, + <59 0 &pdc 78 0>, + <63 0 &pdc 75 0>, + <64 0 &pdc 81 0>, + <65 0 &pdc 87 0>, + <66 0 &pdc 88 0>, + <67 0 &pdc 89 0>, + <68 0 &pdc 54 0>, + <70 0 &pdc 85 0>, + <77 0 &pdc 46 0>, + <80 0 &pdc 90 0>, + <81 0 &pdc 91 0>, + <83 0 &pdc 97 0>, + <84 0 &pdc 98 0>, + <86 0 &pdc 99 0>, + <88 0 &pdc 101 0>, + <89 0 &pdc 102 0>, + <92 0 &pdc 103 0>, + <93 0 &pdc 104 0>, + <100 0 &pdc 53 0>, + <103 0 &pdc 47 0>, + <104 0 &pdc 48 0>, + <108 0 &pdc 49 0>, + <109 0 &pdc 94 0>, + <110 0 &pdc 95 0>, + <111 0 &pdc 96 0>, + <112 0 &pdc 55 0>, + <113 0 &pdc 56 0>, + <118 0 &pdc 50 0>, + <121 0 &pdc 51 0>, + <122 0 &pdc 57 0>, + <123 0 &pdc 58 0>, + <124 0 &pdc 45 0>, + <126 0 &pdc 59 0>, + <128 0 &pdc 76 0>, + <129 0 &pdc 86 0>, + <132 0 &pdc 93 0>, + <133 0 &pdc 65 0>, + <134 0 &pdc 66 0>, + <136 0 &pdc 62 0>, + <137 0 &pdc 63 0>, + <138 0 &pdc 64 0>, + <142 0 &pdc 60 0>, + <143 0 &pdc 61 0>, + <147 0 &pdc 109 0>, /* bi_mx_lpass_1_aoss_mx */ + <150 0 &pdc 110 0>, + <157 0 &pdc 111 0>, + <158 0 &pdc 112 0>, + <160 0 &pdc 113 0>, + <162 0 &pdc 114 0>, + <164 0 &pdc 115 0>, + <166 0 &pdc 116 0>, + <167 0 &pdc 117 0>, + <175 0 &pdc 118 0>, + <177 0 &pdc 119 0>, + <179 0 &pdc 120 0>; + irqdomain-map-mask = <0xff 0>; + irqdomain-map-pass-thru = <0 0xff>; + + trigout_a: trigout_a { + mux { + pins = "gpio2"; + function = "qdss_cti"; + }; + + config { + pins = "gpio2"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se2_2uart_pins: qupv3_se2_2uart_pins { + qupv3_se2_2uart_active: qupv3_se2_2uart_active { + mux { + pins = "gpio117", "gpio118"; + function = "qup2"; + }; + + config { + pins = "gpio117", "gpio118"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se2_2uart_sleep: qupv3_se2_2uart_sleep { + mux { + pins = "gpio117", "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio117", "gpio118"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se6_4uart_pins: qupv3_se6_4uart_pins { + qupv3_se6_default_cts: + qupv3_se6_default_cts { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se6_default_rtsrx: + qupv3_se6_default_rtsrx { + mux { + pins = "gpio17", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio17", "gpio19"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se6_default_tx: + qupv3_se6_default_tx { + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_ctsrx: qupv3_se6_ctsrx { + mux { + pins = "gpio16", "gpio19"; + function = "qup6"; + }; + + config { + pins = "gpio16", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se6_rts: qupv3_se6_rts { + mux { + pins = "gpio17"; + function = "qup6"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se6_tx: qupv3_se6_tx { + mux { + pins = "gpio18"; + function = "qup6"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se12_2uart_pins: qupv3_se12_2uart_pins { + qupv3_se12_2uart_active: qupv3_se12_2uart_active { + mux { + pins = "gpio34", "gpio35"; + function = "qup12"; + }; + + config { + pins = "gpio34", "gpio35"; + drive-strength = <2>; + }; + }; + + qupv3_se12_2uart_sleep: qupv3_se12_2uart_sleep { + mux { + pins = "gpio34", "gpio35"; + drive-strength = <2>; + bias-pull-down; + }; + + config { + pins = "gpio34", "gpio35"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se17_4uart_pins: qupv3_se17_4uart_pins { + qupv3_se17_ctsrx: qupv3_se17_ctsrx { + mux { + pins = "gpio52", "gpio55"; + function = "qup17"; + }; + + config { + pins = "gpio52", "gpio55"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + qupv3_se17_rts: qupv3_se17_rts { + mux { + pins = "gpio53"; + function = "qup17"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se17_tx: qupv3_se17_tx { + mux { + pins = "gpio54"; + function = "qup17"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se18_2uart_pins: qupv3_se18_2uart_pins { + qupv3_se18_rx: qupv3_se18_rx { + mux { + pins = "gpio59"; + function = "qup18"; + }; + + config { + pins = "gpio59"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + qupv3_se18_tx: qupv3_se18_tx { + mux { + pins = "gpio58"; + function = "qup18"; + }; + + config { + pins = "gpio58"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pmx_ts_active { + ts_active: ts_active { + mux { + pins = "gpio38", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio38", "gpio39"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio39"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + pmx_ts_release: pmx_ts_release { + mux { + pins = "gpio38", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio38", "gpio39"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + ufs_dev_reset_assert: ufs_dev_reset_assert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + + sdc2_on: sdc2_on { + clk { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + + data { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + + sd-cd { + pins = "gpio77"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + + data { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + + sd_cd { + pins = "gpio77"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* add pins for DisplayPort */ + sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active { + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + bias-disable; + drive-strength = <16>; + }; + }; + + sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend { + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + ap2mdm { + ap2mdm_active: ap2mdm_active { + mux { + /* ap2mdm-status + * ap2mdm-errfatal + * ap2mdm-vddmin + */ + pins = "gpio56", "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio56", "gpio57"; + drive-strength = <16>; + bias-disable; + }; + }; + + ap2mdm_sleep: ap2mdm_sleep { + mux { + /* ap2mdm-status + * ap2mdm-errfatal + * ap2mdm-vddmin + */ + pins = "gpio56", "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio56", "gpio57"; + drive-strength = <8>; + bias-disable; + }; + + }; + }; + + mdm2ap { + mdm2ap_active: mdm2ap_active { + mux { + /* mdm2ap-status + * mdm2ap-errfatal + * mdm2ap-vddmin + */ + pins = "gpio1", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio1", "gpio3"; + drive-strength = <8>; + bias-disable; + }; + }; + + mdm2ap_sleep: mdm2ap_sleep { + mux { + /* mdm2ap-status + * mdm2ap-errfatal + * mdm2ap-vddmin + */ + pins = "gpio1", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio1", "gpio3"; + drive-strength = <8>; + bias-disable; + }; + }; + }; + + pcie0 { + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio79"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio80"; + function = "pci_e0"; + }; + + config { + pins = "gpio80"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_clkreq_sleep: pcie0_clkreq_sleep { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie1 { + pcie1_perst_default: pcie1_perst_default { + mux { + pins = "gpio82"; + function = "gpio"; + }; + + config { + pins = "gpio82"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie1_clkreq_default: pcie1_clkreq_default { + mux { + pins = "gpio83"; + function = "pci_e1"; + }; + + config { + pins = "gpio83"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_wake_default: pcie1_wake_default { + mux { + pins = "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio84"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie2 { + pcie2_perst_default: pcie2_perst_default { + mux { + pins = "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio85"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie2_clkreq_default: pcie2_clkreq_default { + mux { + pins = "gpio86"; + function = "pci_e2"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie2_wake_default: pcie2_wake_default { + mux { + pins = "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio87"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + }; + + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio75", "gpio60"; + function = "gpio"; + }; + + config { + pins = "gpio75", "gpio60"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio75", "gpio60"; + function = "gpio"; + }; + + config { + pins = "gpio75", "gpio60"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_dsi1_active: sde_dsi1_active { + mux { + pins = "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio128"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi1_suspend: sde_dsi1_suspend { + mux { + pins = "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio66"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio66"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_active: sde_te1_active { + mux { + pins = "gpio67"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio67"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_suspend: sde_te1_suspend { + mux { + pins = "gpio67"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio67"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pri_aux_pcm_clk { + pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep { + mux { + pins = "gpio138"; + function = "gpio"; + }; + + config { + pins = "gpio138"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_clk_active: pri_aux_pcm_clk_active { + mux { + pins = "gpio138"; + function = "mi2s0_sck"; + }; + + config { + pins = "gpio138"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_aux_pcm_sync { + pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep { + mux { + pins = "gpio141"; + function = "gpio"; + }; + + config { + pins = "gpio141"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_sync_active: pri_aux_pcm_sync_active { + mux { + pins = "gpio141"; + function = "mi2s0_ws"; + }; + + config { + pins = "gpio141"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_aux_pcm_din { + pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep { + mux { + pins = "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio139"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_din_active: pri_aux_pcm_din_active { + mux { + pins = "gpio139"; + function = "mi2s0_data0"; + }; + + config { + pins = "gpio139"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_aux_pcm_dout { + pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_dout_active: pri_aux_pcm_dout_active { + mux { + pins = "gpio140"; + function = "mi2s0_data1"; + }; + + config { + pins = "gpio140"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm { + sec_aux_pcm_clk_sleep: sec_aux_pcm_clk_sleep { + mux { + pins = "gpio142"; + function = "gpio"; + }; + + config { + pins = "gpio142"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_clk_active: sec_aux_pcm_clk_active { + mux { + pins = "gpio142"; + function = "mi2s1_sck"; + }; + + config { + pins = "gpio142"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + + sec_aux_pcm_ws_sleep: sec_aux_pcm_ws_sleep { + mux { + pins = "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio145"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_ws_active: sec_aux_pcm_ws_active { + mux { + pins = "gpio145"; + function = "mi2s1_ws"; + }; + + config { + pins = "gpio145"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm_din { + sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep { + mux { + pins = "gpio143"; + function = "gpio"; + }; + + config { + pins = "gpio143"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_din_active: sec_aux_pcm_din_active { + mux { + pins = "gpio143"; + function = "mi2s1_data0"; + }; + + config { + pins = "gpio143"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm_dout { + sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep { + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_dout_active: sec_aux_pcm_dout_active { + mux { + pins = "gpio144"; + function = "mi2s1_data1"; + }; + + config { + pins = "gpio144"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_aux_pcm { + tert_aux_pcm_clk_sleep: tert_aux_pcm_clk_sleep { + mux { + pins = "gpio133"; + function = "gpio"; + }; + + config { + pins = "gpio133"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_clk_active: tert_aux_pcm_clk_active { + mux { + pins = "gpio133"; + function = "mi2s2_sck"; + }; + + config { + pins = "gpio133"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + + tert_aux_pcm_ws_sleep: tert_aux_pcm_ws_sleep { + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_ws_active: tert_aux_pcm_ws_active { + mux { + pins = "gpio135"; + function = "mi2s2_ws"; + }; + + config { + pins = "gpio135"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_aux_pcm_din { + tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep { + mux { + pins = "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio134"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_din_active: tert_aux_pcm_din_active { + mux { + pins = "gpio134"; + function = "mi2s2_data0"; + }; + + config { + pins = "gpio134"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_aux_pcm_dout { + tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep { + mux { + pins = "gpio137"; + function = "gpio"; + }; + + config { + pins = "gpio137"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_dout_active: tert_aux_pcm_dout_active { + mux { + pins = "gpio137"; + function = "mi2s2_data1"; + }; + + config { + pins = "gpio137"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_tdm_clk { + pri_tdm_clk_sleep: pri_tdm_clk_sleep { + mux { + pins = "gpio138"; + function = "gpio"; + }; + + config { + pins = "gpio138"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_clk_active: pri_tdm_clk_active { + mux { + pins = "gpio138"; + function = "mi2s0_sck"; + }; + + config { + pins = "gpio138"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_tdm_sync { + pri_tdm_sync_sleep: pri_tdm_sync_sleep { + mux { + pins = "gpio141"; + function = "gpio"; + }; + + config { + pins = "gpio141"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_sync_active: pri_tdm_sync_active { + mux { + pins = "gpio141"; + function = "mi2s0_ws"; + }; + + config { + pins = "gpio141"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_tdm_din { + pri_tdm_din_sleep: pri_tdm_din_sleep { + mux { + pins = "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio139"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_din_active: pri_tdm_din_active { + mux { + pins = "gpio139"; + function = "mi2s0_data0"; + }; + + config { + pins = "gpio139"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_tdm_dout { + pri_tdm_dout_sleep: pri_tdm_dout_sleep { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_dout_active: pri_tdm_dout_active { + mux { + pins = "gpio140"; + function = "mi2s0_data1"; + }; + + config { + pins = "gpio140"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_tdm { + sec_tdm_sck_sleep: sec_tdm_sck_sleep { + mux { + pins = "gpio142"; + function = "gpio"; + }; + + config { + pins = "gpio142"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_sck_active: sec_tdm_sck_active { + mux { + pins = "gpio142"; + function = "mi2s1_sck"; + }; + + config { + pins = "gpio142"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + + sec_tdm_ws_sleep: sec_tdm_ws_sleep { + mux { + pins = "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio145"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_ws_active: sec_tdm_ws_active { + mux { + pins = "gpio145"; + function = "mi2s1_ws"; + }; + + config { + pins = "gpio145"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_tdm_din { + sec_tdm_din_sleep: sec_tdm_din_sleep { + mux { + pins = "gpio143"; + function = "gpio"; + }; + + config { + pins = "gpio143"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_din_active: sec_tdm_din_active { + mux { + pins = "gpio143"; + function = "mi2s1_data0"; + }; + + config { + pins = "gpio143"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_tdm_dout { + sec_tdm_dout_sleep: sec_tdm_dout_sleep { + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_dout_active: sec_tdm_dout_active { + mux { + pins = "gpio144"; + function = "mi2s1_data1"; + }; + + config { + pins = "gpio144"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_tdm { + tert_tdm_clk_sleep: tert_tdm_clk_sleep { + mux { + pins = "gpio133"; + function = "gpio"; + }; + + config { + pins = "gpio133"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_clk_active: tert_tdm_clk_active { + mux { + pins = "gpio133"; + function = "mi2s2_sck"; + }; + + config { + pins = "gpio133"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + + tert_tdm_ws_sleep: tert_tdm_ws_sleep { + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_ws_active: tert_tdm_ws_active { + mux { + pins = "gpio135"; + function = "mi2s2_ws"; + }; + + config { + pins = "gpio135"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_tdm_din { + tert_tdm_din_sleep: tert_tdm_din_sleep { + mux { + pins = "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio134"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_din_active: tert_tdm_din_active { + mux { + pins = "gpio134"; + function = "mi2s2_data0"; + }; + + config { + pins = "gpio134"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_tdm_dout { + tert_tdm_dout_sleep: tert_tdm_dout_sleep { + mux { + pins = "gpio137"; + function = "gpio"; + }; + + config { + pins = "gpio137"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_dout_active: tert_tdm_dout_active { + mux { + pins = "gpio137"; + function = "mi2s2_data1"; + }; + + config { + pins = "gpio137"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_mi2s_mclk { + pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep { + mux { + pins = "gpio136"; + function = "gpio"; + }; + + config { + pins = "gpio136"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_mclk_active: pri_mi2s_mclk_active { + mux { + pins = "gpio136"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio136"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sck { + pri_mi2s_sck_sleep: pri_mi2s_sck_sleep { + mux { + pins = "gpio138"; + function = "gpio"; + }; + + config { + pins = "gpio138"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sck_active: pri_mi2s_sck_active { + mux { + pins = "gpio138"; + function = "mi2s0_sck"; + }; + + config { + pins = "gpio138"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_ws { + pri_mi2s_ws_sleep: pri_mi2s_ws_sleep { + mux { + pins = "gpio141"; + function = "gpio"; + }; + + config { + pins = "gpio141"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_ws_active: pri_mi2s_ws_active { + mux { + pins = "gpio141"; + function = "mi2s0_ws"; + }; + + config { + pins = "gpio141"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd0 { + pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep { + mux { + pins = "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio139"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd0_active: pri_mi2s_sd0_active { + mux { + pins = "gpio139"; + function = "mi2s0_data0"; + }; + + config { + pins = "gpio139"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd1 { + pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd1_active: pri_mi2s_sd1_active { + mux { + pins = "gpio140"; + function = "mi2s0_data1"; + }; + + config { + pins = "gpio140"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + sec_mi2s_mclk { + sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep { + mux { + pins = "gpio137"; + function = "gpio"; + }; + + config { + pins = "gpio137"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_mclk_active: sec_mi2s_mclk_active { + mux { + pins = "gpio137"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio137"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + sec_mi2s_sck { + sec_mi2s_sck_sleep: sec_mi2s_sck_sleep { + mux { + pins = "gpio142"; + function = "gpio"; + }; + + config { + pins = "gpio142"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sck_active: sec_mi2s_sck_active { + mux { + pins = "gpio142"; + function = "mi2s1_sck"; + }; + + config { + pins = "gpio142"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_ws { + sec_mi2s_ws_sleep: sec_mi2s_ws_sleep { + mux { + pins = "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio145"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_ws_active: sec_mi2s_ws_active { + mux { + pins = "gpio145"; + function = "mi2s1_ws"; + }; + + config { + pins = "gpio145"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd0 { + sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep { + mux { + pins = "gpio143"; + function = "gpio"; + }; + + config { + pins = "gpio143"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd0_active: sec_mi2s_sd0_active { + mux { + pins = "gpio143"; + function = "mi2s1_data0"; + }; + + config { + pins = "gpio143"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd1 { + sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep { + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd1_active: sec_mi2s_sd1_active { + mux { + pins = "gpio144"; + function = "mi2s1_data1"; + }; + + config { + pins = "gpio144"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_sck { + tert_mi2s_sck_sleep: tert_mi2s_sck_sleep { + mux { + pins = "gpio133"; + function = "gpio"; + }; + + config { + pins = "gpio133"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_sck_active: tert_mi2s_sck_active { + mux { + pins = "gpio133"; + function = "mi2s2_sck"; + }; + + config { + pins = "gpio133"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_ws { + tert_mi2s_ws_sleep: tert_mi2s_ws_sleep { + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_ws_active: tert_mi2s_ws_active { + mux { + pins = "gpio135"; + function = "mi2s2_ws"; + }; + + config { + pins = "gpio135"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_sd0 { + tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep { + mux { + pins = "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio134"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_sd0_active: tert_mi2s_sd0_active { + mux { + pins = "gpio134"; + function = "mi2s2_data0"; + }; + + config { + pins = "gpio134"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_sd1 { + tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep { + mux { + pins = "gpio137"; + function = "gpio"; + }; + + config { + pins = "gpio137"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_sd1_active: tert_mi2s_sd1_active { + mux { + pins = "gpio137"; + function = "mi2s2_data1"; + }; + + config { + pins = "gpio137"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + /* WSA speaker reset pins */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + spkr_2_sd_n { + spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_2_sd_n_active: spkr_2_sd_n_active { + mux { + pins = "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio127"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + wcd938x_reset_active: wcd938x_reset_active { + mux { + pins = "gpio32"; + function = "func2"; + }; + + config { + pins = "gpio32"; + drive-strength = <16>; + output-high; + }; + }; + + wcd938x_reset_sleep: wcd938x_reset_sleep { + mux { + pins = "gpio32"; + function = "func2"; + }; + + config { + pins = "gpio32"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio94"; + function = "cam_mclk"; + }; + + config { + pins = "gpio94"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio94"; + function = "cam_mclk"; + }; + + config { + pins = "gpio94"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio95"; + function = "cam_mclk"; + }; + + config { + pins = "gpio95"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio95"; + function = "cam_mclk"; + }; + + config { + pins = "gpio95"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio96"; + function = "cam_mclk"; + }; + + config { + pins = "gpio96"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio96"; + function = "cam_mclk"; + }; + + config { + pins = "gpio96"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio97"; + function = "cam_mclk"; + }; + + config { + pins = "gpio97"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio97"; + function = "cam_mclk"; + }; + + config { + pins = "gpio97"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_active: cam_sensor_mclk4_active { + /* MCLK4 */ + mux { + pins = "gpio98"; + function = "cam_mclk"; + }; + + config { + pins = "gpio98"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend { + /* MCLK4 */ + mux { + pins = "gpio98"; + function = "cam_mclk"; + }; + + config { + pins = "gpio98"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk5_active: cam_sensor_mclk5_active { + /* MCLK5 */ + mux { + pins = "gpio99"; + function = "cam_mclk"; + }; + + config { + pins = "gpio99"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk5_suspend: cam_sensor_mclk5_suspend { + /* MCLK5 */ + mux { + pins = "gpio99"; + function = "cam_mclk"; + }; + + config { + pins = "gpio99"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk6_active: cam_sensor_mclk6_active { + /* MCLK6 */ + mux { + pins = "gpio100"; + function = "cam_mclk"; + }; + + config { + pins = "gpio100"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk6_suspend: cam_sensor_mclk6_suspend { + /* MCLK6 */ + mux { + pins = "gpio100"; + function = "cam_mclk"; + }; + + config { + pins = "gpio100"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rear: cam_sensor_active_rear { + /* RESET REAR */ + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rear: cam_sensor_suspend_rear { + /* RESET REAR */ + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rear_aux: cam_sensor_active_rear_aux { + /* RESET REARAUX */ + mux { + pins = "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio92"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rear_aux: cam_sensor_suspend_rear_aux { + /* RESET REARAUX */ + mux { + pins = "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio92"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst2: cam_sensor_active_rst2 { + /* RESET 2 */ + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst2: cam_sensor_suspend_rst2 { + /* RESET 2 */ + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_3: cam_sensor_active_3 { + /* RESET 3 */ + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_3: cam_sensor_suspend_3 { + /* RESET 3 */ + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst4: cam_sensor_active_rst4 { + /* RESET 2 */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst4: cam_sensor_suspend_rst4 { + /* RESET 2 */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst3: cam_sensor_active_rst3 { + /* RESET 2 */ + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst3: cam_sensor_suspend_rst3 { + /* RESET 2 */ + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_4: cam_sensor_active_4 { + /* RESET 4 */ + mux { + pins = "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio130"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_4: cam_sensor_suspend_4 { + /* RESET 4 */ + mux { + pins = "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio130"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_5: cam_sensor_active_5 { + /* RESET 5 */ + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_5: cam_sensor_suspend_5 { + /* RESET 5 */ + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_6: cam_sensor_active_6 { + /* RESET 6 */ + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_6: cam_sensor_suspend_6 { + /* RESET 6 */ + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio101","gpio102"; // Only 2 + function = "cci_i2c"; + }; + + config { + pins = "gpio101","gpio102"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio101","gpio102"; + function = "cci_i2c"; + }; + + config { + pins = "gpio101","gpio102"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio103","gpio104"; + function = "cci_i2c"; + }; + + config { + pins = "gpio103","gpio104"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio103","gpio104"; + function = "cci_i2c"; + }; + + config { + pins = "gpio103","gpio104"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_active: cci2_active { + mux { + /* CLK, DATA */ + pins = "gpio105","gpio106"; + function = "cci_i2c"; + }; + + config { + pins = "gpio105","gpio106"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_suspend: cci2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio105","gpio106"; + function = "cci_i2c"; + }; + + config { + pins = "gpio105","gpio106"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_active: cci3_active { + mux { + /* CLK, DATA */ + pins = "gpio107","gpio108"; + function = "cci_i2c"; + }; + + config { + pins = "gpio107","gpio108"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_suspend: cci3_suspend { + mux { + /* CLK, DATA */ + pins = "gpio107","gpio108"; + function = "cci_i2c"; + }; + + config { + pins = "gpio107","gpio108"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + tsif0_signals_active: tsif0_signals_active { + tsif1_clk { + pins = "gpio69"; /* TSIF0 CLK */ + function = "tsif0_clk"; + }; + + tsif1_en { + pins = "gpio70"; /* TSIF0 Enable */ + function = "tsif0_en"; + }; + + tsif1_data { + pins = "gpio71"; /* TSIF0 DATA */ + function = "tsif0_data"; + }; + + signals_cfg { + pins = "gpio69", "gpio70", "gpio71"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + /* sync signal is only used if configured to mode-2 */ + tsif0_sync_active: tsif0_sync_active { + tsif1_sync { + pins = "gpio72"; /* TSIF0 SYNC */ + function = "tsif0_sync"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + tsif1_signals_active: tsif1_signals_active { + tsif2_clk { + pins = "gpio73"; /* TSIF1 CLK */ + function = "tsif1_clk"; + }; + + tsif2_en { + pins = "gpio74"; /* TSIF1 Enable */ + function = "tsif1_en"; + }; + + tsif2_data { + pins = "gpio75"; /* TSIF1 DATA */ + function = "tsif1_data"; + }; + + signals_cfg { + pins = "gpio73", "gpio74", "gpio75"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + /* sync signal is only used if configured to mode-2 */ + tsif1_sync_active: tsif1_sync_active { + tsif2_sync { + pins = "gpio76"; /* TSIF1 SYNC */ + function = "tsif1_sync"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + sde_led_driver_en1_gpio: sde_led_driver_en1_gpio { + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + bias-pull-down; + drive-strength = <16>; + }; + }; + + sde_led_driver_en2_gpio: sde_led_driver_en2_gpio { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + bias-pull-down; + drive-strength = <16>; + }; + }; + + sde_led_5v_en_gpio: sde_led_5v_en_gpio { + mux { + pins = "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio134"; + bias-pull-down; + drive-strength = <16>; + }; + }; + + sde_display_1p8_en_gpio: sde_display_1p8_en_gpio { + mux { + pins = "gpio133"; + function = "gpio"; + }; + + config { + pins = "gpio133"; + bias-pull-down; + drive-strength = <16>; + }; + }; + + cam_sensor_6dof_vana_active: cam_sensor_6dof_vana_active { + /* AVDD LDO */ + mux { + pins = "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio84"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_6dof_vana_suspend: cam_sensor_6dof_vana_suspend { + /* AVDD LDO */ + mux { + pins = "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio84"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_6dof_vdig_active: cam_sensor_6dof_vdig_active { + /* VDIG LDO */ + mux { + pins = "gpio82"; + function = "gpio"; + }; + + config { + pins = "gpio82"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_6dof_vdig_suspend: cam_sensor_6dof_vdig_suspend { + /* VDIG LDO */ + mux { + pins = "gpio82"; + function = "gpio"; + }; + + config { + pins = "gpio82"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_6dof_vio_active: cam_sensor_6dof_vio_active { + /* VIO LDO */ + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_6dof_vio_suspend: cam_sensor_6dof_vio_suspend { + /* VIO LDO */ + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_et_vana_active: cam_sensor_et_vana_active { + /* AVDD LDO */ + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_et_vana_suspend: cam_sensor_et_vana_suspend { + /* AVDD LDO */ + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_et_vio_active: cam_sensor_et_vio_active { + /* VIO LDO */ + mux { + pins = "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio145"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_et_vio_suspend: cam_sensor_et_vio_suspend { + /* VIO LDO */ + mux { + pins = "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio145"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rgb_vana_active: cam_sensor_rgb_vana_active { + mux { + pins = "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio117"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rgb_vana_suspend: cam_sensor_rgb_vana_suspend { + mux { + pins = "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio117"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rgb_vio_active: cam_sensor_rgb_vio_active { + mux { + pins = "gpio116"; + function = "gpio"; + }; + + config { + pins = "gpio116"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rgb_vio_suspend: cam_sensor_rgb_vio_suspend { + mux { + pins = "gpio116"; + function = "gpio"; + }; + + config { + pins = "gpio116"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rgb_vdig_active: cam_sensor_rgb_vdig_active { + mux { + pins = "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio115"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rgb_vdig_suspend: cam_sensor_rgb_vdig_suspend { + mux { + pins = "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio115"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_etleft: cam_sensor_active_etleft { + /* RESET REAR */ + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_etleft: cam_sensor_suspend_etleft { + /* RESET REAR */ + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_etright: cam_sensor_active_etright { + /* RESET REAR */ + mux { + pins = "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio92"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_etright: cam_sensor_suspend_etright { + /* RESET REAR */ + mux { + pins = "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio92"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_6dofleft: cam_sensor_active_6dofleft { + /* RESET REAR */ + mux { + pins = "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio130"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_6dofleft: cam_sensor_suspend_6dofleft { + /* RESET REAR */ + mux { + pins = "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio130"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_6dofright: cam_sensor_active_6dofright { + /* RESET REAR */ + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_6dofright: cam_sensor_suspend_6dofright { + /* RESET REAR */ + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rgbright: cam_sensor_active_rgbright { + /* RESET REAR */ + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rgbright: cam_sensor_suspend_rgbright { + /* RESET REAR */ + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rgbleft: cam_sensor_active_rgbleft { + /* RESET REAR */ + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rgbleft: cam_sensor_suspend_rgbleft { + /* RESET REAR */ + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + bt_en_sleep: bt_en_sleep { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + + /* QUPv3_0 North SE0 mappings */ + qupv3_se0_i3c_pins: qupv3_se0_i3c_pins { + qupv3_se0_i3c_active: qupv3_se0_i3c_active { + mux { + pins = "gpio28", "gpio29"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se0_i3c_sleep: qupv3_se0_i3c_sleep { + mux { + pins = "gpio28", "gpio29"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <16>; + bias-pull-up; + }; + }; + }; + + /* QUPv3_0 North SE1 mappings */ + qupv3_se1_i3c_pins: qupv3_se1_i3c_pins { + qupv3_se1_i3c_active: qupv3_se1_i3c_active { + mux { + pins = "gpio4", "gpio5"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se1_i3c_sleep: qupv3_se1_i3c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <16>; + bias-pull-up; + }; + }; + }; + + /* SE 0 pin mappings */ + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio28", "gpio29"; + function = "qup0"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio28", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 1 pin mappings */ + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio4", "gpio5"; + function = "qup1"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + lt9611_pins: lt9611_pins { + mux { + pins = "gpio2", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio2", "gpio1"; + drive-strength = <8>; + bias-disable = <0>; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 111 NFC Read Interrupt */ + pins = "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 111 NFC Read Interrupt */ + pins = "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* 6: Enable 110: Firmware */ + pins = "gpio6", "gpio110"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio110"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* 6: Enable 110: Firmware */ + pins = "gpio6", "gpio110"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio110"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active: nfc_clk_req_active { + /* active state */ + mux { + /* GPIO 7: NFC CLOCK REQUEST */ + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend: nfc_clk_req_suspend { + /* sleep state */ + mux { + /* GPIO 7: NFC CLOCK REQUEST */ + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + /* SE 2 pin mappings */ + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio115", "gpio116"; + function = "qup2"; + }; + + config { + pins = "gpio115", "gpio116"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio115", "gpio116"; + function = "gpio"; + }; + + config { + pins = "gpio115", "gpio116"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 3 pin mappings */ + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_active: qupv3_se3_i2c_active { + mux { + pins = "gpio119", "gpio120"; + function = "qup3"; + }; + + config { + pins = "gpio119", "gpio120"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio119", "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio119", "gpio120"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 4 pin mappings */ + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_active: qupv3_se4_i2c_active { + mux { + pins = "gpio8", "gpio9"; + function = "qup4"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 5 pin mappings */ + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_active: qupv3_se5_i2c_active { + mux { + pins = "gpio12", "gpio13"; + function = "qup5"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 6 pin mappings */ + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_active: qupv3_se6_i2c_active { + mux { + pins = "gpio16", "gpio17"; + function = "qup6"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 7 pin mappings */ + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_active: qupv3_se7_i2c_active { + mux { + pins = "gpio20", "gpio21"; + function = "qup7"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio20", "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio28", "gpio29", "gpio30", + "gpio31"; + function = "qup0"; + }; + + config { + pins = "gpio28", "gpio29", "gpio30", + "gpio31"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio28", "gpio29", "gpio30", + "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio29", "gpio30", + "gpio31"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_active: qupv3_se1_spi_active { + mux { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + function = "qup1"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio115", "gpio116", "gpio117", + "gpio118"; + function = "qup2"; + }; + + config { + pins = "gpio115", "gpio116", "gpio117", + "gpio118"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio115", "gpio116", "gpio117", + "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio115", "gpio116", "gpio117", + "gpio118"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_active: qupv3_se3_spi_active { + mux { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + function = "qup3"; + }; + + config { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_active: qupv3_se4_spi_active { + mux { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + function = "qup4"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_active: qupv3_se5_spi_active { + mux { + pins = "gpio12", "gpio13", "gpio14", + "gpio15"; + function = "qup5"; + }; + + config { + pins = "gpio12", "gpio13", "gpio14", + "gpio15"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio12", "gpio13", "gpio14", + "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio12", "13", "gpio14", + "gpio15"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_active: qupv3_se6_spi_active { + mux { + pins = "gpio16", "gpio17", "gpio18", + "gpio19"; + function = "qup6"; + }; + + config { + pins = "gpio16", "gpio17", "gpio18", + "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio16", "gpio17", "gpio18", + "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17", "gpio18", + "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_active: qupv3_se7_spi_active { + mux { + pins = "gpio20", "gpio21", "gpio22", + "gpio23"; + function = "qup7"; + }; + + config { + pins = "gpio20", "gpio21", "gpio22", + "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio20", "gpio21", "gpio22", + "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21", "gpio22", + "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* QUPv3_1 South_1 SE mappings */ + /* SE 8 pin mappings */ + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_active: qupv3_se8_i2c_active { + mux { + pins = "gpio24", "gpio25"; + function = "qup8"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 9 pin mappings */ + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_active: qupv3_se9_i2c_active { + mux { + pins = "gpio125", "gpio126"; + function = "qup9"; + }; + + config { + pins = "gpio125", "gpio126"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio125", "gpio126"; + function = "gpio"; + }; + + config { + pins = "gpio125", "gpio126"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 10 pin mappings */ + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_active: qupv3_se10_i2c_active { + mux { + pins = "gpio129", "gpio130"; + function = "qup10"; + }; + + config { + pins = "gpio129", "gpio130"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio129", "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio129", "gpio130"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 11 pin mappings */ + qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { + qupv3_se11_i2c_active: qupv3_se11_i2c_active { + mux { + pins = "gpio60", "gpio61"; + function = "qup11"; + }; + + config { + pins = "gpio60", "gpio61"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio60", "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio60", "gpio61"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 12 pin mappings */ + qupv3_se12_i2c_pins: qupv3_se12_i2c_pins { + qupv3_se12_i2c_active: qupv3_se12_i2c_active { + mux { + pins = "gpio32", "gpio33"; + function = "qup12"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep { + mux { + pins = "gpio32", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 13 pin mappings */ + qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { + qupv3_se13_i2c_active: qupv3_se13_i2c_active { + mux { + pins = "gpio36", "gpio37"; + function = "qup13"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { + mux { + pins = "gpio36", "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_active: qupv3_se8_spi_active { + mux { + pins = "gpio24", "gpio25", "gpio26", + "gpio27"; + function = "qup8"; + }; + + config { + pins = "gpio24", "gpio25", "gpio26", + "gpio27"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio24", "gpio25", "gpio26", + "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25", "gpio26", + "gpio27"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_active: qupv3_se9_spi_active { + mux { + pins = "gpio125", "gpio126", "gpio127", + "gpio128"; + function = "qup9"; + }; + + config { + pins = "gpio125", "gpio126", "gpio127", + "gpio128"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio125", "gpio126", "gpio127", + "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio125", "gpio126", "gpio127", + "gpio128"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se10_spi_pins: qupv3_se10_spi_pins { + qupv3_se10_spi_active: qupv3_se10_spi_active { + mux { + pins = "gpio129", "gpio130", "gpio131", + "gpio132"; + function = "qup10"; + }; + + config { + pins = "gpio129", "gpio130", "gpio131", + "gpio132"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { + mux { + pins = "gpio129", "gpio130", "gpio131", + "gpio132"; + function = "gpio"; + }; + + config { + pins = "gpio129", "gpio130", "gpio131", + "gpio132"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se11_spi_pins: qupv3_se11_spi_pins { + qupv3_se11_spi_active: qupv3_se11_spi_active { + mux { + pins = "gpio60", "gpio61", "gpio62", + "gpio63"; + function = "qup11"; + }; + + config { + pins = "gpio60", "gpio61", "gpio62", + "gpio63"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { + mux { + pins = "gpio60", "gpio61", "gpio62", + "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio60", "gpio61", "gpio62", + "gpio63"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se12_spi_pins: qupv3_se12_spi_pins { + qupv3_se12_spi_active: qupv3_se12_spi_active { + mux { + pins = "gpio32", "gpio33", "gpio34", + "gpio35"; + function = "qup12"; + }; + + config { + pins = "gpio32", "gpio33", "gpio34", + "gpio35"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_sleep: qupv3_se12_spi_sleep { + mux { + pins = "gpio32", "gpio33", "gpio34", + "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33", "gpio34", + "gpio35"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se13_spi_pins: qupv3_se13_spi_pins { + qupv3_se13_spi_active: qupv3_se13_spi_active { + mux { + pins = "gpio36", "gpio37", "gpio38", + "gpio39"; + function = "qup13"; + }; + + config { + pins = "gpio36", "gpio37", "gpio38", + "gpio39"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_sleep: qupv3_se13_spi_sleep { + mux { + pins = "gpio36", "gpio37", "gpio38", + "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37", "gpio38", + "gpio39"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* QUPv3_2 South_2 SE mappings */ + /* SE 14 pin mappings */ + qupv3_se14_i2c_pins: qupv3_se14_i2c_pins { + qupv3_se14_i2c_active: qupv3_se14_i2c_active { + mux { + pins = "gpio40", "gpio41"; + function = "qup14"; + }; + + config { + pins = "gpio40", "gpio41"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep { + mux { + pins = "gpio40", "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio41"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 15 pin mappings */ + qupv3_se15_i2c_pins: qupv3_se15_i2c_pins { + qupv3_se15_i2c_active: qupv3_se15_i2c_active { + mux { + pins = "gpio44", "gpio45"; + function = "qup15"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep { + mux { + pins = "gpio44", "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 16 pin mappings */ + qupv3_se16_i2c_pins: qupv3_se16_i2c_pins { + qupv3_se16_i2c_active: qupv3_se16_i2c_active { + mux { + pins = "gpio48", "gpio49"; + function = "qup16"; + }; + + config { + pins = "gpio48", "gpio49"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se16_i2c_sleep: qupv3_se16_i2c_sleep { + mux { + pins = "gpio48", "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio49"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 17 pin mappings */ + qupv3_se17_i2c_pins: qupv3_se17_i2c_pins { + qupv3_se17_i2c_active: qupv3_se17_i2c_active { + mux { + pins = "gpio52", "gpio53"; + function = "qup17"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se17_i2c_sleep: qupv3_se17_i2c_sleep { + mux { + pins = "gpio52", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 18 pin mappings */ + qupv3_se18_i2c_pins: qupv3_se18_i2c_pins { + qupv3_se18_i2c_active: qupv3_se18_i2c_active { + mux { + pins = "gpio56", "gpio57"; + function = "qup18"; + }; + + config { + pins = "gpio56", "gpio57"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se18_i2c_sleep: qupv3_se18_i2c_sleep { + mux { + pins = "gpio56", "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio56", "gpio57"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 19 pin mappings */ + qupv3_se19_i2c_pins: qupv3_se19_i2c_pins { + qupv3_se19_i2c_active: qupv3_se19_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup19"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se19_i2c_sleep: qupv3_se19_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + qupv3_se14_spi_pins: qupv3_se14_spi_pins { + qupv3_se14_spi_active: qupv3_se14_spi_active { + mux { + pins = "gpio40", "gpio41", "gpio42", + "gpio43"; + function = "qup14"; + }; + + config { + pins = "gpio40", "gpio41", "gpio42", + "gpio43"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se14_spi_sleep: qupv3_se14_spi_sleep { + mux { + pins = "gpio40", "gpio41", "gpio42", + "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio41", "gpio42", + "gpio43"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se15_spi_pins: qupv3_se15_spi_pins { + qupv3_se15_spi_active: qupv3_se15_spi_active { + mux { + pins = "gpio44", "gpio45", "gpio46", + "gpio47"; + function = "qup15"; + }; + + config { + pins = "gpio44", "gpio45", "gpio46", + "gpio47"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_sleep: qupv3_se15_spi_sleep { + mux { + pins = "gpio44", "gpio45", "gpio46", + "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45", "gpio46", + "gpio47"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se16_spi_pins: qupv3_se16_spi_pins { + qupv3_se16_spi_active: qupv3_se16_spi_active { + mux { + pins = "gpio48", "gpio49", "gpio50", + "gpio51"; + function = "qup16"; + }; + + config { + pins = "gpio48", "gpio49", "gpio50", + "gpio51"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se16_spi_sleep: qupv3_se16_spi_sleep { + mux { + pins = "gpio48", "gpio49", "gpio50", + "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio49", "gpio50", + "gpio51"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se17_spi_pins: qupv3_se17_spi_pins { + qupv3_se17_spi_active: qupv3_se17_spi_active { + mux { + pins = "gpio52", "gpio53", "gpio54", + "gpio55"; + function = "qup17"; + }; + + config { + pins = "gpio52", "gpio53", "gpio54", + "gpio55"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se17_spi_sleep: qupv3_se17_spi_sleep { + mux { + pins = "gpio52", "gpio53", "gpio54", + "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53", "gpio54", + "gpio55"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se18_spi_pins: qupv3_se18_spi_pins { + qupv3_se18_spi_active: qupv3_se18_spi_active { + mux { + pins = "gpio56", "gpio57", "gpio58", + "gpio59"; + function = "qup18"; + }; + + config { + pins = "gpio56", "gpio57", "gpio58", + "gpio59"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se18_spi_sleep: qupv3_se18_spi_sleep { + mux { + pins = "gpio56", "gpio57", "gpio58", + "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio56", "gpio57", "gpio58", + "gpio59"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se19_spi_pins: qupv3_se19_spi_pins { + qupv3_se19_spi_active: qupv3_se19_spi_active { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "qup19"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se19_spi_sleep: qupv3_se19_spi_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + usb2_id_det_default: usb2_id_det_default { + config { + pins = "gpio91"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; + + wil6210_refclk_en_pin: wil6210_refclk_en_pin { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; +}; diff --git a/qcom/kona-v2.1.dtsi b/qcom/kona-v2.1.dtsi new file mode 100644 index 00000000..bc62b4c1 --- /dev/null +++ b/qcom/kona-v2.1.dtsi @@ -0,0 +1,8 @@ + +#include "kona-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. kona v2.1"; + compatible = "qcom,kona"; + qcom,msm-id = <356 0x20001>; +}; diff --git a/qcom/kona-v2.dtsi b/qcom/kona-v2.dtsi new file mode 100644 index 00000000..a8058ccc --- /dev/null +++ b/qcom/kona-v2.dtsi @@ -0,0 +1,23 @@ +#include "kona.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. kona v2"; + compatible = "qcom,kona"; + qcom,msm-id = <356 0x20000>; +}; + +&CPU4 { + dynamic-power-coefficient = <533>; +}; + +&CPU5 { + dynamic-power-coefficient = <533>; +}; + +&CPU6 { + dynamic-power-coefficient = <533>; +}; + +&CPU7 { + dynamic-power-coefficient = <642>; +}; diff --git a/qcom/kona.dtsi b/qcom/kona.dtsi new file mode 100644 index 00000000..4af2306a --- /dev/null +++ b/qcom/kona.dtsi @@ -0,0 +1,1108 @@ +#include +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. kona"; + compatible = "qcom,kona"; + qcom,msm-id = <356 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; + }; + + reserved_memory: reserved-memory { }; + + aliases { }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 4>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-level = <3>; + }; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 0 4>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_2>; + qcom,freq-domain = <&cpufreq_hw 0 4>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_200: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_200: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_3>; + qcom,freq-domain = <&cpufreq_hw 0 4>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_300: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_300: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_4>; + qcom,freq-domain = <&cpufreq_hw 1 4>; + capacity-dmips-mhz = <1894>; + dynamic-power-coefficient = <514>; + #cooling-cells = <2>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_400: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_400: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_5>; + qcom,freq-domain = <&cpufreq_hw 1 4>; + capacity-dmips-mhz = <1894>; + dynamic-power-coefficient = <514>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_500: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_500: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_6>; + qcom,freq-domain = <&cpufreq_hw 1 4>; + capacity-dmips-mhz = <1894>; + dynamic-power-coefficient = <514>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_600: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_600: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_7>; + qcom,freq-domain = <&cpufreq_hw 2 4>; + capacity-dmips-mhz = <1894>; + dynamic-power-coefficient = <598>; + #cooling-cells = <2>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_700: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_700: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + }; + + cluster2 { + core0 { + cpu = <&CPU7>; + }; + }; + }; + }; + + idle-states { + SILVER_OFF: silver-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <360>; + exit-latency-us = <531>; + min-residency-us = <3934>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + GOLD_OFF: gold-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <702>; + exit-latency-us = <1061>; + min-residency-us = <4488>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + APSS_OFF: cluster-e3 { /* LLCC off, AOSS sleep */ + compatible = "domain-idle-state"; + idle-state-name = "llcc-off"; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9987>; + arm,psci-suspend-param = <0x4100c344>; + }; + }; + + soc: soc { + cpufreq_hw: qcom,cpufreq-hw { + compatible = "qcom,cpufreq-epss"; + reg = <0x18591000 0x1000>, <0x18592000 0x1000>, + <0x18593000 0x1000>; + reg-names = "freq-domain0", "freq-domain1", + "freq-domain2"; + + //clocks = <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GPLL0>; + //clock-names = "xo", "alternate"; + + qcom,lut-row-size = <4>; + qcom,skip-enable-check; + + #freq-domain-cells = <2>; + + cpu7_notify: cpu7-notify { + qcom,cooling-cpu = <&CPU7>; + #cooling-cells = <2>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + firmware: firmware { + qcom_scm { + compatible = "qcom,scm"; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo,recovery"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; + }; +}; + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp_region@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_region@80700000 { + no-map; + reg = <0x0 0x80700000 0x0 0x160000>; + }; + + cmd_db: reserved-memory@80860000 { + reg = <0x0 0x80860000 0x0 0x20000>; + compatible = "qcom,cmd-db"; + no-map; + }; + + smem_mem: smem_region@80900000 { + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + }; + + removed_mem: removed_region@80b00000 { + no-map; + reg = <0x0 0x80b00000 0x0 0x5300000>; + }; + + pil_camera_mem: pil_camera_region@86200000 { + no-map; + reg = <0x0 0x86200000 0x0 0x500000>; + }; + + pil_wlan_fw_mem: pil_wlan_fw_region@86700000 { + no-map; + reg = <0x0 0x86700000 0x0 0x100000>; + }; + + pil_ipa_fw_mem: pil_ipa_fw_region@86800000 { + no-map; + reg = <0x0 0x86800000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: pil_ipa_gsi_region@86810000 { + no-map; + reg = <0x0 0x86810000 0x0 0xa000>; + }; + + pil_gpu_mem: pil_gpu_region@8681a000 { + no-map; + reg = <0x0 0x8681a000 0x0 0x2000>; + }; + + pil_npu_mem: pil_npu_region@86900000 { + no-map; + reg = <0x0 0x86900000 0x0 0x500000>; + }; + + video_mem: video_region@86e00000 { + no-map; + reg = <0x0 0x86e00000 0x0 0x500000>; + }; + + pil_cvp_mem: pil_cvp_region@87300000 { + no-map; + reg = <0x0 0x87300000 0x0 0x500000>; + }; + + pil_cdsp_mem: pil_cdsp_region@87800000 { + no-map; + reg = <0x0 0x87800000 0x0 0x1400000>; + }; + + pil_slpi_mem: pil_slpi_region@88c00000 { + no-map; + reg = <0x0 0x88c00000 0x0 0x1500000>; + }; + + pil_adsp_mem: pil_adsp_region@8a100000 { + no-map; + reg = <0x0 0x8a100000 0x0 0x1d00000>; + }; + + pil_spss_mem: pil_spss_region@8be00000 { + no-map; + reg = <0x0 0x8be00000 0x0 0x100000>; + }; + + cdsp_secure_heap: cdsp_secure_heap@8bf00000 { + no-map; + reg = <0x0 0x8bf00000 0x0 0x4600000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xC00000>; + }; + + sdsp_mem: sdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; + + cdsp_mem: cdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + + cont_splash_memory: cont_splash_region@9c000000 { + reg = <0x0 0x9c000000 0x0 0x02300000>; + label = "cont_splash_region"; + }; + + disp_rdump_memory: disp_rdump_region@9c000000 { + reg = <0x0 0x9c000000 0x0 0x00800000>; + label = "disp_rdump_region"; + }; + + dfps_data_memory: dfps_data_region@9e300000 { + reg = <0x0 0x9e300000 0x0 0x0100000>; + label = "dfps_data_region"; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x2800000>; + }; + + sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + secure_display_memory: secure_display_region { /* Secure UI */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xA400000>; + }; + + cnss_wlan_mem: cnss_wlan_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + + mailbox_mem: mailbox_region { + compatible = "shared-dma-pool"; + no-map; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x400000>; + size = <0x0 0x20000>; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + memtimer: timer@17c20000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c20000 0x1000>; + clock-frequency = <19200000>; + + frame@17c21000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = ; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = ; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = ; + reg = <0x17c27000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = ; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = ; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = ; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = ; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,kona-pdc"; + reg = <0xb220000 0x30000>, <0x17c000f0 0x60>; + qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>, <126 716 12>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + qcom,chd_silver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x18000058 0x18010058 + 0x18020058 0x18030058>; + qcom,config-arr = <0x18000060 0x18010060 + 0x18020060 0x18030060>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x18040058 0x18050058 + 0x18060058 0x18070058>; + qcom,config-arr = <0x18040060 0x18050060 + 0x18060060 0x18070060>; + }; + + cache-controller@9200000 { + //compatible = "qcom,kona-llcc"; + reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + cap-based-alloc-and-pwr-collapse; + }; + + wdog: qcom,wdt@17c10000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,wakeup-enable; + qcom,ipi-ping; + }; + + qcom,msm-imem@146bf000 { + compatible = "qcom,msm-imem"; + reg = <0x146bf000 0x1000>; + ranges = <0x0 0x146bf000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + qcom,mpm2-sleep-counter@c221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; + + qcom-secure-buffer { + compatible = "qcom,secure-buffer"; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c200_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c300_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c400_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c500_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c600_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c700_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + c0_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x130>; + }; + + c100_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x131>; + }; + + c200_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x132>; + }; + + c300_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x133>; + }; + + c400_scandump { + qcom,dump-size = <0x1a4c0>; + qcom,dump-id = <0x134>; + }; + + c500_scandump { + qcom,dump-size = <0x1a4c0>; + qcom,dump-id = <0x135>; + }; + + c600_scandump { + qcom,dump-size = <0x1a4c0>; + qcom,dump-id = <0x136>; + }; + + c700_scandump { + qcom,dump-size = <0x1a4c0>; + qcom,dump-id = <0x137>; + }; + + cpuss_reg { + qcom,dump-size = <0x30000>; + qcom,dump-id = <0xef>; + }; + + l1_icache0 { + qcom,dump-size = <0x10800>; + qcom,dump-id = <0x60>; + }; + + l1_icache100 { + qcom,dump-size = <0x10800>; + qcom,dump-id = <0x61>; + }; + + l1_icache200 { + qcom,dump-size = <0x10800>; + qcom,dump-id = <0x62>; + }; + + l1_icache300 { + qcom,dump-size = <0x10800>; + qcom,dump-id = <0x63>; + }; + + l1_icache400 { + qcom,dump-size = <0x26000>; + qcom,dump-id = <0x64>; + }; + + l1_icache500 { + qcom,dump-size = <0x26000>; + qcom,dump-id = <0x65>; + }; + + l1_icache600 { + qcom,dump-size = <0x26000>; + qcom,dump-id = <0x66>; + }; + + l1_icache700 { + qcom,dump-size = <0x26000>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x80>; + }; + + l1_dcache100 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x81>; + }; + + l1_dcache200 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x82>; + }; + + l1_dcache300 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x83>; + }; + + l1_dcache400 { + qcom,dump-size = <0x1A000>; + qcom,dump-id = <0x84>; + }; + + l1_dcache500 { + qcom,dump-size = <0x1A000>; + qcom,dump-id = <0x85>; + }; + + l1_dcache600 { + qcom,dump-size = <0x1A000>; + qcom,dump-id = <0x86>; + }; + + l1_dcache700 { + qcom,dump-size = <0x1A000>; + qcom,dump-id = <0x87>; + }; + + l1_itlb400 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x24>; + }; + + l1_itlb500 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x25>; + }; + + l1_itlb600 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x26>; + }; + + l1_itlb700 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x27>; + }; + + l1_dtlb400 { + qcom,dump-size = <0x480>; + qcom,dump-id = <0x44>; + }; + + l1_dtlb500 { + qcom,dump-size = <0x480>; + qcom,dump-id = <0x45>; + }; + + l1_dtlb600 { + qcom,dump-size = <0x480>; + qcom,dump-id = <0x46>; + }; + + l1_dtlb700 { + qcom,dump-size = <0x480>; + qcom,dump-id = <0x47>; + }; + + l2_cache400 { + qcom,dump-size = <0x68000>; + qcom,dump-id = <0xc4>; + }; + + l2_cache500 { + qcom,dump-size = <0x68000>; + qcom,dump-id = <0xc5>; + }; + + l2_cache600 { + qcom,dump-size = <0x68000>; + qcom,dump-id = <0xc6>; + }; + + l2_cache700 { + qcom,dump-size = <0xD0000>; + qcom,dump-id = <0xc7>; + }; + + l2_tlb0 { + qcom,dump-size = <0x6000>; + qcom,dump-id = <0x120>; + }; + + l2_tlb100 { + qcom,dump-size = <0x6000>; + qcom,dump-id = <0x121>; + }; + + l2_tlb200 { + qcom,dump-size = <0x6000>; + qcom,dump-id = <0x122>; + }; + + l2_tlb300 { + qcom,dump-size = <0x6000>; + qcom,dump-id = <0x123>; + }; + + l2_tlb400 { + qcom,dump-size = <0x7800>; + qcom,dump-id = <0x124>; + }; + + l2_tlb500 { + qcom,dump-size = <0x7800>; + qcom,dump-id = <0x125>; + }; + + l2_tlb600 { + qcom,dump-size = <0x7800>; + qcom,dump-id = <0x126>; + }; + + l2_tlb700 { + qcom,dump-size = <0x7800>; + qcom,dump-id = <0x127>; + }; + + gemnoc { + qcom,dump-size = <0x100000>; + qcom,dump-id = <0x162>; + }; + + mhm_scan { + qcom,dump-size = <0x20000>; + qcom,dump-id = <0x161>; + }; + + rpmh { + qcom,dump-size = <0x2000000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x80000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + etf_swao { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + etf_slpi { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf3>; + }; + + etfslpi_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x103>; + }; + + etf_lpass { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf4>; + }; + + etflpass_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x104>; + }; + }; + +}; + +#include "kona-pinctrl.dtsi" From 792c7b381a2a89c215eb3d1726bbffb14a685062 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Tue, 18 Oct 2022 13:22:48 +0530 Subject: [PATCH 30/41] bindings: interrupt-controller: Add compatible for kona pdc Document compatible for kona pdc irqchip. Change-Id: I1fbfbe959784ff9456ff23a0561d35b6d3a99be1 --- bindings/interrupt-controller/qcom,pdc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/interrupt-controller/qcom,pdc.txt b/bindings/interrupt-controller/qcom,pdc.txt index c16d168e..a2030839 100644 --- a/bindings/interrupt-controller/qcom,pdc.txt +++ b/bindings/interrupt-controller/qcom,pdc.txt @@ -27,6 +27,7 @@ Properties: - "qcom,sdxpinn-pdc": For SDXPINN - "qcom,lemans-pdc": For lemans - "qcom,sdxbaagha-pdc": For SDXBAAGHA + - "qcom,kona-pdc": For Kona - reg: Usage: required From 5184bcb8e28516e834422dba11df4cf5340a5ea6 Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Wed, 2 Nov 2022 15:00:02 +0800 Subject: [PATCH 31/41] ARM: dts: msm: update to correct regulator Update to correct regulator which kalama + pinn target used. Change-Id: Id51a650514a8accd70cf6cec8c4bc0cf2bb731c3 --- qcom/sdxpinn-external-soc.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxpinn-external-soc.dtsi b/qcom/sdxpinn-external-soc.dtsi index 731d27c6..00fbebde 100644 --- a/qcom/sdxpinn-external-soc.dtsi +++ b/qcom/sdxpinn-external-soc.dtsi @@ -31,8 +31,8 @@ qcom,ap2mdm-soft-reset-gpio = <&pm8550_gpios 1 0>; reg-names = "l10b"; - l10c-supply = <&L10B>; - l10c-uV-uA = <1200000 100000>; + l10b-supply = <&L10B>; + l10b-uV-uA = <1200000 100000>; qcom,esoc-skip-restart-for-mdm-crash; status = "ok"; From 298bb8e663c35b5b821c153059459a346d90f411 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Tue, 18 Oct 2022 13:23:35 +0530 Subject: [PATCH 32/41] ARM: dts: msm: Add RSC and PDC devices for kona Add apps and disp RSC devices. Also update the PDC device compatible and remove GPIO to PDC irq map from TLMM device. Change-Id: Ibc746de7766f57dea8c6768fad1dca2179f1efdc --- qcom/kona-pinctrl.dtsi | 80 ------------------------------------------ qcom/kona.dtsi | 48 ++++++++++++++++++++++++- 2 files changed, 47 insertions(+), 81 deletions(-) diff --git a/qcom/kona-pinctrl.dtsi b/qcom/kona-pinctrl.dtsi index d9a4e596..2f5ea535 100644 --- a/qcom/kona-pinctrl.dtsi +++ b/qcom/kona-pinctrl.dtsi @@ -9,86 +9,6 @@ #interrupt-cells = <2>; wakeup-parent = <&pdc>; qcom,gpios-reserved = <28 29 30 31 40 41 42 43>; - irqdomain-map = <0 0 &pdc 79 0>, - <1 0 &pdc 84 0>, - <2 0 &pdc 80 0>, - <3 0 &pdc 82 0>, - <4 0 &pdc 107 0>, - <7 0 &pdc 43 0>, - <11 0 &pdc 42 0>, - <14 0 &pdc 44 0>, - <15 0 &pdc 52 0>, - <19 0 &pdc 67 0>, - <23 0 &pdc 68 0>, - <24 0 &pdc 105 0>, - <27 0 &pdc 92 0>, - <28 0 &pdc 106 0>, - <31 0 &pdc 69 0>, - <35 0 &pdc 70 0>, - <39 0 &pdc 73 0>, - <40 0 &pdc 108 0>, - <43 0 &pdc 71 0>, - <45 0 &pdc 72 0>, - <47 0 &pdc 83 0>, - <51 0 &pdc 74 0>, - <55 0 &pdc 77 0>, - <59 0 &pdc 78 0>, - <63 0 &pdc 75 0>, - <64 0 &pdc 81 0>, - <65 0 &pdc 87 0>, - <66 0 &pdc 88 0>, - <67 0 &pdc 89 0>, - <68 0 &pdc 54 0>, - <70 0 &pdc 85 0>, - <77 0 &pdc 46 0>, - <80 0 &pdc 90 0>, - <81 0 &pdc 91 0>, - <83 0 &pdc 97 0>, - <84 0 &pdc 98 0>, - <86 0 &pdc 99 0>, - <88 0 &pdc 101 0>, - <89 0 &pdc 102 0>, - <92 0 &pdc 103 0>, - <93 0 &pdc 104 0>, - <100 0 &pdc 53 0>, - <103 0 &pdc 47 0>, - <104 0 &pdc 48 0>, - <108 0 &pdc 49 0>, - <109 0 &pdc 94 0>, - <110 0 &pdc 95 0>, - <111 0 &pdc 96 0>, - <112 0 &pdc 55 0>, - <113 0 &pdc 56 0>, - <118 0 &pdc 50 0>, - <121 0 &pdc 51 0>, - <122 0 &pdc 57 0>, - <123 0 &pdc 58 0>, - <124 0 &pdc 45 0>, - <126 0 &pdc 59 0>, - <128 0 &pdc 76 0>, - <129 0 &pdc 86 0>, - <132 0 &pdc 93 0>, - <133 0 &pdc 65 0>, - <134 0 &pdc 66 0>, - <136 0 &pdc 62 0>, - <137 0 &pdc 63 0>, - <138 0 &pdc 64 0>, - <142 0 &pdc 60 0>, - <143 0 &pdc 61 0>, - <147 0 &pdc 109 0>, /* bi_mx_lpass_1_aoss_mx */ - <150 0 &pdc 110 0>, - <157 0 &pdc 111 0>, - <158 0 &pdc 112 0>, - <160 0 &pdc 113 0>, - <162 0 &pdc 114 0>, - <164 0 &pdc 115 0>, - <166 0 &pdc 116 0>, - <167 0 &pdc 117 0>, - <175 0 &pdc 118 0>, - <177 0 &pdc 119 0>, - <179 0 &pdc 120 0>; - irqdomain-map-mask = <0xff 0>; - irqdomain-map-pass-thru = <0 0xff>; trigout_a: trigout_a { mux { diff --git a/qcom/kona.dtsi b/qcom/kona.dtsi index 4af2306a..b67f7598 100644 --- a/qcom/kona.dtsi +++ b/qcom/kona.dtsi @@ -664,8 +664,54 @@ interrupts = ; }; + apps_rsc: rsc@18200000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x18200000 0x10000>, + <0x18210000 0x10000>, + <0x18220000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + qcom,drv-count = <3>; + interrupts = , + , + ; + + apps_rsc_drv2: drv@2 { + qcom,drv-id = <2>; + qcom,tcs-offset = <0xd00>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + }; + }; + + disp_rsc: rsc@af20000 { + label = "disp_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0xaf20000 0x10000>; + reg-names = "drv-0"; + qcom,drv-count = <1>; + interrupts = ; + + disp_rsc_drv0: drv@0 { + qcom,drv-id = <0>; + qcom,tcs-offset = <0x1c00>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + }; + }; + pdc: interrupt-controller@b220000 { - compatible = "qcom,kona-pdc"; + compatible = "qcom,pdc", "qcom,kona-pdc"; reg = <0xb220000 0x30000>, <0x17c000f0 0x60>; qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>, <126 716 12>; #interrupt-cells = <2>; From 1ed3295cc683d117b2336b2fc055b1eae279d676 Mon Sep 17 00:00:00 2001 From: Yingjie Zhu Date: Thu, 3 Nov 2022 00:36:06 +0800 Subject: [PATCH 33/41] ARM: dts: msm: add Bluetooth related configuration in SA8195 1. Add Bluetooth UART alias for hsuart0. 2. Add CNSS power control nodes. Change-Id: I08c32ec8d5c7973637d700fbf5917cf08603bd07 --- qcom/sa8195p.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index 8ff30377..e381c9a9 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -6,6 +6,9 @@ model = "Qualcomm Technologies, Inc. SA8195P"; qcom,msm-name = "SA8195P"; qcom,msm-id = <405 0x20000>; + aliases { + hsuart0 = &qupv3_se17_4uart; + }; }; &soc { @@ -62,3 +65,28 @@ status= "ok"; }; + +/* Add CNSS power ctrl nodes specific to SA8195 */ +&soc { + /* PWR_CTR2_VDD_1P8 supply */ + vreg_conn_1p8: vreg_conn_1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + pinctrl-names = "default"; + pinctrl-0 = <&conn_power_1p8_active>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 173 0>; + }; + + /* PWR_CTR1_VDD_PA supply */ + vreg_conn_pa: vreg_conn_pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + pinctrl-names = "default"; + pinctrl-0 = <&conn_power_pa_active>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 174 0>; + }; +}; From b0b0474254e148c48f701b2ff3a2a9595a793943 Mon Sep 17 00:00:00 2001 From: lixiang Date: Fri, 4 Nov 2022 14:25:54 +0800 Subject: [PATCH 34/41] ARM: dts: msm: Remove the HAB physical channel node for CLK mmidgrp800 used by clk is not needed anymore. Remove it from HAB device tree nodes. Change-Id: I11e67cf441403969c25a7f3c9890d5a4315b8499 --- qcom/quin-vm-common.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index e4871fd5..85b07256 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -171,12 +171,6 @@ remote-vmids = <0>; }; - mmidgrp800: mmidgrp800 { - grp-start-id = <800>; - role = "fe"; - remote-vmids = <0>; - }; - mmidgrp900: mmidgrp900 { grp-start-id = <900>; role = "fe"; From 97cda4b94574877b74c559e99b4ad9d19a626a73 Mon Sep 17 00:00:00 2001 From: Zou Shunxiang Date: Thu, 27 Oct 2022 10:55:24 +0800 Subject: [PATCH 35/41] ARM: dts: msm: Add support for DMA Heaps of Direwolf LVGVM Add support for display DMA heaps for Direwolf LVGVM. Change-Id: I107092abbab15c347595dd16926042438b90f95e --- qcom/direwolf-vm-lv.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/qcom/direwolf-vm-lv.dtsi b/qcom/direwolf-vm-lv.dtsi index c7c4f15c..7e6cf28a 100644 --- a/qcom/direwolf-vm-lv.dtsi +++ b/qcom/direwolf-vm-lv.dtsi @@ -1,3 +1,22 @@ +&reserved_memory { + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x0a000000>; + }; +}; + +&qcom_dma_heaps { + qcom,display { + qcom,dma-heap-name = "qcom,display"; + qcom,dma-heap-type = ; + qcom,max-align = <9>; + memory-region = <&secure_display_memory>; + }; +}; + &soc { }; From f4d65850e0f494415a38a2bfcb51d4f1e250958a Mon Sep 17 00:00:00 2001 From: Naveen Kumar Goud Arepalli Date: Wed, 2 Nov 2022 20:19:24 +0530 Subject: [PATCH 36/41] ARM: dts: msm: Enable nand smmu for hlos bam pipes Enable nand smmu for only hlos bam pipes 0x7 enables mask for both hlos and modem 0x3 enables mask for only hlos bam pipes. Change-Id: I3d05e575bf327f29445db5284d31c2eb7ee3a04b --- qcom/sa410m.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sa410m.dtsi b/qcom/sa410m.dtsi index e5a4a65b..96aa915d 100644 --- a/qcom/sa410m.dtsi +++ b/qcom/sa410m.dtsi @@ -767,7 +767,7 @@ /* Voting for max b/w on PNOC bus for now */ <1057800 725760>; - iommus = <&apps_smmu 0x100 0x7>; + iommus = <&apps_smmu 0x100 0x3>; qcom,iommu-dma = "bypass"; status = "disabled"; }; From a9e419ef8045f33bae08ed1a4e2158abf00a8aeb Mon Sep 17 00:00:00 2001 From: Shivangi Kesharwani Date: Thu, 3 Nov 2022 12:19:21 +0530 Subject: [PATCH 37/41] ARM: dts: qcom: Add dts entry to create heap regions for qseecom Add dts entry to create heap qseecom_mem, qseecom_ta_mem, user_contig_mem Change-Id: I95d1fd33087fed7646e4a8c38cf32b977774f958 --- qcom/monaco.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index b46d6e53..372c71b5 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -524,6 +524,9 @@ reg = <0x61800000 0x2100000>; reg-names = "secapp-region"; memory-region = <&qseecom_mem>; + qseecom_mem = <&qseecom_mem>; + qseecom_ta_mem = <&qseecom_ta_mem>; + user_contig_mem = <&user_contig_mem>; qcom,hlos-num-ce-hw-instances = <1>; qcom,hlos-ce-hw-instance = <0>; qcom,qsee-ce-hw-instance = <0>; From 8f32b7bb5c838c7fbabfc0ac72f1e58e3d2e39a2 Mon Sep 17 00:00:00 2001 From: Anant Goel Date: Mon, 7 Nov 2022 21:57:45 -0800 Subject: [PATCH 38/41] ARM: dts: msm: Add handoff SMRs for the Auto VM platform Add the handoff SMRs required for the Auto VM platform to ensure proper context bank allocations. Change-Id: Iceee8d81e8e8ff3117d25cfd22464651e6029dce --- bindings/iommu/arm,smmu.txt | 4 ++++ qcom/sa8155-vm.dtsi | 2 ++ 2 files changed, 6 insertions(+) diff --git a/bindings/iommu/arm,smmu.txt b/bindings/iommu/arm,smmu.txt index c886bfb6..a923cb55 100644 --- a/bindings/iommu/arm,smmu.txt +++ b/bindings/iommu/arm,smmu.txt @@ -185,6 +185,10 @@ conditions. - qcom,num-smr-override: Optional integer. See qcom,num-context-banks-override. +- qcom,multi-match-handoff-smr: + Optional property. Should be included if one handoff SMR matches + multiple SMRs. + ** Deprecated properties: - mmu-masters (deprecated in favour of the generic "iommus" binding) : diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index b3c4047a..6646a79d 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -182,6 +182,8 @@ #iommu-cells = <2>; qcom,skip-init; qcom,use-3-lvl-tables; + qcom,handoff-smrs = <0xffff 0x0>; + qcom,multi-match-handoff-smr; qcom,disable-atos; #global-interrupts = <1>; #size-cells = <1>; From a8a9c53ed35c3ab29720230d95d6446f6d2426ef Mon Sep 17 00:00:00 2001 From: Zihang Hu Date: Fri, 28 Oct 2022 13:18:22 +0530 Subject: [PATCH 39/41] ARM: dts: msm: Add kona-regulators.dtsi for kona iot target Add kona-regulators.dtsi to enable regulator. Change-Id: I74e2c8c1d3018834f09afc58618916000af0e5ea --- qcom/kona-regulators.dtsi | 937 ++++++++++++++++++++++++++++++++++++++ qcom/kona.dtsi | 1 + 2 files changed, 938 insertions(+) create mode 100644 qcom/kona-regulators.dtsi diff --git a/qcom/kona-regulators.dtsi b/qcom/kona-regulators.dtsi new file mode 100644 index 00000000..c4f48209 --- /dev/null +++ b/qcom/kona-regulators.dtsi @@ -0,0 +1,937 @@ +#include + +/* RPMh regulators */ +&apps_rsc_drv2 { + /* PM8150A S3 = VDD_MX supply */ + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mx.lvl"; + proxy-supply = <&VDD_MX_LEVEL>; + + VDD_MX_LEVEL: S3C_LEVEL: + pm8150a_s3_level: regulator-pm8150a-s3-level { + regulator-name = "pm8150a_s3_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + + VDD_MX_LEVEL_AO: S3C_LEVEL_AO: + pm8150a_s3_level_ao: regulator-pm8150a-s3-level-ao { + regulator-name = "pm8150a_s3_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + + VDD_MX_MMCX_SUPPLY_LEVEL: regulator-pm8150a-s3-mmcx-sup-level { + regulator-name = "pm8150a_s3_mmcx_sup_level"; + qcom,set = ; + pm8150a_s3_mmcx_sup_level-parent-supply = + <&VDD_CX_MMCX_SUPPLY_LEVEL>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + /* PM8150 S3 + S2 + S1 = VDD_CX supply */ + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "cx.lvl"; + proxy-supply = <&VDD_CX_MMCX_SUPPLY_LEVEL>; + + VDD_CX_LEVEL: S3A_LEVEL: + pm8150_s3_level: regulator-pm8150-s3-level { + regulator-name = "pm8150_s3_level"; + qcom,set = ; + pm8150_s3_level-parent-supply = <&VDD_MX_LEVEL>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + VDD_CX_LEVEL_AO: S3A_LEVEL_AO: + pm8150_s3_level_ao: regulator-pm8150-s3-level-ao { + regulator-name = "pm8150_s3_level_ao"; + qcom,set = ; + pm8150_s3_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + VDD_CX_MMCX_SUPPLY_LEVEL: regulator-pm8150-s3-mmcx-sup-level { + regulator-name = "pm8150_s3_mmcx_sup_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage + = ; + }; + }; + + rpmh-regulator-smpa4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpa4"; + S4A: pm8150_s4: regulator-pm8150-s4 { + regulator-name = "pm8150_s4"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1920000>; + qcom,init-voltage = <1800000>; + }; + }; + + rpmh-regulator-smpa5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpa5"; + S5A: pm8150_s5: regulator-pm8150-s5 { + regulator-name = "pm8150_s5"; + qcom,set = ; + regulator-min-microvolt = <1824000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1824000>; + }; + }; + + rpmh-regulator-smpa6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpa6"; + S6A: pm8150_s6: regulator-pm8150-s6 { + regulator-name = "pm8150_s6"; + qcom,set = ; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1128000>; + qcom,init-voltage = <600000>; + }; + }; + + rpmh-regulator-ldoa2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L2A: pm8150_l2: regulator-pm8150-l2 { + regulator-name = "pm8150_l2"; + qcom,set = ; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + qcom,init-voltage = <3072000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L3A: pm8150_l3: regulator-pm8150-l3 { + regulator-name = "pm8150_l3"; + qcom,set = ; + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <932000>; + qcom,init-voltage = <928000>; + qcom,init-mode = ; + }; + }; + + /* PM8150 L4 = VDD_SSC_MX supply */ + rpmh-regulator-lmxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lmx.lvl"; + L4A_LEVEL: pm8150_l4_level: regulator-pm8150-l4-level { + regulator-name = "pm8150_l4_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level + = ; + }; + }; + + rpmh-regulator-ldoa5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + proxy-supply = <&pm8150_l5>; + L5A: pm8150_l5: regulator-pm8150-l5 { + regulator-name = "pm8150_l5"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <100000>; + }; + + L5A_AO: pm8150_l5_ao: regulator-pm8150-l5-ao { + regulator-name = "pm8150_l5_ao"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + + regulator-pm8150-l5-so { + regulator-name = "pm8150_l5_so"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + qcom,init-enable = <0>; + }; + }; + + rpmh-regulator-ldoa6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L6A: pm8150_l6: regulator-pm8150-l6 { + regulator-name = "pm8150_l6"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L7A: pm8150_l7: regulator-pm8150-l7 { + regulator-name = "pm8150_l7"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + proxy-supply = <&pm8150_l9>; + L9A: pm8150_l9: regulator-pm8150-l9 { + regulator-name = "pm8150_l9"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <100000>; + }; + }; + + rpmh-regulator-ldoa10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L10A: pm8150_l10: regulator-pm8150-l10 { + regulator-name = "pm8150_l10"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + /* PM8150 L11 = VDD_SSC_CX supply */ + rpmh-regulator-lcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lcx.lvl"; + L11A_LEVEL: pm8150_l11_level: regulator-pm8150-l11-level { + regulator-name = "pm8150_l11_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + rpmh-regulator-ldoa12 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L12A: pm8150_l12: regulator-pm8150-l12 { + regulator-name = "pm8150_l12"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + + L12A_AO: pm8150_l12_ao: regulator-pm8150-l12-ao { + regulator-name = "pm8150_l12_ao"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + + regulator-pm8150-l12-so { + regulator-name = "pm8150_l12_so"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + qcom,init-enable = <0>; + }; + }; + + rpmh-regulator-ldoa13 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L13A: pm8150_l13: regulator-pm8150-l13 { + regulator-name = "pm8150_l13"; + qcom,set = ; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + qcom,init-voltage = <3008000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa14 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa14"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + proxy-supply = <&pm8150_l14>; + L14A: pm8150_l14: regulator-pm8150-l14 { + regulator-name = "pm8150_l14"; + qcom,set = ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <62000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1880000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa15 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L15A: pm8150_l15: regulator-pm8150-l15 { + regulator-name = "pm8150_l15"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa16 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L16A: pm8150_l16: regulator-pm8150-l16 { + regulator-name = "pm8150_l16"; + qcom,set = ; + regulator-min-microvolt = <3024000>; + regulator-max-microvolt = <3304000>; + qcom,init-voltage = <3024000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa17 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L17A: pm8150_l17: regulator-pm8150-l17 { + regulator-name = "pm8150_l17"; + qcom,set = ; + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3008000>; + qcom,init-voltage = <2496000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa18 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoa18"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L18A: pm8150_l18: regulator-pm8150-l18 { + regulator-name = "pm8150_l18"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <920000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + /* PM8150A S1 + S2 = VDD_GFX supply */ + rpmh-regulator-gfxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "gfx.lvl"; + VDD_GFX_LEVEL: S1C_LEVEL: + pm8150a_s1_level: regulator-pm8150a-s1-level { + regulator-name = "pm8150a_s1_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + /* PM8150A S4 + S5 = VDD_MMCX supply */ + rpmh-regulator-mmcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mmcx.lvl"; + proxy-supply = <&VDD_MMCX_LEVEL>; + + VDD_MMCX_LEVEL: S4C_LEVEL: + pm8150a_s4_level: regulator-pm8150a-s4-level { + regulator-name = "pm8150a_s4_level"; + qcom,set = ; + pm8150a_s4_level-parent-supply = <&VDD_MX_MMCX_SUPPLY_LEVEL>; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage + = ; + }; + + VDD_MMCX_LEVEL_AO: S4C_LEVEL_AO: + pm8150a_s4_level_ao: regulator-pm8150a-s4-level-ao { + regulator-name = "pm8150a_s4_level_ao"; + qcom,set = ; + pm8150a_s4_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + regulator-pm8150a-s4-level-so { + regulator-name = "pm8150a_s4_level_so"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + /* PM8150A S6 = VDD_EBI supply */ + rpmh-regulator-ebilvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "ebi.lvl"; + S6C_LEVEL: pm8150a_s6_level: regulator-pm8150a-s6-level { + regulator-name = "pm8150a_s6_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + rpmh-regulator-smpc7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc7"; + S7C: pm8150a_s7: regulator-pm8150a-s7 { + regulator-name = "pm8150a_s7"; + qcom,set = ; + regulator-min-microvolt = <348000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <348000>; + }; + }; + + rpmh-regulator-smpc8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc8"; + qcom,regulator-type = "pmic5-hfsmps"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 200000>; + S8C: pm8150a_s8: regulator-pm8150a-s8 { + regulator-name = "pm8150a_s8"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc1"; + qcom,regulator-type = "pmic5-ldo"; + L1C: pm8150a_l1: regulator-pm8150a-l1 { + regulator-name = "pm8150a_l1"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + }; + }; + + rpmh-regulator-ldoc2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L2C: pm8150a_l2: regulator-pm8150a-l2 { + regulator-name = "pm8150a_l2"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L3C: pm8150a_l3: regulator-pm8150a-l3 { + regulator-name = "pm8150a_l3"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L4C: pm8150a_l4: regulator-pm8150a-l4 { + regulator-name = "pm8150a_l4"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L5C: pm8150a_l5: regulator-pm8150a-l5 { + regulator-name = "pm8150a_l5"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L6C: pm8150a_l6: regulator-pm8150a-l6 { + regulator-name = "pm8150a_l6"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L7C: pm8150a_l7: regulator-pm8150a-l7 { + regulator-name = "pm8150a_l7"; + qcom,set = ; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + qcom,init-voltage = <2856000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc8"; + qcom,regulator-type = "pmic5-ldo"; + L8C: pm8150a_l8: regulator-pm8150a-l8 { + regulator-name = "pm8150a_l8"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + }; + }; + + rpmh-regulator-ldoc9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L9C: pm8150a_l9: regulator-pm8150a-l9 { + regulator-name = "pm8150a_l9"; + qcom,set = ; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <2704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L10C: pm8150a_l10: regulator-pm8150a-l10 { + regulator-name = "pm8150a_l10"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + proxy-supply = <&pm8150a_l11>; + L11C: pm8150a_l11: regulator-pm8150a-l11 { + regulator-name = "pm8150a_l11"; + qcom,set = ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <857000>; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3304000>; + qcom,init-voltage = <3104000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-bobc1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "bobc1"; + qcom,regulator-type = "pmic5-bob"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1000000 2000000>; + qcom,send-defaults; + + BOB: pm8150a_bob: regulator-pm8150a-bob { + regulator-name = "pm8150a_bob"; + qcom,set = ; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + qcom,init-voltage = <3312000>; + qcom,init-mode = ; + }; + + BOB_AO: pm8150a_bob_ao: regulator-pm8150a-bob-ao { + regulator-name = "pm8150a_bob_ao"; + qcom,set = ; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + qcom,init-voltage = <3008000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-smpf1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpf1"; + S1F: pm8009_s1: regulator-pm8009-s1 { + regulator-name = "pm8009_s1"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + }; + }; + + rpmh-regulator-smpf2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpf2"; + S2F: pm8009_s2: regulator-pm8009-s2 { + regulator-name = "pm8009_s2"; + qcom,set = ; + regulator-min-microvolt = <512000>; + regulator-max-microvolt = <1100000>; + qcom,init-voltage = <512000>; + }; + }; + + rpmh-regulator-ldof1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldof1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L1F: pm8009_l1: regulator-pm8009-l1 { + regulator-name = "pm8009_l1"; + qcom,set = ; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + qcom,init-voltage = <1104000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldof2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldof2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L2F: pm8009_l2: regulator-pm8009-l2 { + regulator-name = "pm8009_l2"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldof3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldof3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L3F: pm8009_l3: regulator-pm8009-l3 { + regulator-name = "pm8009_l3"; + qcom,set = ; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + qcom,init-voltage = <1056000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldof5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldof5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L5F: pm8009_l5: regulator-pm8009-l5 { + regulator-name = "pm8009_l5"; + qcom,set = ; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + qcom,init-voltage = <2800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldof6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldof6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L6F: pm8009_l6: regulator-pm8009-l6 { + regulator-name = "pm8009_l6"; + qcom,set = ; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + qcom,init-voltage = <2800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldof7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldof7"; + qcom,regulator-type = "pmic5-ldo"; + L7F: pm8009_l7: regulator-pm8009-l7 { + regulator-name = "pm8009_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + }; + }; +}; + +&soc { + refgen: refgen-regulator@88e7000 { + compatible = "qcom,refgen-kona-regulator"; + reg = <0x88e7000 0x84>; + regulator-name = "refgen"; + regulator-enable-ramp-delay = <5>; + proxy-supply = <&refgen>; + qcom,proxy-consumer-enable; + }; +}; diff --git a/qcom/kona.dtsi b/qcom/kona.dtsi index b67f7598..388bedfb 100644 --- a/qcom/kona.dtsi +++ b/qcom/kona.dtsi @@ -1151,4 +1151,5 @@ }; +#include "kona-regulators.dtsi" #include "kona-pinctrl.dtsi" From b37a42cd978171e2e3d3e16bc1284fd13071c9bc Mon Sep 17 00:00:00 2001 From: congying Date: Wed, 9 Nov 2022 12:56:23 +0800 Subject: [PATCH 40/41] ARM: dts: msm: Update display FPS max level Update display FPS max level from 4 to 16, now display FPS had 10 level, so suggest change to 16. Change-Id: Id53fa83d10ce20f2d3cc3f5fb829cb22b4b64a90 --- qcom/kalama-thermal.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/kalama-thermal.dtsi b/qcom/kalama-thermal.dtsi index 249a8dc7..98d736da 100644 --- a/qcom/kalama-thermal.dtsi +++ b/qcom/kalama-thermal.dtsi @@ -221,7 +221,7 @@ compatible = "qcom,userspace-cooling-devices"; display_fps: display-fps { - qcom,max-level = <4>; + qcom,max-level = <16>; #cooling-cells = <2>; }; }; From d563f6faf08c0ff1290ba98745a7bf7043796b85 Mon Sep 17 00:00:00 2001 From: Balakrishna Godavarthi Date: Mon, 14 Mar 2022 22:05:46 +0530 Subject: [PATCH 41/41] ARM: dts: msm: Add support for BT control glink node This change add support to create device node for BT control glink node which used for communication between APPS and ADSP. Change-Id: Id038b15c2bf295cfd3bb310661e90500c0b1d69a --- qcom/kalama.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/kalama.dtsi b/qcom/kalama.dtsi index 73640d80..cf8fece2 100644 --- a/qcom/kalama.dtsi +++ b/qcom/kalama.dtsi @@ -2582,6 +2582,11 @@ qcom,glinkpkt-ch-name = "DATA11"; qcom,glinkpkt-dev-name = "smd11"; }; + qcom,glinkpkt-btoip_control { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "bt_cp_ctrl"; + qcom,glinkpkt-dev-name = "bt_cp_ctrl"; + }; }; qcom,glink {