From 843573c10d34f20c3b24d71c22d193f09ef12f07 Mon Sep 17 00:00:00 2001 From: Manisha Podhuturi Date: Thu, 2 Jun 2022 12:32:41 +0530 Subject: [PATCH] ARM: dts: msm: Add QUP node for SA8195 target Add I2C, SPI and UART QUP nodes for SA8195 target. Change-Id: I9804c79bc288790d4c49a2609d105f33119e2697 --- qcom/sa8195-qupv3.dtsi | 1071 +++++++++++++++++++++++++++++++++ qcom/sa8195-ssc-qupv3.dtsi | 117 ++++ qcom/sa8195p-adp-common.dtsi | 4 - qcom/sdmshrike-pinctrl.dtsi | 1094 +++++++++++++++++----------------- qcom/sdmshrike.dtsi | 23 +- 5 files changed, 1740 insertions(+), 569 deletions(-) create mode 100644 qcom/sa8195-qupv3.dtsi create mode 100644 qcom/sa8195-ssc-qupv3.dtsi diff --git a/qcom/sa8195-qupv3.dtsi b/qcom/sa8195-qupv3.dtsi new file mode 100644 index 00000000..747ba682 --- /dev/null +++ b/qcom/sa8195-qupv3.dtsi @@ -0,0 +1,1071 @@ +&soc { + /* QUPv3 West Instances + * West 0 : SE 0 + * West 1 : SE 1 + * West 2 : SE 2 + * West 3 : SE 3 + * West 4 : SE 4 + * West 5 : SE 5 + * West 6 : SE 6 + * West 7 : SE 7 + * + * QUPv3 East0 and East1 Instances + * East1 0 : SE 8 + * East1 1 : SE 9 + * East1 2 : SE 10 + * East1 3 : SE 11 + * East1 4 : SE 12 + * East1 5 : SE 16 + * East0 0 : SE 17 + * East0 1 : SE 18 + * East0 2 : SE 19 + * East0 3 : SE 13 + * East0 4 : SE 14 + * East0 5 : SE 15 + */ + + /*GPI Instance */ + gpi_dma0: qcom,gpi-dma@800000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x800000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x4d6 0x0>; + qcom,max-num-gpii = <13>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0xfa>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + dma-coherent; + status = "disabled"; + }; + + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x8c0000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x4c3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + + qupv3_se0_i2c: i2c@880000 { + compatible = "qcom,i2c-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se0_spi: spi@880000 { + compatible = "qcom,spi-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se1_spi: spi@884000 { + compatible = "qcom,spi-geni"; + reg = <0x884000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se2_spi: spi@888000 { + compatible = "qcom,spi-geni"; + reg = <0x888000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se3_spi: spi@88c000 { + compatible = "qcom,spi-geni"; + reg = <0x88c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@890000 { + compatible = "qcom,i2c-geni"; + reg = <0x890000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se4_spi: spi@890000 { + compatible = "qcom,spi-geni"; + reg = <0x890000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* HS UART Instance */ + qupv3_se4_4uart: qcom,qup_uart@890000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x890000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se4_default_ctsrtsrx>, + <&qupv3_se4_default_tx>; + pinctrl-1 = <&qupv3_se4_ctsrx>, <&qupv3_se4_rts>, + <&qupv3_se4_tx>; + pinctrl-2 = <&qupv3_se4_ctsrx>, <&qupv3_se4_rts>, + <&qupv3_se4_tx>; + pinctrl-3 = <&qupv3_se4_default_ctsrtsrx>,<&qupv3_se4_default_tx>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@894000 { + compatible = "qcom,i2c-geni"; + reg = <0x894000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se5_spi: spi@894000 { + compatible = "qcom,spi-geni"; + reg = <0x894000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@898000 { + compatible = "qcom,i2c-geni"; + reg = <0x898000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se6_spi: spi@898000 { + compatible = "qcom,spi-geni"; + reg = <0x898000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@89c000 { + compatible = "qcom,i2c-geni"; + reg = <0x89c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se7_spi: spi@89c000 { + compatible = "qcom,spi-geni"; + reg = <0x89c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; + + /* GPI Instance */ + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x616 0x0>; + qcom,max-num-gpii = <13>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0xfa>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + dma-coherent; + status = "disabled"; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x603 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + + qupv3_se8_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se8_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_active>; + pinctrl-1 = <&qupv3_se8_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se9_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se10_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se10_2uart: qcom,qup_uart@a88000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_2uart_active>; + pinctrl-1 = <&qupv3_se10_2uart_sleep>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se11_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_spi_active>; + pinctrl-1 = <&qupv3_se11_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se12_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_spi_active>; + pinctrl-1 = <&qupv3_se12_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* Debug UART Instance for CDP/MTP platform */ + qupv3_se12_2uart: qcom,qup_uart@a90000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa90000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_2uart_active>; + pinctrl-1 = <&qupv3_se12_2uart_sleep>; + status = "disabled"; + }; + + qupv3_se13_i2c: i2c@a94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_i2c_active>; + pinctrl-1 = <&qupv3_se13_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se13_spi: spi@a94000 { + compatible = "qcom,spi-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_spi_active>; + pinctrl-1 = <&qupv3_se13_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se13_2uart: qcom,qup_uart@a94000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa94000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_2uart_active>; + pinctrl-1 = <&qupv3_se13_2uart_sleep>; + status = "disabled"; + }; + }; + + /* GPI Instance */ + gpi_dma2: qcom,gpi-dma@c00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xc00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x7b6 0x0>; + qcom,max-num-gpii = <13>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0xfa>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + dma-coherent; + status = "disabled"; + }; + + /* QUPv3_2 wrapper instance */ + qupv3_2: qcom,qupv3_2_geni_se@cc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xcc0000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x7a3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + + qupv3_se14_i2c: i2c@c80000 { + compatible = "qcom,i2c-geni"; + reg = <0xc80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_i2c_active>; + pinctrl-1 = <&qupv3_se14_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se14_spi: spi@c80000 { + compatible = "qcom,spi-geni"; + reg = <0xc80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_spi_active>; + pinctrl-1 = <&qupv3_se14_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se15_i2c: i2c@c84000 { + compatible = "qcom,i2c-geni"; + reg = <0xc84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_i2c_active>; + pinctrl-1 = <&qupv3_se15_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se15_spi: spi@c84000 { + compatible = "qcom,spi-geni"; + reg = <0xc84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_spi_active>; + pinctrl-1 = <&qupv3_se15_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se16_i2c: i2c@c88000 { + compatible = "qcom,i2c-geni"; + reg = <0xc88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_i2c_active>; + pinctrl-1 = <&qupv3_se16_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se16_spi: spi@c88000 { + compatible = "qcom,spi-geni"; + reg = <0xc88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_spi_active>; + pinctrl-1 = <&qupv3_se16_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se17_i2c: i2c@c8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xc8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_i2c_active>; + pinctrl-1 = <&qupv3_se17_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se17_spi: spi@c8c000 { + compatible = "qcom,spi-geni"; + reg = <0xc8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_spi_active>; + pinctrl-1 = <&qupv3_se17_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* HS UART Instance */ + qupv3_se17_4uart: qcom,qup_uart@c8c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xc8c000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 46 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se17_default_ctsrtsrx>, + <&qupv3_se17_default_tx>; + pinctrl-1 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>, + <&qupv3_se17_tx>; + pinctrl-2 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>, + <&qupv3_se17_tx>; + pinctrl-3 = <&qupv3_se17_default_ctsrtsrx>,<&qupv3_se17_default_tx>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + qupv3_se18_i2c: i2c@c90000 { + compatible = "qcom,i2c-geni"; + reg = <0xc90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_i2c_active>; + pinctrl-1 = <&qupv3_se18_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se18_spi: spi@c90000 { + compatible = "qcom,spi-geni"; + reg = <0xc90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_spi_active>; + pinctrl-1 = <&qupv3_se18_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se19_i2c: i2c@c94000 { + compatible = "qcom,i2c-geni"; + reg = <0xc94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_i2c_active>; + pinctrl-1 = <&qupv3_se19_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se19_spi: spi@c94000 { + compatible = "qcom,spi-geni"; + reg = <0xc94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_spi_active>; + pinctrl-1 = <&qupv3_se19_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/sa8195-ssc-qupv3.dtsi b/qcom/sa8195-ssc-qupv3.dtsi new file mode 100644 index 00000000..81d8698e --- /dev/null +++ b/qcom/sa8195-ssc-qupv3.dtsi @@ -0,0 +1,117 @@ +&soc { + /* QUPv3_3 wrapper instance */ + qupv3_3: qcom,qupv3_3_geni_se@26c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x26c0000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&scc SCC_QUPV3_M_HCLK_CLK>, + <&scc SCC_QUPV3_S_HCLK_CLK>; + iommus = <&apps_smmu 0x4e3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + + qupv3_se20_i2c: i2c@2680000 { + compatible = "qcom,i2c-geni"; + reg = <0x2680000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&scc SCC_QUPV3_SE0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se20_i2c_active>; + pinctrl-1 = <&qupv3_se20_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se21_i2c: i2c@2684000 { + compatible = "qcom,i2c-geni"; + reg = <0x2684000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&scc SCC_QUPV3_SE1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_i2c_active>; + pinctrl-1 = <&qupv3_se21_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se21_spi: spi@2684000 { + compatible = "qcom,spi-geni"; + reg = <0x2684000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&scc SCC_QUPV3_SE1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_spi_active>; + pinctrl-1 = <&qupv3_se21_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se22_i2c: i2c@2688000 { + compatible = "qcom,i2c-geni"; + reg = <0x2688000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&scc SCC_QUPV3_SE2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se22_i2c_active>; + pinctrl-1 = <&qupv3_se22_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se22_spi: spi@2688000 { + compatible = "qcom,spi-geni"; + reg = <0x2688000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&scc SCC_QUPV3_SE2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_SENSORS_AHB &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se22_spi_active>; + pinctrl-1 = <&qupv3_se22_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/sa8195p-adp-common.dtsi b/qcom/sa8195p-adp-common.dtsi index 830d61f8..bbfa0b09 100644 --- a/qcom/sa8195p-adp-common.dtsi +++ b/qcom/sa8195p-adp-common.dtsi @@ -1,5 +1 @@ #include - -&uart2 { - status = "ok"; -}; diff --git a/qcom/sdmshrike-pinctrl.dtsi b/qcom/sdmshrike-pinctrl.dtsi index 6869825c..7b1a0636 100644 --- a/qcom/sdmshrike-pinctrl.dtsi +++ b/qcom/sdmshrike-pinctrl.dtsi @@ -4084,6 +4084,73 @@ }; }; + qupv3_se4_4uart_pins: qupv3_se4_4uart_pins { + qupv3_se4_default_ctsrtsrx: qupv3_se4_default_ctsrtsrx { + mux { + pins = "gpio51", "gpio52", "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio51", "gpio52", "gpio54"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se4_default_tx: qupv3_se4_default_tx { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se4_ctsrx: qupv3_se4_ctsrx { + mux { + pins = "gpio51", "gpio54"; + function = "qup4"; + }; + + config { + pins = "gpio51", "gpio54"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_rts: qupv3_se4_rts { + mux { + pins = "gpio52"; + function = "qup4"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se4_tx: qupv3_se4_tx { + mux { + pins = "gpio53"; + function = "qup4"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + /* SE 5 pin mappings */ qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { qupv3_se5_i2c_active: qupv3_se5_i2c_active { @@ -4451,6 +4518,34 @@ }; }; + qupv3_se10_2uart_pins: qupv3_se10_2uart_pins { + qupv3_se10_2uart_active: qupv3_se10_2uart_active { + mux { + pins = "gpio11", "gpio12"; + function = "qup10"; + }; + + config { + pins = "gpio11", "gpio12"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep { + mux { + pins = "gpio11", "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio11", "gpio12"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + /* SE 11 pin mappings */ qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { qupv3_se11_i2c_active: qupv3_se11_i2c_active { @@ -4573,435 +4668,6 @@ }; }; - /* SE 13 pin mappings */ - qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { - qupv3_se13_i2c_active: qupv3_se13_i2c_active { - mux { - pins = "gpio43", "gpio44"; - function = "qup13"; - }; - - config { - pins = "gpio43", "gpio44"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { - mux { - pins = "gpio43", "gpio44"; - function = "gpio"; - }; - - config { - pins = "gpio43", "gpio44"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se13_spi_pins: qupv3_se13_spi_pins { - qupv3_se13_spi_active: qupv3_se13_spi_active { - mux { - pins = "gpio43", "gpio44", "gpio45", - "gpio46"; - function = "qup13"; - }; - - config { - pins = "gpio43", "gpio44", "gpio45", - "gpio46"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se13_spi_sleep: qupv3_se13_spi_sleep { - mux { - pins = "gpio43", "gpio44", "gpio45", - "gpio46"; - function = "gpio"; - }; - - config { - pins = "gpio43", "gpio44", "gpio45", - "gpio46"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - - /* SE 14 pin mappings */ - qupv3_se14_i2c_pins: qupv3_se14_i2c_pins { - qupv3_se14_i2c_active: qupv3_se14_i2c_active { - mux { - pins = "gpio47", "gpio48"; - function = "qup14"; - }; - - config { - pins = "gpio47", "gpio48"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep { - mux { - pins = "gpio47", "gpio48"; - function = "gpio"; - }; - - config { - pins = "gpio47", "gpio48"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se14_spi_pins: qupv3_se14_spi_pins { - qupv3_se14_spi_active: qupv3_se14_spi_active { - mux { - pins = "gpio47", "gpio48", "gpio49", - "gpio50"; - function = "qup14"; - }; - - config { - pins = "gpio47", "gpio48", "gpio49", - "gpio50"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se14_spi_sleep: qupv3_se14_spi_sleep { - mux { - pins = "gpio47", "gpio48", "gpio49", - "gpio50"; - function = "gpio"; - }; - - config { - pins = "gpio47", "gpio48", "gpio49", - "gpio50"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - /* SE 15 pin mappings */ - qupv3_se15_i2c_pins: qupv3_se15_i2c_pins { - qupv3_se15_i2c_active: qupv3_se15_i2c_active { - mux { - pins = "gpio27", "gpio28"; - function = "qup15"; - }; - - config { - pins = "gpio27", "gpio28"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep { - mux { - pins = "gpio27", "gpio28"; - function = "gpio"; - }; - - config { - pins = "gpio27", "gpio28"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se15_spi_pins: qupv3_se15_spi_pins { - qupv3_se15_spi_active: qupv3_se15_spi_active { - mux { - pins = "gpio27", "gpio28", "gpio29", - "gpio30"; - function = "qup15"; - }; - - config { - pins = "gpio27", "gpio28", "gpio29", - "gpio30"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se15_spi_sleep: qupv3_se15_spi_sleep { - mux { - pins = "gpio27", "gpio28", "gpio29", - "gpio30"; - function = "gpio"; - }; - - config { - pins = "gpio27", "gpio28", "gpio29", - "gpio30"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - /* SE 16 pin mappings */ - qupv3_se16_i2c_pins: qupv3_se16_i2c_pins { - qupv3_se16_i2c_active: qupv3_se16_i2c_active { - mux { - pins = "gpio86", "gpio85"; - function = "qup16"; - }; - - config { - pins = "gpio86", "gpio85"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se16_i2c_sleep: qupv3_se16_i2c_sleep { - mux { - pins = "gpio86", "gpio85"; - function = "gpio"; - }; - - config { - pins = "gpio86", "gpio85"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se16_spi_pins: qupv3_se16_spi_pins { - qupv3_se16_spi_active: qupv3_se16_spi_active { - mux { - pins = "gpio83", "gpio84", "gpio85", - "gpio86"; - function = "qup16"; - }; - - config { - pins = "gpio83", "gpio84", "gpio85", - "gpio86"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se16_spi_sleep: qupv3_se16_spi_sleep { - mux { - pins = "gpio83", "gpio84", "gpio85", - "gpio86"; - function = "gpio"; - }; - - config { - pins = "gpio83", "gpio84", "gpio85", - "gpio86"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - /* SE 17 pin mappings */ - qupv3_se17_i2c_pins: qupv3_se17_i2c_pins { - qupv3_se17_i2c_active: qupv3_se17_i2c_active { - mux { - pins = "gpio55", "gpio56"; - function = "qup17"; - }; - - config { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se17_i2c_sleep: qupv3_se17_i2c_sleep { - mux { - pins = "gpio55", "gpio56"; - function = "gpio"; - }; - - config { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se17_spi_pins: qupv3_se17_spi_pins { - qupv3_se17_spi_active: qupv3_se17_spi_active { - mux { - pins = "gpio55", "gpio56", "gpio57", - "gpio58"; - function = "qup17"; - }; - - config { - pins = "gpio55", "gpio56", "gpio57", - "gpio58"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se17_spi_sleep: qupv3_se17_spi_sleep { - mux { - pins = "gpio55", "gpio56", "gpio57", - "gpio58"; - function = "gpio"; - }; - - config { - pins = "gpio55", "gpio56", "gpio57", - "gpio58"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - /* SE 18 pin mappings */ - qupv3_se18_i2c_pins: qupv3_se18_i2c_pins { - qupv3_se18_i2c_active: qupv3_se18_i2c_active { - mux { - pins = "gpio23", "gpio24"; - function = "qup18"; - }; - - config { - pins = "gpio23", "gpio24"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se18_i2c_sleep: qupv3_se18_i2c_sleep { - mux { - pins = "gpio23", "gpio24"; - function = "gpio"; - }; - - config { - pins = "gpio23", "gpio24"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se18_spi_pins: qupv3_se18_spi_pins { - qupv3_se18_spi_active: qupv3_se18_spi_active { - mux { - pins = "gpio23", "gpio24", "gpio25", - "gpio26"; - function = "qup18"; - }; - - config { - pins = "gpio23", "gpio24", "gpio25", - "gpio26"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se18_spi_sleep: qupv3_se18_spi_sleep { - mux { - pins = "gpio23", "gpio24", "gpio25", - "gpio26"; - function = "gpio"; - }; - - config { - pins = "gpio23", "gpio24", "gpio25", - "gpio26"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - /* SE 19 pin mappings */ - qupv3_se19_i2c_pins: qupv3_se19_i2c_pins { - qupv3_se19_i2c_active: qupv3_se19_i2c_active { - mux { - pins = "gpio181", "gpio182"; - function = "qup19"; - }; - - config { - pins = "gpio181", "gpio182"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se19_i2c_sleep: qupv3_se19_i2c_sleep { - mux { - pins = "gpio181", "gpio182"; - function = "gpio"; - }; - - config { - pins = "gpio181", "gpio182"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se19_spi_pins: qupv3_se19_spi_pins { - qupv3_se19_spi_active: qupv3_se19_spi_active { - mux { - pins = "gpio181", "gpio182", "gpio183", - "gpio184"; - function = "qup19"; - }; - - config { - pins = "gpio181", "gpio182", "gpio183", - "gpio184"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se19_spi_sleep: qupv3_se19_spi_sleep { - mux { - pins = "gpio181", "gpio182", "gpio183", - "gpio184"; - function = "gpio"; - }; - - config { - pins = "gpio181", "gpio182", "gpio183", - "gpio184"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - /* SE12 UART-2wire pin mappings */ qupv3_se12_2uart_pins: qupv3_se12_2uart_pins { qupv3_se12_2uart_active: qupv3_se12_2uart_active { @@ -5031,117 +4697,8 @@ }; }; - trigout_a: trigout_a { - mux { - pins = "gpio141"; - function = "qdss_cti"; - }; - - config { - pins = "gpio141"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se4_4uart_pins: qupv3_se4_4uart_pins { - qupv3_se4_default_ctsrtsrx: qupv3_se4_default_ctsrtsrx { - mux { - pins = "gpio51", "gpio52", "gpio54"; - function = "gpio"; - }; - - config { - pins = "gpio51", "gpio52", "gpio54"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - qupv3_se4_default_tx: qupv3_se4_default_tx { - mux { - pins = "gpio53"; - function = "gpio"; - }; - - config { - pins = "gpio53"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - qupv3_se4_ctsrx: qupv3_se4_ctsrx { - mux { - pins = "gpio51", "gpio54"; - function = "qup4"; - }; - - config { - pins = "gpio51", "gpio54"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se4_rts: qupv3_se4_rts { - mux { - pins = "gpio52"; - function = "qup4"; - }; - - config { - pins = "gpio52"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - qupv3_se4_tx: qupv3_se4_tx { - mux { - pins = "gpio53"; - function = "qup4"; - }; - - config { - pins = "gpio53"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - /* SE 10 pin mappings */ - qupv3_se10_2uart_pins: qupv3_se10_2uart_pins { - qupv3_se10_2uart_active: qupv3_se10_2uart_active { - mux { - pins = "gpio11", "gpio12"; - function = "qup10"; - }; - - config { - pins = "gpio11", "gpio12"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep { - mux { - pins = "gpio11", "gpio12"; - function = "gpio"; - }; - - config { - pins = "gpio11", "gpio12"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - - qupv3_se16_2uart_pins: qupv3_se16_2uart_pins { - qupv3_se16_2uart_active: qupv3_se16_2uart_active { + qupv3_se13_2uart_pins: qupv3_se13_2uart_pins { + qupv3_se13_2uart_active: qupv3_se13_2uart_active { mux { pins = "gpio83", "gpio84"; function = "qup16"; @@ -5154,7 +4711,7 @@ }; }; - qupv3_se16_2uart_sleep: qupv3_se16_2uart_sleep { + qupv3_se13_2uart_sleep: qupv3_se13_2uart_sleep { mux { pins = "gpio83", "gpio84"; function = "gpio"; @@ -5168,10 +4725,314 @@ }; }; - /* SE 13 UART 4-Wire pin mappings */ - qupv3_se13_4uart_pins: qupv3_se13_4uart_pins { - qupv3_se13_default_ctsrtsrx: - qupv3_se13_default_ctsrtsrx { + /* SE 13 pin mappings */ + qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { + qupv3_se13_i2c_active: qupv3_se13_i2c_active { + mux { + pins = "gpio86", "gpio85"; + function = "qup16"; + }; + + config { + pins = "gpio86", "gpio85"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { + mux { + pins = "gpio86", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio86", "gpio85"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se13_spi_pins: qupv3_se13_spi_pins { + qupv3_se13_spi_active: qupv3_se13_spi_active { + mux { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "qup16"; + }; + + config { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_sleep: qupv3_se13_spi_sleep { + mux { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 14 pin mappings */ + qupv3_se14_i2c_pins: qupv3_se14_i2c_pins { + qupv3_se14_i2c_active: qupv3_se14_i2c_active { + mux { + pins = "gpio55", "gpio56"; + function = "qup17"; + }; + + config { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep { + mux { + pins = "gpio55", "gpio56"; + function = "gpio"; + }; + + config { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se14_spi_pins: qupv3_se14_spi_pins { + qupv3_se14_spi_active: qupv3_se14_spi_active { + mux { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + function = "qup17"; + }; + + config { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se14_spi_sleep: qupv3_se14_spi_sleep { + mux { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + function = "gpio"; + }; + + config { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 15 pin mappings */ + qupv3_se15_i2c_pins: qupv3_se15_i2c_pins { + qupv3_se15_i2c_active: qupv3_se15_i2c_active { + mux { + pins = "gpio23", "gpio24"; + function = "qup18"; + }; + + config { + pins = "gpio23", "gpio24"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep { + mux { + pins = "gpio23", "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio24"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se15_spi_pins: qupv3_se15_spi_pins { + qupv3_se15_spi_active: qupv3_se15_spi_active { + mux { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + function = "qup18"; + }; + + config { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_sleep: qupv3_se15_spi_sleep { + mux { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 16 pin mappings */ + qupv3_se16_i2c_pins: qupv3_se16_i2c_pins { + qupv3_se16_i2c_active: qupv3_se16_i2c_active { + mux { + pins = "gpio181", "gpio182"; + function = "qup19"; + }; + + config { + pins = "gpio181", "gpio182"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se16_i2c_sleep: qupv3_se16_i2c_sleep { + mux { + pins = "gpio181", "gpio182"; + function = "gpio"; + }; + + config { + pins = "gpio181", "gpio182"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se16_spi_pins: qupv3_se16_spi_pins { + qupv3_se16_spi_active: qupv3_se16_spi_active { + mux { + pins = "gpio181", "gpio182", "gpio183", + "gpio184"; + function = "qup19"; + }; + + config { + pins = "gpio181", "gpio182", "gpio183", + "gpio184"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se16_spi_sleep: qupv3_se16_spi_sleep { + mux { + pins = "gpio181", "gpio182", "gpio183", + "gpio184"; + function = "gpio"; + }; + + config { + pins = "gpio181", "gpio182", "gpio183", + "gpio184"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 17 pin mappings */ + qupv3_se17_i2c_pins: qupv3_se17_i2c_pins { + qupv3_se17_i2c_active: qupv3_se17_i2c_active { + mux { + pins = "gpio43", "gpio44"; + function = "qup13"; + }; + + config { + pins = "gpio43", "gpio44"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se17_i2c_sleep: qupv3_se17_i2c_sleep { + mux { + pins = "gpio43", "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio43", "gpio44"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se17_spi_pins: qupv3_se17_spi_pins { + qupv3_se17_spi_active: qupv3_se17_spi_active { + mux { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + function = "qup13"; + }; + + config { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se17_spi_sleep: qupv3_se17_spi_sleep { + mux { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se17_4uart_pins: qupv3_se17_4uart_pins { + qupv3_se17_default_ctsrtsrx: + qupv3_se17_default_ctsrtsrx { mux { pins = "gpio43", "gpio44", "gpio46"; function = "gpio"; @@ -5184,7 +5045,7 @@ }; }; - qupv3_se13_default_tx: qupv3_se13_default_tx { + qupv3_se17_default_tx: qupv3_se17_default_tx { mux { pins = "gpio45"; function = "gpio"; @@ -5197,7 +5058,7 @@ }; }; - qupv3_se13_ctsrx: qupv3_se13_ctsrx { + qupv3_se17_ctsrx: qupv3_se17_ctsrx { mux { pins = "gpio43", "gpio46"; function = "qup13"; @@ -5210,7 +5071,7 @@ }; }; - qupv3_se13_rts: qupv3_se13_rts { + qupv3_se17_rts: qupv3_se17_rts { mux { pins = "gpio44"; function = "qup13"; @@ -5223,7 +5084,7 @@ }; }; - qupv3_se13_tx: qupv3_se13_tx { + qupv3_se17_tx: qupv3_se17_tx { mux { pins = "gpio45"; function = "qup13"; @@ -5236,5 +5097,140 @@ }; }; }; + + /* SE 18 pin mappings */ + qupv3_se18_i2c_pins: qupv3_se18_i2c_pins { + qupv3_se18_i2c_active: qupv3_se18_i2c_active { + mux { + pins = "gpio47", "gpio48"; + function = "qup14"; + }; + + config { + pins = "gpio47", "gpio48"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se18_i2c_sleep: qupv3_se18_i2c_sleep { + mux { + pins = "gpio47", "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio47", "gpio48"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se18_spi_pins: qupv3_se18_spi_pins { + qupv3_se18_spi_active: qupv3_se18_spi_active { + mux { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + function = "qup14"; + }; + + config { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se18_spi_sleep: qupv3_se18_spi_sleep { + mux { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 19 pin mappings */ + qupv3_se19_i2c_pins: qupv3_se19_i2c_pins { + qupv3_se19_i2c_active: qupv3_se19_i2c_active { + mux { + pins = "gpio27", "gpio28"; + function = "qup15"; + }; + + config { + pins = "gpio27", "gpio28"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se19_i2c_sleep: qupv3_se19_i2c_sleep { + mux { + pins = "gpio27", "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio28"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se19_spi_pins: qupv3_se19_spi_pins { + qupv3_se19_spi_active: qupv3_se19_spi_active { + mux { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + function = "qup15"; + }; + + config { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se19_spi_sleep: qupv3_se19_spi_sleep { + mux { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + trigout_a: trigout_a { + mux { + pins = "gpio141"; + function = "qdss_cti"; + }; + + config { + pins = "gpio141"; + drive-strength = <2>; + bias-disable; + }; + }; }; }; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 7486e049..d80de192 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -26,8 +26,8 @@ memory { device_type = "memory"; reg = <0 0 0 0>; }; aliases { - serial0 = &uart2; ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + serial0 = &qupv3_se12_2uart; }; cpus { @@ -966,21 +966,6 @@ qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; }; - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x00ac0000 0x6000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - - uart2: serial@a90000 { - compatible = "qcom,geni-debug-uart"; - reg = <0x00a90000 0x4000>; - interrupts = ; - status = "disabled"; - }; - }; - thermal_zones: thermal-zones { }; @@ -1832,3 +1817,9 @@ status = "ok"; }; #include "sa8195-thermal.dtsi" +#include "sa8195-qupv3.dtsi" +#include "sa8195-ssc-qupv3.dtsi" + +&qupv3_se12_2uart { + status = "ok"; +};