From 8889795873f2a67fa1474c5f3c3d33f25823ed94 Mon Sep 17 00:00:00 2001
From: Qingqing Zhou <qqzhou@qti.qualcomm.com>
Date: Wed, 25 May 2022 00:31:25 +0800
Subject: [PATCH 1/2] ARM: dts: msm: Add initial smmu dt for sdxbaagha

Add the apps smmu device.

Change-Id: Ic72cd7700a2460848fbde2d9b6919f524ce26e7d
---
 qcom/msm-arm-smmu-sdxbaagha.dtsi | 98 ++++++++++++++++++++++++++++++++
 qcom/sdxbaagha.dtsi              |  1 +
 2 files changed, 99 insertions(+)
 create mode 100644 qcom/msm-arm-smmu-sdxbaagha.dtsi

diff --git a/qcom/msm-arm-smmu-sdxbaagha.dtsi b/qcom/msm-arm-smmu-sdxbaagha.dtsi
new file mode 100644
index 00000000..7af56384
--- /dev/null
+++ b/qcom/msm-arm-smmu-sdxbaagha.dtsi
@@ -0,0 +1,98 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+	apps_smmu: apps-smmu@15000000 {
+		compatible = "qcom,qsmmu-v500";
+		reg = <0x15000000 0x40000>;
+		#iommu-cells = <2>;
+		#global-interrupts = <1>;
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		dma-coherent;
+
+		interrupts =    <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+
+		anoc_qtb: anoc_qtb@1670000 {
+			compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
+			reg = <0x1670000 0x1000>;
+			qcom,stream-id-range = <0x0 0x400>;
+			qcom,iova-width = <36>;
+			qcom,num-qtb-ports = <1>;
+		};
+
+		anoc_pcie_qtb: anoc_pcie_qtb@16d0000 {
+			compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
+			reg = <0x16d0000 0x1000>;
+			qcom,stream-id-range = <0x400 0x400>;
+			qcom,iova-width = <36>;
+			qcom,num-qtb-ports = <1>;
+		};
+	};
+
+	dma_dev {
+		compatible = "qcom,iommu-dma";
+		memory-region = <&system_cma>;
+	};
+
+	iommu_test_device {
+		compatible = "qcom,iommu-debug-test";
+
+		usecase0_apps {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x180 0x0>;
+		};
+
+		usecase1_apps_fastmap {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x180 0x0>;
+			qcom,iommu-dma = "fastmap";
+		};
+
+		usecase2_apps_atomic {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x180 0x0>;
+			qcom,iommu-dma = "atomic";
+		};
+
+		usecase3_apps_dma {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x180 0x0>;
+			dma-coherent;
+		};
+
+		usecase4_apps_secure {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x180 0x0>;
+			qcom,iommu-vmid = <0xa>; /* VMID_CP_PIXEL */
+		};
+	};
+};
diff --git a/qcom/sdxbaagha.dtsi b/qcom/sdxbaagha.dtsi
index c8139ae4..90325af1 100644
--- a/qcom/sdxbaagha.dtsi
+++ b/qcom/sdxbaagha.dtsi
@@ -206,3 +206,4 @@
 
 #include "sdxbaagha-pinctrl.dtsi"
 #include "sdxbaagha-dma-heaps.dtsi"
+#include "msm-arm-smmu-sdxbaagha.dtsi"

From e529cbbdf66d92324f3c0d6d518dcbc36247364d Mon Sep 17 00:00:00 2001
From: Qingqing Zhou <qqzhou@qti.qualcomm.com>
Date: Fri, 1 Jul 2022 17:43:26 +0800
Subject: [PATCH 2/2] ARM: dts: msm: Add secure buffer device for sdxbaagha

Allow clients to create secure memory.

Change-Id: I4cbec7098fcd881bea1b340171890e15377bbd27
---
 qcom/sdxbaagha.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/qcom/sdxbaagha.dtsi b/qcom/sdxbaagha.dtsi
index 90325af1..16654416 100644
--- a/qcom/sdxbaagha.dtsi
+++ b/qcom/sdxbaagha.dtsi
@@ -202,6 +202,10 @@
 			status = "disabled";
 		};
 	};
+
+	qcom,secure-buffer {
+		compatible = "qcom,secure-buffer";
+	};
 };
 
 #include "sdxbaagha-pinctrl.dtsi"