diff --git a/qcom/sdxpinn-rumi.dtsi b/qcom/sdxpinn-rumi.dtsi
index 47fd153c..3d49e578 100644
--- a/qcom/sdxpinn-rumi.dtsi
+++ b/qcom/sdxpinn-rumi.dtsi
@@ -87,3 +87,29 @@
 &APSS_OFF {
 	status = "nok";
 };
+
+&soc {
+	usb_nop_phy: usb_nop_phy {
+		compatible = "usb-nop-xceiv";
+	};
+
+	usb_emu_phy_0: usb_emu_phy@a784000 {
+		compatible = "qcom,usb-emu-phy";
+		reg = <0x0a784000 0x9500>;
+
+		qcom,emu-init-seq = <0x100000 0x20
+				     0x0 0x20
+				     0x000101F0 0x20
+				     0x100000 0x3c
+				     0x0 0x3c
+				     0x0010060 0x3c>;
+	};
+};
+
+&usb {
+	dwc3@a600000 {
+		usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>;
+		maximum-speed = "high-speed";
+		dr_mode = "peripheral";
+	};
+};
diff --git a/qcom/sdxpinn-usb.dtsi b/qcom/sdxpinn-usb.dtsi
new file mode 100644
index 00000000..a97213e7
--- /dev/null
+++ b/qcom/sdxpinn-usb.dtsi
@@ -0,0 +1,52 @@
+#include <dt-bindings/clock/qcom,gcc-sdxpinn.h>
+
+&soc {
+	usb: ssusb@a600000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0x0a600000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pwr_event_irq";
+
+		USB3_GDSC-supply = <&gcc_usb30_gdsc>;
+		clocks = <&gcc GCC_USB30_MASTER_CLK>,
+			<&gcc GCC_USB30_SLV_AHB_CLK>,
+			<&gcc GCC_USB30_MSTR_AXI_CLK>,
+			<&gcc GCC_USB30_MOCK_UTMI_CLK>,
+			<&gcc GCC_USB30_SLEEP_CLK>;
+		clock-names = "core_clk", "iface_clk",
+					"bus_aggr_clk", "utmi_clk",
+					"sleep_clk";
+
+		resets = <&gcc GCC_USB30_BCR>;
+		reset-names = "core_reset";
+
+		qcom,core-clk-rate = <200000000>;
+		qcom,core-clk-rate-hs = <66666667>;
+		qcom,default-bus-vote = <2>; /* use svs bus voting */
+		qcom,num-gsi-evt-buffs = <0x3>;
+		qcom,gsi-reg-offset =
+			<0x0fc /* GSI_GENERAL_CFG */
+			0x208 /* GSI_DBL_ADDR_L */
+			0x224 /* GSI_DBL_ADDR_H */
+			0x240 /* GSI_RING_BASE_ADDR_L */
+			0x25c /* GSI_RING_BASE_ADDR_H */
+			0x1a4>; /* GSI_IF_STS */
+		dwc3@a600000 {
+			compatible = "snps,dwc3";
+			reg = <0x0a600000 0xd93c>;
+			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x10>;
+			tx-fifo-resize;
+			maximum-speed = "super-speed-plus";
+			dr_mode = "otg";
+		};
+
+	};
+};
diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi
index 3ad072da..e9adfb06 100644
--- a/qcom/sdxpinn.dtsi
+++ b/qcom/sdxpinn.dtsi
@@ -661,6 +661,7 @@
 #include "sdxpinn-debug.dtsi"
 #include "sdxpinn-pinctrl.dtsi"
 #include "sdxpinn-pcie.dtsi"
+#include "sdxpinn-usb.dtsi"
 #include "sdxpinn-qupv3.dtsi"
 #include "msm-arm-smmu-sdxpinn.dtsi"
 #include "sdxpinn-dma-heaps.dtsi"