From 8de59096fcf972b8f0ca35a2586a40d8497d4c23 Mon Sep 17 00:00:00 2001
From: Santoshkumar Zalake <szalake@qti.qualcomm.com>
Date: Mon, 9 May 2022 20:28:05 +0530
Subject: [PATCH] dt-bindings: Add GNSS SiRF bindings to devicetree

Add GNSS SiRF bindings snapshot to the devicetree

Change-Id: I38d740b6bfa76e8fcd195d8d32501bfad5373a03
---
 bindings/soc/qcom/qcom,gnss_sirf.txt | 47 ++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 bindings/soc/qcom/qcom,gnss_sirf.txt

diff --git a/bindings/soc/qcom/qcom,gnss_sirf.txt b/bindings/soc/qcom/qcom,gnss_sirf.txt
new file mode 100644
index 00000000..8965e432
--- /dev/null
+++ b/bindings/soc/qcom/qcom,gnss_sirf.txt
@@ -0,0 +1,47 @@
+Binding for SIRF GNSS receiver control driver
+GPIO pins are toggled to control GNSS receiver power states either to
+wake it from sleep or put receiver into sleep mode
+
+Required properties:
+- compatible: must be "qcom,gnss_sirf"
+- #gpio-pins:
+      0: GPIO 18
+      1: GPIO 87
+
+Example:
+	ss5_pwr_ctrl0 {
+		compatible = "qcom,gnss_sirf";
+		pinctrl-0 = <&ss5_pwr_ctrl_rst_on>;
+		ssVreset-gpio = <&tlmm 87 1>;
+		ssVonoff-gpio = <&tlmm 18 1>;
+	};
+
+	ss5_pwr_ctrl_pins: ss5_pwr_ctrl_pins {
+		ss5_pwr_ctrl_rst_on: ss5_pwr_ctrl_rst_on {
+			mux {
+				pins = "gpio87", "gpio18";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio87", "gpio18";
+				drive-strength = <16>; /* 16 mA */
+				bias-pull-up;
+				output-high;
+			};
+		};
+
+		ss5_pwr_ctrl_rst_off: ss5_pwr_ctrl_off {
+			mux {
+				pins = "gpio87", "gpio18";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio87", "gpio18";
+				drive-strength = <16>; /* 16 mA */
+				bias-pull-up;
+				output-high;
+			};
+		};
+	};