From 8de7322c630bf24a00dca2e8d8b91e086ca70f8e Mon Sep 17 00:00:00 2001
From: Swetha Chikkaboraiah <c_schikk@qti.qualcomm.com>
Date: Thu, 29 Sep 2022 16:02:05 +0530
Subject: [PATCH] ARM: dts: msm: set ddr bus-width to 8

Set DDR bus-width to 8 for khaje.

Change-Id: If407376ada9f69e26ece314621fdbdad74e01c32
---
 qcom/khaje.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi
index b79d978e..a3dac1fb 100644
--- a/qcom/khaje.dtsi
+++ b/qcom/khaje.dtsi
@@ -3502,7 +3502,7 @@
 		qcom_ddr_dcvs_hw: ddr {
 			compatible = "qcom,dcvs-hw";
 			qcom,dcvs-hw-type = <0>;
-			qcom,bus-width = <4>;
+			qcom,bus-width = <8>;
 			qcom,freq-tbl = <&ddr_freq_table>;
 
 			ddr_dcvs_sp: sp {