From 8e1ae70c084dec40561bb359e9bdff6d027ab47a Mon Sep 17 00:00:00 2001 From: Prashanth K Date: Tue, 19 Apr 2022 12:09:47 +0530 Subject: [PATCH] ARM: dts: msm: Add HS USB PHY support in Cinder Add HS USB Phy node in cinder usb for supporting HS mode. some voltage regualtors are different for RU & DU, hence the voltage regulators are added in corresponding target DT files. Change-Id: I3237ef28f99bf9f01495363f19013da1af3c8013 --- qcom/cinder-du.dtsi | 8 ++++++++ qcom/cinder-ru.dtsi | 8 ++++++++ qcom/cinder-rumi.dtsi | 4 ---- qcom/cinder-usb.dtsi | 21 +++++++++++++++++++++ 4 files changed, 37 insertions(+), 4 deletions(-) diff --git a/qcom/cinder-du.dtsi b/qcom/cinder-du.dtsi index e157d26e..7adbeef7 100644 --- a/qcom/cinder-du.dtsi +++ b/qcom/cinder-du.dtsi @@ -148,3 +148,11 @@ reg = <0x0 0xc3200000 0x0 0x12c00000>; }; }; +&soc { + usb2_phy0 { + vdd-supply = <&L8A>; + vdda18-supply = <&L14A>; + vdda33-supply = <&L2A>; + qcom,vdd-voltage-level = <0 888000 920000>; + }; +}; diff --git a/qcom/cinder-ru.dtsi b/qcom/cinder-ru.dtsi index 7d9b32b1..ae98a702 100644 --- a/qcom/cinder-ru.dtsi +++ b/qcom/cinder-ru.dtsi @@ -143,3 +143,11 @@ reg = <0x0 0xb4e00000 0x0 0x3200000>; }; }; +&soc { + usb2_phy0 { + vdd-supply = <&L5A>; + vdda18-supply = <&L14A>; + vdda33-supply = <&L2A>; + qcom,vdd-voltage-level = <0 880000 920000>; + }; +}; diff --git a/qcom/cinder-rumi.dtsi b/qcom/cinder-rumi.dtsi index 5e6090b9..9ab35f06 100644 --- a/qcom/cinder-rumi.dtsi +++ b/qcom/cinder-rumi.dtsi @@ -28,10 +28,6 @@ qcom,tcsr-not-supported; }; - usb_nop_phy: usb_nop_phy { - compatible = "usb-nop-xceiv"; - }; - usb_emu_phy: phy@a784000 { compatible = "qcom,usb-emu-phy"; reg = <0x0a784000 0x9500>; diff --git a/qcom/cinder-usb.dtsi b/qcom/cinder-usb.dtsi index 875910a1..3da74151 100644 --- a/qcom/cinder-usb.dtsi +++ b/qcom/cinder-usb.dtsi @@ -48,6 +48,7 @@ qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; dma-coherent; + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; interrupts = ; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; @@ -60,4 +61,24 @@ maximum-speed = "super-speed-plus"; }; }; + + /* USB port related High Speed PHY */ + usb2_phy0: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x120>, + <0x088e2000 0x4>; + reg-names = "hsusb_phy_base", + "eud_enable_reg"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB2_CLKREF_EN>; + clock-names = "ref_clk_src", "ref_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; };